A Comparative Study On Various Adders

A REPORT Submitted by

PEEYUSH PASHINE(2011H140033H)

M.E. (EMBEDDED SYSTEMS) BIRLA INSTITUTE OF TECHNOLOGY AND SCINCE PILANIHYDERABAD

TABLE OF CONTENTS 1)Introduction 2)Types of adders 2.1)1 bit adder 2.11)Half adder/subs tractor 2.111)Design 2.112) Pros and Cons 2.113)Verilog Code 2.12)Full adder 2.121)Design(adder) and sub tractor 2.122) Pros and Cons 2.123)Verilog Code 2.2)Ripple Carry adder 2.21)Design(adder and sub tractor) 2.22) static adder circuit 2.23) Pros and cons 2.24)Some interpretation about carry 2.25)Pros and cons 2.26) Manchester carry chain implementation 2.27) Pros and Cons 2.28)Verilog Code 2.3)Carry look ahead adder 2.31)Design 2.32) Pros and Cons 2.33)Verilog Code 2.4) Carry select/skip adder 2.41)Design 2.42) Pros and Cons 2.43)Verilog Code 2.6)Carry save adder 2.61)Design 2.62) Pros and Cons 2.63)Verilog Code

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2.7)Binary tree adder 2.71)Group PG logic 2.72)Design 2.73)Pros and Cons 3) Comparison between adders and conclusion 4) Bibliography

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LIST OF FIGURES 1)Fig1:-half 1 bit adder 2)Fig2:- full 1 bit adder 3)Fig3:-half adder design 4)Fig4:-full adder design 5)Fig5:-adder with sub tractor 6)Fig6:-ripple carry adder 7)Fig7:-adder and sub tractor(ripple) 8)Fig8:- static adder circuit(cmos) 9)Fig9:- Manchester carry chain 10)Fig10:- Manchester circuit with pass transistor 11)Fig11:- rtl diagram ripple carry adder circuit 12)Fig12:-propagate and generate adder design 13)Fig13:-carry look ahead block diagram 14)Fig14:-carry look ahead design circuit 15)Fig15:-CLA rtl diagram

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16)Fig16:-carry skip adder block diagram 17)Fig17:-carry skip adder circuit(Manchester) 18)Fig18:- carry skip adder critical path 19)Fig19:- carry skip adder rtl 20)Fig20:-carry save adder 21)Fig21:-binary tree functioning 23

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1)Introduction :- In digital electronics adder is a digital circuit that performs addition of numbers, these can be classified into 1 bit adders and multi bit adders. Further 1bit adders are categorized in half adders and full adders. These are not only used in ALU but also in memory for calculating addresses, table indices and many more. 2)Types of adders :-There are several type of adders as mentioned further below 2.1) 1 bit adder:- Consider 2 binary variables a and b, which can have 4 combinations when adding i.e. 0+0=0, 0+1=1,1+0=1,1+1=10 , here the last result is binary 10,which can of course can not exceed of 1 bit, here concept of carryout comes into the picture.

Fig1

Fig2

2.11)Half adder:- A simple 1 bit adder, with 2 binary inputs is known as half adder. Its sum and carryout expression can be given as 2.111)Design A Sum= a XOR b Carryout= a AND b 0 0 1 1 B 0 1 0 1 sum 0 1 1 0 Cout 0 0 0 1

Fig 3 2.112)Pros and Cons:-half adder is useful for adding two 1 bit numbers only.Delay generated is 1 unit AND-OR delay. carry is available earlier than sum. 2.113)Verilog code:module half adder(input a, input b ,output sum, output carry) { assign sum=a^b; assign carry =a&b; end module}

2.12)Full adder:- When 3 single bits are added in a row, adder known as a full adder. Sum and carry out expression can be given as below

A 0 0

b 0 0 1 1 0 0 1 1

cin 0 1 0 1 0 1 0 1

sum 0 1 1 0 1 0 0 1

cout 0 0 0 1 0 1 1 1

2.121)Design :Sum =a XOR b Carry out=a AND b + b AND c + a AND c

0 0 1 1 1 1

Fig 4

Fig 5

The above figure shows how an adder and sub tractor can be implemented in the same module, for adder ci=0,and for sub tractor ci=1,binv is selected ,thus computing 2s complement and adding to the ai input. 2.122)Pro and Cons :-when implementing adder and sub tractor both in single module, cin should be high, which states that, only half adder/sub tractor can be implemented by this. Delay generated is 2 unit AND-OR delay for both the sum and carry. 2.123)Verilog code:module fulladder(input a, input b, input cin, output sum, output cout) { assign sum=a^b^cin; assign cout=a&b+b&c+a&c; end module } 2.2)Ripple Carry adder:- now when n bit adders are if made using 1 bit adders(n 1 bit adders, where for 1 bit addition fulladders and halfadder is used(half adder for 1st stage, as often carry in at for 1st stage remains zero and fulladders for remaining of the stages)we can say carry is rippled through stages. This is known as carry ripple adder.

2.21)Design:-

Fig 6 The above figure is a carry ripple adder for 4 bit addition and the below figure shows how a subs tractor can be represented as n bit rippled subs tractor. For subs tractor operation ci=1, 2nd input bi is complemented, so Subtraction=ai-bi=ai+bi+1

Fig 7

2.22)Static adder circuit :- The carry and sum expression for the full adder can be again written as Carry out=ai.bi+(ai+bi)ci Sum= ai.bi.ci+Cout (ai+bi+ci)

Fig 8 The above figure is a static cmos representation of full adder. 2.23)Pros and Cons:-It used 28 transistor for the implementation of full adder, also Cout is available in complimented form, which again need to be inverted using cmos inverter to get the Cout in non complemented form.

2.24)Some important interpretation about carry:- From the full adder truth table we can easily interpret , carry out is killed or deleted when both of the inputs to the fulladder are zero, irrespective of carry in whether it is 1 or 0.The 2nd observation is carry which is feed by the previous stage propagates to the next stage when either of the inputs to the full adder at present stage is 1(high).The another observation states carry is generated at present stage and will be feed to next stage when both of the inputs to the full adders are high. Hence in the expression cout=ai.bi+(ai+bi).ci, 1st term tells about carry generation at the present stage, and 2nd term states about carry propagation to the next stage(look we used XOR gate there in the design of full adder, in place of or gate in 2nd term here, which gives is the original carryout expression, just to avoid use of extra OR gate in design, as it does effect either XOR gate or OR gate is used for carry out since the only difference caused between 2 gates is for when both of the inputs are high ,that even is compensated, because we consider carry generation by 1st term in above expression to rise carry out high. 2.25)Pros and cons:-however 1 OR gate for propagation computation is used for ease of access, and to minimize the delay in n bit adder. It induce more hardware compared to the original n bit full adder implementation. 2.26)Manchester carry chain implementation:- Using cmos the carry propagation and generation condition is achieved. when pi(propagate) signal is high for particular stage(here i stands for n stages in ripple carry adder, i<=n).carry in(ci) is passed to cout, otherwise either carry is generated if Gi signal is high or carry is deleted if di signal is high(di=ai.bi).Now need of delete signal can be

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avoid

when

using

precharge

transistor

signal

is

used.

Fig 10 In the above figure initially =1,it pre -charges and for the kth stage(0<k<n) carry is either propagated ,generated based upon pi and gi signal respectively, otherwise carry is killed. 2.27)Pro and cons:-Use of Manchester carry chain for propagation and generation of c out, reduced complexity and avoids the need for more multiplexers in hardware implementation.

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2.28)Verilog Code:module fulladd(a ,b, carryin, sum, carryout); input a, b, carryin; /* add these bits*/ output sum, carryout; /* results */ assign {carryout, sum} = a + b + carryin; /* compute the sum and carry */ endmodule module nbitfulladd(a,b,carryin,sum,carryout); input[7:0] a, b; /* add these bits */ input carryin; /* carry in*/ output [7:0] sum; /* result */ output carryout; wire [7:1] carry; /* transfers the carry between bits */ fulladd a0(a[0],b[0],carryin,sum[0],carry[1]); fulladd a1(a[1],b[1],carry[1],sum[1],carry[2]); fulladd a2(a[2],b[2],carry[2],sum[2],carry[3]); fulladd a3(a[3],b[3],carry[3],sum[3],carryout); endmodule

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Fig 11 2.3)Carry look ahead adder:- As discussed in ripple carry adder, the significant delay produced due to ripple operation is a trade off. this can be minimized when carry in to all stages are computed initially itself, as it will minimize the wait for carry at every stage in a n bit adder, hence sum and carryout expression can be re written as 2.31)Design:Sum=ai XOR bi XOR Ci Carry out=Gi+Pi.Ci, where Pi=ai XOR bi and Gi=ai.bi.

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Fig 12 Now further delay due to XOR gate can be mimized by 1 unit, if Pi=ai+bi is used and sum computation is accomplished using XOR gate,hence inclusion of one OR gate.

Fig 13

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Fig 14 For the above figure sum and carry expressions can be written as Co=Go+PoCin

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C1=G1+P1Co C2=G2+P2C1 C3=G3+P3C2 C3=G3+P3(G2+P2(G1+P1(Go+PoCin))) C3=G3+P3G2+P3G2G1+P3P2P1G0+P3P2P1PoCin 2.32)Pros and Cons:- Delay generated in whole n bit adder here is 5 unit, 1 unit AND or OR delay from the 1st stage.2 unit delay AND+OR in 2nd stage and 2 unit AND+OR delay, in 3rd stage of sum computation using XOR gates. Carries are computed for all the stages ,as long as inputs adder,but complexity of hardware increases,here architecture may be easier compared to ripple carry adder but no. of fan ins to to gates,and also wire length for inputs to reachout for gates increases.so as the no of bits goes on increasing the benefits of carry look ahead adder diminishes, however it is better than ripple carry adder upto12 bits addition operation. 2.33)Verilog Code:module sum(a,b,carryin,result); input a, b, carryin; /* add these bits*/ output result; /* sum */ assign result = a ^ b ^ carryin; /* compute the sum */ endmodule

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module carry_block(a,b,carryin,carry); input [3:0] a, b; /* add these bits*/ input carryin; /* carry into the block */ output [3:0] carry; /* carries for each bit in the block */ wire [3:0] g, p; /* generate and propagate */ assign g[0] = a[0] & b[0]; /* generate 0 */ assign p[0] = a[0] ^ b[0]; /* propagate 0 */ assign g[1] = a[1] & b[1]; /* generate 1 */ assign p[1] = a[1] ^ b[1]; /* propagate 1 */ assign g[2] = a[2] & b[2]; /* generate 2 */ assign p[2] = a[2] ^ b[2]; /* propagate 2 */ assign g[3] = a[3] & b[3]; /* generate 3 */ assign p[3] = a[3] ^ b[3]; /* propagate 3 */ assign carry[0] = g[0] | (p[0] & carryin); assign carry[1] = g[1] | p[1] & (g[0] | (p[0] & carryin)); assign carry[2] = g[2] | p[2] & (g[1] | p[1] & (g[0] | (p[0] & carryin))); assign carry[3] = g[3] | p[3] & (g[2] | p[2] & (g[1] | p[1] & (g[0] | (p[0] & carryin)))); endmodule module carry_lookahead_adder(a,b,carryin,sum,carryout); input [3:0] a, b; /* add these together */

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input carryin; output [3:0] sum; /* result */ output carryout; wire [4:1] carry; /* intermediate carries */ /* build the carry-lookahead units */ carry_block b0(a[3:0],b[3:0],carryin,carry[4:1]); /* build the sum */ sum a0(a[0],b[0],carryin,sum[0]); sum a1(a[1],b[1],carry[1],sum[1]); sum a2(a[2],b[2],carry[2],sum[2]); sum a3(a[3],b[3],carry[3],sum[3]); endmodule

Fig 15

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2.4)Carry skip/select adder:- In binary system, carry either can be 0 or 1.only two possibility of value provides feasibility for choosing between two. So if there is a mechanism to select carry, or better say, skipping carry through several stages, then delay minimization can be better obtained. The expression for C3 for 4 bit adder, contains term P3P2P1PoCin, all the signals are computed at initial stage and are available to user, the term signifies if there is a carry generation at 1st stage, and is propagated till last stage, the worst case delay can be avoided if propagated carry is selected at initial stage itself, and skipped through remaining stages. 2.41)Design:-

Fig 16 When computing BP=P1P2P3Po,carry is selected from 1st stage, for n bit adders,we can divide n bits into stages of m bits, where carry is rippled through 1st m bits, and then it is skipped, in this manner,delay can be minimized.

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Fig 17 The above figure shows Manchester carry select implementation, here either carry is generated or propagated in chain, implemented using nmos.

Fig 18 Also from the above figure we interpret till carry is selected either 0 or 1, by the multiplexer, computation for selection of carry from the next stage is already available.

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2.42)Pros and Cons:-complexity may increase due to multiplexer operation, however multiplexers can be implemented by simple cmos inverter by selection of proper inputs to mux. Critical path is shown in gray color. 2.43)Verilog Code:module fulladd_p(a,b,carryin,sum,carryout,p); input a, b, carryin; /* add these bits*/ output sum, carryout, p; /* results including propagate */ assign {carryout, sum} = a + b + carryin; /* compute the sum and carry */ assign p = a | b; endmodule module carryskip(a,b,carryin,sum,carryout); input [7:0] a, b; /* add these bits */ input carryin; /* carry in*/ output [7:0] sum; /* result */ output carryout; wire [8:1] carry; /* transfers the carry between bits */ wire [7:0] p; /* propagate for each bit */ wire cs4; /* final carry for first group */

fulladd_p a0(a[0],b[0],carryin,sum[0],carry[1],p[0]);

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fulladd_p a1(a[1],b[1],carry[1],sum[1],carry[2],p[1]); fulladd_p a2(a[2],b[2],carry[2],sum[2],carry[3],p[2]); fulladd_p a3(a[3],b[3],carry[3],sum[3],carry[4],p[3]); assign cs4 = carry[4] | (p[0] & p[1] & p[2] & p[3] & carryin); fulladd_p a4(a[4],b[4],cs4, fulladd_p a5(a[5],b[5],cs4, fulladd_p a6(a[6],b[6],cs4, fulladd_p a7(a[7],b[7],cs4, sum[4],carry[5],p[4]); sum[5],carry[6],p[5]); sum[6],carry[7],p[6]); sum[7],carry[8],p[7]);

assign carryout = carry[8] | (p[4] & p[5] & p[6] & p[7] & cs4); endmodule

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Fig 19 2.5)Carry save adder:-when n bit adder is implemented, still carry is rippled to the next stage, of same row, even though inputs to the lower next stage is ready, but kept in wait state, until the sum and carry output didnt come from the above stage. This induces delay, now it can be optimized, if carry out is passed diagonally to the lower next stage,instead of rippling to the next stage of same row. Carry computation is not performed, but it is saved upto last row ,where the results are obtained finally, in the last bottom row, carry is rippled however, but it significantly reduce the amount of delay occurred due to rippling operation. 2.51)Design:-

2.52)Pros and Cons:- This adder is used in array multiplier ,delay is reduced significantly compared to ripple carry adder, for n*n multiplier delay elapsed when ripple carry adders are used in 2n,where as if carry save adders are used worst case delay is n+3 units. carry save adders are used in binary tree adders also.

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2.6)Binary tree adder:-Understanding binary tree adder requires concepts of group PG logic ,which is explained below. 2.61)Group PG logic:- The sum and carry expression for full adder in terms of propagate and generate signal are written as Sum=ai XOR bi XOR Ci Carry out=Gi+Pi.Ci, where Pi=ai XOR bi and Gi=ai.bi. Also for n bit adder carry out for nth stage(let here n=4) is given as C3=G3+P3G2+P3G2G1+P3P2P1G0+P3P2P1PoCin We can write P=PoP1P2P3 and G= G3+P3G2+P3G2G1+P3P2P1G0 Hence C3=G+PCin 2.62)This concept is used in tree adder shown below

Fig 20

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2.63)Pros and Cons:-Architecture is easy when group PG logic is used but complexity during implementation increases. 3)Comparison among adders and conclusions:- All the adders for 1bit addition uses full adder operation,also for most of the adders,performance in terms of power and delay is similar upto 4 bits. Carry look ahead adder reduces the delay compared to ripple carry adder but as the adder size increases complexity increases also,fan in to the gates increases.Delay of the circuit depends upon,how many gates are connected in series and delay of a gate depends upon no of fan ins, so the later term dominates as adder size increases in carry look ahead adder. In static adder implementation using cmos, if inverted inputs are applied then need of cmos inverter is vanished and less no. of transistors are required.For the carry select adder, significant amount of time can be utilized if bit size carry selection are progressively increased.

4)Bibliography :1) cmos vlsi design book by neil weste 2) cmos vlsi design book by k l kishore 3) http://en.wikipedia.org/wiki/Adder_(electronics) 4) http://www.cs.umd.edu/class/sum2003/cmsc311/Notes/Comb/adder.html 5) http://en.wikipedia.org/wiki/Carry-lookahead_adder

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