Group A Null Convention Logic

1. Ternary FIR Filter design using Null Convention Logic

Description The semiconductor industry has long know that it faces a perfect storm of technical challenges *1+ encompassing excessive power consumption per unit area [2], [3], the increasing dominance of connecting wires in circuit delays, a greater spread of transistor characteristics, and extreme difficulties with synchronous timing closure and clock distribution exponential increase in device complexity limits the ability of designers to successfully create a product that works. To address this problem requires flexible logic platforms that can reliably deliver high performance at low power and with low cost of design. Clockless, or asynchronous architectures offer one potential solution. Although many asynchronous techniques (e.g. [4]) have been proposed to eliminate the problems associated with global clock distribution, none can be considered to have been commercially successful to date. One example of an asynchronous methodology is NULL Convention Logic (NCL) [5], [6], a quasi-delay insensitive (QDI) technique that exhibits robust behaviour in the face of wide component variability and power supply scaling. Recently, RMIT University Melbourne researchers have successfully introduced a new generation of SWL techniques (often single bit) that can be used to perform general-purpose DSP functions. These new single-bit systems require simpler hardware implementation while still offer equivalent performance as multi-bit systems. Intensive work was done to justify this where the area-power characteristics of the single-bit technique have been extensively demonstrated using FPGA implementations [7-10], where a single-bit Ternary FIR filter (Fig. 1) was successful designed to operate at clock rates in excess of 400MHz. The filter will easily handle a 6MHz video stream at an Over Sampling Ratio (OSR) of 64 while occupying small area, around 5% of the target FPGA (i.e. Stratix IV).

Fig. 1. Single-bit Ternary FIR filter (adapted from [10]).

Fig. 2. Block diagram of a ternary FIR filter (adapted from [10]).

The single-bit ternary FIR-like filter (SBTFF) which was first proposed in [10] was designed and mapped to a target FPGA. The filter as shown in Fig. 1 consists of a ternary filter and a Sigma Delta Modulator (M). The ternary filter (Fig. 2) uses coefficients from the set {+1, 0, -1} instead of {+1, 1} as in the binary case, which will exhibit a higher Signal to Quantization Noise Ratio (SQNR). Mathematically the FIR filter output can be described by a convolution of the ternary taps and the input signal . If M is the filter order, then the filter output is given by: { }

Multi-bit signals output from the ternary FIR filter will then be encoded into single-bit format by the one-bit M modulator. The order of a single-bit filter is directly related to the order of the Over Sampling Ratio. Thus the architecture can be seen to be highly regular and locally interconnected. It is also capable of almost completely pipelined operation, gaining very high throughput at the expense of latency. These characteristics make it suitable for implementation in a QDI technology such as NCL as the local connectivity characteristics make it easier to meet the few asynchronous timing constraints. This research will extend the use of SWL DSP algorithms into an asynchronous platform based on NCL logic. A number of NCL cells will be first designed and implemented using commercial EDA tools to prepare for the NCL platform. Then, the FIR filter will be designed and mapped into the platform and verified. It is expected that the performance (power, speed) of new design will be significantly improved in compared with results from FPGA and synchronous ASIC implementations. Results from the work can help encourage the asynchronous paradigm into the future. Activities 1. Literature review 2. NCL cells design (transistor-level and physical level) 3. FIR filter design 4. Design verification and evaluation 5. Modification and improvement References
[1] (2007). International Technology Roadmap for Semiconductors . Available: http://www.itrs.net/Links/2007ITRS/Home2007.htm

[2] C. McNairy and R. Bhatia, "Montecito: A Dual-Core, Dual-Thread Itanium Processor," IEEE Micro, vol. 25, pp. 10-20, March/April 2005. [3] P. M. Kogge, K. Bergman, S. Borkar, D. Campbell, W. Carlson, W. Dally, M. Denneau, P. Franzon, W. Harrod, K. Hill, J. Hiller, S. Karp, S. Keckler, D. Klein, R. Lucas, M. Richards, A. Scarpelli, S. Scott, A. Snavely, T. Sterling, R. S. Williams, and K. Yelick. (2008). ExaScale Computing Study: Technology Challenges in Achieving Exascale Systems. Available: www.cse.nd.edu/Reports/2008TR-2008-13.pdf . [4] P. E. Gronowski, W. J. Bowhill, R. P. Preston, M. K. Gowan, and R. L. Allmon, "High-Performance Microprocessor Design," IEEE Journal of Solid-State Circuits, vol. 33, pp. 676 - 686, 1998. TM [5] K. M. Fant and S. A. Brandt, "NULL Convention Logic : a complete and consistent logic for asynchronous digital circuit synthesis," in Proceedings of International Conference on Application Specific Systems, Architectures and Processors, ASAP 96. , 1996, pp. 261-273. [6] Karl M. Fant and Scott A. Brandt, "Null Convention Logic System," 5,305,463, 1994. [7] T. D. Memon, P. Beckett, and Z. M. Hussain, "Analysis and Design of a Ternary FIR Filter using Sigma Delta Modulation," presented at the International Symposium on Computing, Communication, and Control (ISCCC 2009), Singapore, 2009. [8] T. D. Memon, P. Beckett, and A. Z. Sadik, "Analysis and Design of a Ternary FIR Filter using Sigma Delta Modulation, accepted for publication 19 October, 2009," presented at the IEEE International Multitopic Conference (INMIC 2009), Islamabad, Pakistan, 2009. [9] T. D. Memon, P. Beckett, and A. Z. Sadik, "Performance-Area Tradeoffs in the Design of a Short Word Length FIR Filter, accepted for publication 19 October, 2009," presented at the International Conference On MEMS NANO And Smart Systems (ICMENS 2009), Dubai, UAE, 2009. [10] T. D. Memon, P. Beckett, and A. Z. Sadik, "Efficient Implementation of Ternary SDM filters using Stateof-the-art FPGA, accepted for publication 19 October, 2009," presented at the IEEE International Multitopic Conference (INMIC 2009), Islamabad, Pakistan, 2009.

2. Design of a Null Convention Logic FPGA congurable logic block (CLB)

Description Asynchronous logic design in general and Null Convention Logic (NCL) technology in specific currently encounters many difficulties due to the lack of support from the industry and commercial EDA vendors who still favour synchronous logic design. While waiting NCL-based ASIC approach develop, there are attempts to build a NCL-based FPGA that can be used to implement digital circuits with short time-to-market and smaller design effort. Success in building such FPGA will definitely help encourage the wide adoption of NCL-based into the future. Due to the difference in the way NCL gates are constructed in compared with conventional static CMOS [1], NCL circuits cannot be mapped directly to conventional FPGA without any compromise performance. Therefore, there is a need to implement a new FPGA structure that fits NCL structure from the scratch. Researchers from [2-4] have successfully developed logic elements and then finished congurable logic block (CLB) structure for NCL on both semi-static and static approaches using the 1.8-V, 180-nm TSMC CMOS process. However, the CLB has not been optimised for area and power yet. Also, the design process was done using Mentor Graphics tools provided at the university. Extension the work to other platforms (e.g. Cadence and Synopsys tools) hence makes it hard to be adapted widely. In this project, we aim to implement the NCL-based CLB on Cadence and Synopsys platforms with more focus on physical design of the block. Some more investigations on CLB structure itself will be expected to be done. Activities 1. Literature Review 2. CLB design using Custom Design Flow (Schematic Design -> Simulation -> Layout ) 3. Design test circuits. 4. Evaluation and Optimisation References 1. NCL book http://www.morganclaypool.com/doi/abs/10.2200/S00202ED1V01Y200907DCS023 2. http://www.ndsu.edu/pubweb/~scotsmit/Smith_FPGA_TVLSI.pdf 3. http://www.ndsu.edu/pubweb/~scotsmit/Smith_semi_static_FPGA.pdf 4. http://www.ndsu.edu/pubweb/~scotsmit/Smith_static_FPGA.pdf

3. ASIC implementation using Null Convention Logic (NCL)

Description Asynchronous design is expected to become a potential replacement for synchronous design techniques by ITRS [1] due to many advantages such as small effort on clock design, high performance and ability to work with harsh environment. It is argued that when synchronous techniques hit their limitations in term of clock frequency and supreme complex design methods, asynchronous will be matured enough to put in use. However every major industrial shift requires a lot of efforts form many stakeholders (e.g. design houses, EDA vendors, academics) and is a time consuming processes. Currently, asynchronous design still receive very limited supports from industrial design companies as well as from EDA vendors. Therefore, we only see attempts from few companies or academic researchers to work in this field. Among some asynchronous approaches, Null Convention Logic (NCL) [2] recently has been received many attentions. Startups such as [3] [4] have been working with NCL and attempt to make the technology strong and ready for the major changes in near future. Academics at [5] have been working actively on many aspects of NCL and try to bring NCL into engineering curriculum at their universities [6] with some initial positive results. The common design method for NCL is full custom design where every designs were done from scratch. The main reason for this is the lack of sufficient EDA tools dedicated for asynchronous design, the most essential requirements in modern VLSI design. Some have suggested to build NCLbased FPGA [7] so these can be used later to widely spread the usage of NCL. However, there might take quite long time to make this approach complete. Another approach is take advantage of existing EDA tools for synchronous tools and then make asynchronous design compatible with these tools. For example, UNCLE (Unified NULL Convention Logic Environment) [8] logic synthesis tool for NCL has been developed to work with commercial tools such as Design Compiler from Synopsys to produce NCL gate-level net list from RTL description as well as perform gate-level simulation using Synopsys VCS. The results from the work actually has encourage researchers to keep working in such approach to move towards more automatic flow for NCL design. In this project, we aim to develop the familiarity with the ASIC design flow for NCL based on available commercial tools and self-developed tools. Some designs (e.g. simple video processing algorithms) will be developed from RTL to physical design to validate the efficiency of the flow. Activities 1. Literature Review 2. ASIC Design flow (RTL design -> simulation -> synthesis -> P&S -> STA) 3. Evaluation and Optimisation References
1. 2. (2007). International Technology Roadmap for Semiconductors . Available: http://www.itrs.net/Links/2007ITRS/Home2007.htm Karl M. Fant and Scott A. Brandt, "Null Convention Logic System," 5,305,463, 1994.

3. http://www.eetimes.com/document.asp?doc_id=1172662 4. http://wavesemi.com/ 5. http://www.ndsu.edu/pubweb/~scotsmit/CCLI_async.html

6. http://www.ndsu.edu/pubweb/~scotsmit/CCLI_poster2011.pdf 7. http://www.ndsu.edu/pubweb/~scotsmit/Smith_FPGA_TVLSI.pdf 8. http://www.ndsu.edu/pubweb/~scotsmit/uncle_async_12.pdf

Group B FPGA Implementation of Short Word Length DSP algorithms

4. Implementation of SWL DC Blocking 5. Implementation of SWL Comb Filter
Description (for both 4 -5) The rapid advances in Very Large Scale Integration (VLSI) have made it possible to implement fast and efficient Digital Signal Processing (DSP) algorithms in hardware. The trend enables the production of high performance, small area and low power consumption devices. Among many challenges remained the existing of large number of multiplication stages is identified as the main cause to make DSP algorithms hardware implementation very complex. In last decade, Short Word Length (SWL) processing has proved promising technique in offering DSP applications with similar performance as conventional multi-bit systems but with low complexity [7]. Recently, RMIT University Melbourne researchers have invented a new generation of SWL techniques (often single bit) that can be used to perform general-purpose DSP functions, including classical and adaptive filtering. The key advantage of single-bit systems is that they do not require complex integer multiplication hardware [1-2] due to the fact that arithmetic on single-bit signals is much simpler than on multi-bit signals. The area-power characteristics of the single-bit technique have been extensively demonstrated using FPGA implementations [3-5], where a single-bit Ternary FIR filter (Fig. 1) was successful designed to operate at clock rates in excess of 400MHz. The filter will easily handle a 6MHz video stream at an Over Sampling Ratio (OSR) of 64 while occupying small area, around 5% of the target FPGA (i.e. Stratix IV).

Fig. 1. Single-bit Ternary FIR filter (adapted from [1]).

The above work will be extended into the implementation of DSP applications using SWL filter on FPGA platform. We will implement two applications suggested in [8]: comb filter and DC-blocker. It is expected that the performance of these two applications will outperform the conventional approach using multi-bit alternative. It is expected also from the work, the full understanding of how to compare effectively an application in two different approaches. Activities 1. Literature Review 2. System Modelling for Simulation (Using Matlab) 3. FPGA implementation 4. Evaluation and Optimisation

References [1] A. C. Thompson, P. O'Shea, Z. M. Hussain, and B. R. Steele, "Efficient Single-Bit Ternary Digital Filtering Using Sigma-Delta Modulator," IEEE Signal Processing Letters vol. 11, pp. 164-166, February 2004. A. C. Thompson, Z. M. Hussain, and P. O'Shea, "A Single-Bit Narrow-band Bandpass Digital Filter," Institute of Engineers Australia (IEAust) Electronic Journal 2005. T. D. Memon, P. Beckett, and Z. M. Hussain, "Analysis and Design of a Ternary FIR Filter using Sigma Delta Modulation," presented at the International Symposium on Computing, Communication, and Control (ISCCC 2009), Singapore, 2009. T. D. Memon, P. Beckett, and A. Z. Sadik, "Analysis and Design of a Ternary FIR Filter using Sigma Delta Modulation, accepted for publication 19 October, 2009," presented at the IEEE International Multitopic Conference (INMIC 2009), Islamabad, Pakistan, 2009. T. D. Memon, P. Beckett, and A. Z. Sadik, "Performance-Area Tradeoffs in the Design of a Short Word Length FIR Filter, accepted for publication 19 October, 2009," presented at the International Conference On MEMS NANO And Smart Systems (ICMENS 2009), Dubai, UAE, 2009. Tayab D Memon, Paul Beckett, Amin Z Sadik, Power-Area-Performance Characteristics of FPGA-based Sigma-Delta FIR Filters, Journal of Signal Processing Systems Springer (JSPS), No. 11265, ISSN: 1939-8018, DOI: 10.1007/s11265-012-0664-8. T. D. Memon, Design and Analysis of Short Word Length DSP Systems for Mobile Communication, Ph.D. dissertation, School ECE., RMIT Univ., Melbourne, Victoria, Australia, 2012 http://researchbank.rmit.edu.au/eserv/rmit:6282/Sadik.pdf

[2] [3]

[4]

[5]

[6]

[7]

[8]

Group C High Level Synthesis Design and Verification

6. Image processing for FPGA using High-level Synthesis (HLS)
Description In recent years, when the task of building more and more complex designs in Register-transfer level (RTL) using Verilog of VHDL languages is becoming increasingly difficult, there has been a new trend of moving hardware design and verification from traditional RTL into high-level languages such as System C. The new approach, which promises better system-level performance, has been gradually adapted by design companies and receives great support from EDA vendors. Key benefits include faster turnaround time, better performance, smaller chip area, less power consumption as well as high productivity with less engineering effort. Successful design cases from the industry can be found to prove the increasing popularity of the new methodology [1]. The essential factor that determines the success of new approach is the existence of consistent highlevel synthesis tools, which take design description in C, C++, or SystemC as the input and quickly produces RTL Verilog or VHDL as the output. Such tools have been developed and continuously improved by commercial EDA vendors such as Cadence or Synopsys, for example Synphony HighLevel Synthesis Solution [2] or Cadence C-to-Silicon Compiler [3]. Some universities [4] also have been working closely with EDA vendors, develop teaching materials and introduce the new technique into their curricula in order to equip the next generation of hardware designers with required skill set. A number of open-source HLS tools like LegUp [5] or GAUT [6] can be found for researchers and new designers to get started with this field. With the support from HLS tools, System-on-chip (SOC) designers can describe their designs at higher level of abstraction to increases the productivity while have more time on design optimisation to achieve higher Quality of Results (QoR) than conventional approach, particularly desirable in case of signal processing or image processing applications. The process of hardware compilation is done automatically by HLS tools where output RTL can be optimised up to the correct trade-off point for area (cost), power, and performance. If the target device is a FPGA, designers can quickly validate results and make modifications easily [7] while in an ASIC application they can still be confident with the output RTL since HLS tools have taken account estimated performance characteristics in hardware compilation process. In this project, a face detection algorithm using for locker application (Fig. 3, 4) will be developed using high-level language C and then be synthesised using open source HLS tools LegUp. It is expected to achieve superior performance in compared with the conventional approach on the same target device Altera FPGA DE2 board. Also, the project will explore the hardware/software co-design aspect of the algorithm to optimise the final result. Understanding the HW/SW codesign techniques will enable the development of efficient DSP applications at high-level abstraction in the future.

Figure 3 Face recognition for locker system

Figure 4 Block diagram of face recognition for locker system

Activities 1. Literature Review 2. High-level design of face recognition algorithm and other supporting blocks 3. Synthesis and evaluation 4. Optimisation and improvement References 1. http://www.eetimes.com/document.asp?doc_id=1280845 2. http://www.synopsys.com/Systems/BlockDesign/HLS/Pages/SynphonyC-Compiler.aspx 3. http://www.cadence.com/products/sd/silicon_compiler/pages/default.aspx 4. Erickson, J.; Warren, M., "Modern system on chip challenges demand development of new skills in electronic engineering graduates," Interdisciplinary Engineering Design Education Conference (IEDEC), 2013 3rd , vol., no., pp.32,35, 4-5 March 2013 5. Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Tomasz Czajkowski, Stephen D. Brown, and Jason H. Anderson, "LegUp: An Open Source High-Level

Synthesis Tool for FPGA-Based Processor/Accelerator Systems," ACM Transactions on Embedded Computing Systems. 6. P. Coussy and D. Heller, "GAUT - A Free and Open Source High-Level Synthesis Tool for FPGAbased Acceleration of Scientific Computing" 7. Cong, J.; Bin Liu; Neuendorffer, S.; Noguera, J.; Vissers, K.; Zhiru Zhang, "High-Level Synthesis for FPGAs: From Prototyping to Deployment," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , vol.30, no.4, pp.473,491, April 2011

7. HW/SW co-design using System C

Description similar as found in 6 Different from project 6, in this project we aim to explore the advantages of HW/SW co-design techniques using SystemC in combine with commercial HLS tools Xilinx Vivado Design Suite [5]. An application with both HW and SW components will be developed. Activities 1. Literature Review 2. System level design and verifications. 3. Synthesis and evaluation 4. Optimisation and improvement References 1. http://www.eetimes.com/document.asp?doc_id=1280845 2. http://www.synopsys.com/Systems/BlockDesign/HLS/Pages/SynphonyC-Compiler.aspx 3. http://www.cadence.com/products/sd/silicon_compiler/pages/default.aspx 4. Erickson, J.; Warren, M., "Modern system on chip challenges demand development of new skills in electronic engineering graduates," Interdisciplinary Engineering Design Education Conference (IEDEC), 2013 3rd , vol., no., pp.32,35, 4-5 March 2013 5. http://www.xilinx.com/products/design-tools/vivado/

Group D Raspberry Pi applications

The introduction of Raspberry Pi board, credit-card-sized single-board computer board on 2012, has encouraged the spread of small sized computers. The boards was first launched to support the teaching of computer science and IT at schools but have turned out to be a very popular product than even their manufacturers can imagine. With the availability of a range of components (e.g. SOCS, ARM microcontroller, HDMI connections, Ethernet connections), researches, hobbyists, students have been working on many interesting topics. They also tried to import applications from other platforms into this magical super low-cost board (e.g. 25 USD/1 board). In the following projects, we aim to explore the ability of the board in solving problems in a simpler way and portable ways hence mobile applications can be achieved.

8. Multiple-functions sensor node with Raspberry Pi

Description OpenCV is a very famous open source library for computer vision that has been used for many applications in wide range from academics to the industry. The engineer from [1] has recently successfully to port OpenCV to work smoothly on the Raspberry Pi board to perform some image processing algorithms. Since then, many people have been working this filed. In this project we will aim to take advantages from above results and then move to performing video processing algorithms using Raspberry Pi boards. Besides, the project wants to make the Raspberry become a multi-purpose station to work as a sensor node. The station should be equipped with common connections such as 3G, Wifi, GPS and some sensors that allow it to collect data at interested locations. Note Original ideas for this project comes from In Flow Traffic project last semester where I aim to perform video processing + data transmission using the board. However due to some limitations on time and skills on Linux, the group did not complete this part. Hence this project can be considered as the continuation of the previous project. However, it is not limited only in term of the video processing for traffic info. Other video processing can be considered and replaced the original ideas. Activities 1. Literature Review 2. Hardware implementation 3. Algorithms development 4. System evaluation 5. Optimisation and improvement References 1. http://www.raspberrypi.org/archives/4207

9. Wi-Fi Triangulations and Fingerprinting

Description The original idea comes from the project list of Tony last semester that some of you might see that. A group of cohort 2 worked on a WiFi-based tracking project using WiFi tags attached to objects of interest. They have successfully implemented the tracking algorithm based on RSSI matrix [1] and proved that they are working in Building 1 of RMIT. The method requires some manual work in collecting location data before the algorithm can be applied. On the other hand, the other method RSSI triangulation can be used to reduce this manual step with the tradeoff of more sophisticated algorithms need to be developed. In this project, we aim to discover the usage of triangulation for tracking purpose. It is expected to analyse the current algorithms to see any improvements can be done to improve its performance. To implement the algorithm we can consider using ARM boards, Raspberry Pi board or even selfdeveloped board. This option at the moment will be left open but I still put this topic in Raspberry Pi Group Activities 1. Literature Review 2. Hardware implementation 3. Algorithms development 4. System evaluation 5. Optimisation and improvement References 1. http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5544941&tag=1 2. Report from cohort 2 I will provide later

10.
Description

Wifi-based tracking of visitors at mass events

Recently, I found this interesting paper [1] on Wifi tracking application. The intention of this is to implement algorithms that allow event organiser to track roughly how many people in a specific location in a mass event. The method they used is claim as The mechanism works by scanning at multiple locations for packets sent out by the Wi-Fi interface on visitors' smartphones, and correlating the data captured at these different locations . In this project, I want to re-produce the algorithm and seek for any practical applications for the algorithm. Another target we can look for is to use this algorithm for security purposes by tracking a single object of interest without it knowing it is being tracked. Similar like the previous topic, in the paper [1] they used Raspberry Pi board to implement the algorithm but again we can be flexible on this and decide this later.

Activities 1. Literature Review 2. Hardware implementation 3. Algorithms development 4. System evaluation 5. Optimisation and improvement

References
1. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&tp=&arnumber=6583443&queryText%3 Draspberry+pi

11. Raspberry Pi with MATLAB and Simulink for Teaching Video and Image Processing
Description There has been a growing need for hands-on and project-based learning via a low-cost, easy to use hardware and software platform in teaching engineering nowadays. In teaching image processing often students are introduced only to working with algorithms alone using powerful such as MATLAB and Simulink. However, they are not often introduced how to implement these algorithms as standalone application on Hardware platforms such as microcontroller, FPGA or embedded boards. Recently, take advantage of the popularity of Raspberry Pi, Simulink has been equipped with Simulink built-in support for Raspberry Pi [1] which allows users to really implement developed algorithms onto the boards. The approach is claim to help students understand concepts and workflows for designing an embedded system, without using hand programming. Some trainings on the packages have been conducted by Mathworks as well [2] In this project, we aim to explore this toolbox in order to develop a set of algorithms that often being used in teaching image and video processing. It is expected also to develop a real-time image processing application to prove that the board is capable to deliver such requirement. Activities 1. Literature Review 2. Algorithms development 3. System evaluation 4. Optimisation and improvement References 1. http://www.mathworks.com/hardware-support/raspberry-pi.html

Group E Near Field Communication (NFC) Applications

12.
Note This project was offered to one of my students from cohort 3, he is actually doing that in Melbourne at the moment. Current result is not as good as I expected. There are couple reasons for that 1. We are using an EVM board from TI, which does give us too much flexibility on programming and make modifications. 2. The project use EVM board + a GSM board. Currently he is stuck at integrating two boards to work together Hence I want to offer the project again with few modifications. Original descriptions are below Original Description Near field communication, abbreviated NFC, is a form of contactless communication between devices like smartphones or tablets. Contactless communication allows a user to wave the smartphone over a NFC compatible device to send information without needing to touch the devices together or go through multiple steps setting up a connection. Mobile payment based on NFC is the most popular application and widely supported from the mobile industry lately with big players such as U.S Bank, Vodafone, and Google. However, it is still a long journey to really make NFC a vehicle for mobile transaction and these above companies still having been struggling. It is worth notice that NFC isnt just for mobile payment anymore where the significant increase in the number of NFC-enabled handsets shows tremendous potential for other non-payment activities. These include NFC used for marketing, ticketing and transportation, product packaging, device-to-device content transfers. NFC Smart Posters are objects in or on which readable NFC tags have been placed. An NFC Smart Poster can come in many forms it can be a poster, billboard, magazine page, even a threedimensional object. The common factor is an NFC tag that has an NDEF message stored in it and is attached or embedded in the desired medium. This small tag with information is read when an NFC device is held close to it. Examples include a poster with a web address for buying sports tickets, a timetable displayed at a bus stop, and coupons inserted in a magazine advertisement. A Smart Poster could even be a statue of a movie wizard character with an NFC tag embedded into the end of its wand.

NFC Smart Poster

Figure 1 - Smart poster [3] NFC smart posters have shown their potential in using for tourisms where the posters were installed at the Parcours in Monaco [1] and helped to bring the tourist a completed new interactive experience in finding site information, directions. Users could access further text about the location, exhibit, photos, audio commentary and video content at the Nouveau Muse National de Monaco where a number of NFC Smart Posters were installed. Original Scope In this project, we will aim to develop a NFC smart poster that can be installed at tourist information booths that can provide tourists comprehensive information of tourist activities in town. Detailed information of activities, locations, and supported materials will be easily accessed by tourists when they use NFC-enable smartphones to touch these smart posters. Generic information about the city and other useful tourist information can be also provided to tourists in a convenient manner. Adjusted Scope We also aim to build a complete poster but I want to aim for 3G connection not 2G connection. The poster should also have display connections which will help to display the content on a real screen (VGA, HDMI or S-video connections). Activities 1. Literature Review 2. Hardware implementation This time I insist on building our own board -> easy for configure and program 3. Software implementation MCU programming 4. System evaluation 5. Optimisation and improvement References: [1]. http://www.nfc-forum.org/resources/white_papers/NFC_Smart_Posters_White_Paper.pdf [2]. http://pro.gigaom.com/blog/nfc-while-payments-struggle-other-segments-will-thrive/ [3]. http://www.nfc-forum.org/aboutnfc/ 4. Report from cohort 3 student I will provide later

13.

NFC Restaurant Menu

Description I am quite interested in NFC technology and hence I want to try out some applications based on NFC. The next idea is I want to produce is a NFC menu, similar with the one found at [1]. This is a variation of NFC smart poster. The difference from this one and the previous is that we dont focus on updating content remotely anymore. The menu here is the integration between NFC + QR code reader into one single menu. Such combinations have been very popular in modern mobile marketing application in western countries [2 -5]. In this project, apart from dealing with HW and programming, if possible we will aim to develop a simple mobile app (Android for example) that can work with the menu. This menu is expected to be used with Smart Ordering System later on. Activities 1. Literature Review 2. Hardware implementation This time I insist on building our own board -> easy for configure and program 3. Software implementation MCU programming 4. Mobile apps development. 5. System evaluation. 6. Optimisation and improvement. References 1. http://www.atuch.com/products/nfc-poster-restaurant-menu-nfc-solution-qrcode-smartposter-mobile-touch 2. http://www.tapit.com.au/ 3. http://venturebeat.com/2013/02/17/heads-up-marketers-nfc-will-do-more-for-you-than-qrcodes/ 4. http://www.marketingtechblog.com/near-field-communications/ 5. http://nfctimes.com/report/tag-marketing-platforms-gain-momentum-more-nfc-enabledsmartphones-roll-out

14.

Smart Restaurant Ordering system

Description The project provides the smart and effective solution in restaurant ordering and billing management. The Customers can order food on menu (with labels on that) with the support of NFC reader or QR code (similar to above project). Orders will be received at the centre and inform directly to the Cook. The system provides flexibility to allow to add/remove order that the same table later. The Cook, through a screen and simple operations, can inform which food disks are ready to serve so that the waiter can come and get to customers. The system allows to print-out the bill at a certain table after that. Every information can be managed and reported to log files daily (bill information) This system can be helpful in a big restaurant with many table areas

Reduce the efforts of waiters and allow him/her to manage a bigger area Fast and error-free Central billing control Cook can receive orders and easy to control the order status Menu list can be changed and store in a file upload to the board through USB mass product interface

In this project, we will aim to work only on the communication system between tables with the centre (in the kitchen) in the most convenient ways. We can treat the system as a small sensor network with each table is as each node. The centre will gather ordering information from each node and then process. It is expected that a ordering system will also be developed to form a complete application. Zigbee or Wi-Fi might be considered as the communication mean between components in the network. One example can be referred to in [1] Activities 1. Literature Review 2. Hardware implementation 3. Software implementation 4. System evaluation. 5. Optimisation and improvement. References 1. http://www.youtube.com/watch?v=JRntJJPfQFw

15.

NFC-Based Motorbike Ignition

Description Original comes from the demo at [1]. In this project, I would like to produce something similar, an NFC key for motorbikes in Vietnam. In other word, besides normal key, we will help to use NFC to enhance the security for motorbikes. What is expected in this project is that we might spend some efforts on increase the security of NFC technology itself for security applications. Some of the encryption techniques used for cars might be considered and applied in this project. Activities 1. Literature Review 2. Hardware implementation 3. Software implementation 4. System evaluation. 5. Optimisation and improvement. References 1. http://www.youtube.com/watch?v=sqcWky_rfJg

Group F Embedded Systems

16. Robotic Bird for Surveillance applications
The topic was proposed by Thu. We aim to build a small robotic bird that can fly autonomously or at least can be control easily.

17.

Design an ARM-based computer platform

Note: This project I was suggested by a former student and I think it is a good idea to try out. However, I did not have too much time to give detailed description. Who is interested in this one can talk with me for more information and then we can investigate together. Scope Build a small computer platform with ARM microprocessor running Linux operating system (boot, driver, apps, and hardware) Why should we do this: Often we pay more attention to write applications on an available platform but not so many pay attentions to build a complete platform from beginning. That means we need to build the board with essential components, and then write BSP, boot loader for that board.etc. Completing this project will enable students to fully understand how a computer platform is built from both hardware (circuit design) to software (writing Operating System).

Group G Your ideas

If students have any other topics to propose, please let me know hence we can discuss and come up with a solid proposal