CHAPTER 3 DIGITAL CODING OF SIGNALS

Computers are often used to automate the recording of measurements. The transducers and signal conditioning circuits produce a voltage signal that is proportional to a quantity we wish to measure. This signal may be constant or it may be varying with time. We cannot directly input this voltage into a computer, so we use an analog to digital converter (ADC) to turn the voltage we wish to measure into an integer code which can be handled by the computer. Once inside the computer the integer code can be used to produce an estimate of the measured voltage. This in turn can be converted into the quantity that we wish to measure, e.g., temperature, acceleration, flow rate, by using the results of a static calibration. In this chapter we will concentrate on how this voltage to integer coding is done. We will not go into any details on the hardware structure of an ADC, there are many types available from suppliers; your choice of ADC will depend on cost, speed requirements, compatibility with the computer you are using and the software available to manipulate the ADC from your computer. Here, all we are interested in is the result of the analog to digital conversion and how it should be interpreted. The coding-decoding that takes place in the ADC and computer gives rise to errors, which may be small or large compared to the true voltages depending on how well the analog to digital converter is being utilized. Below is a description of some of the components of analog to digital conversion; this should give you some ideas on how to use these devices effectively. An analog to digital converter converts a voltage into an n-bit integer code which can then be stored on a computer. Many ADC's are set up to sample a signal at equally spaced time intervals and store an integer code each time the signal is sampled. There are many issues here. For example: Can we convert the integer code back to the voltage we sampled? Do we have enough information to reconstruct the original signal? What happens if the signal voltage changes while the ADC is calculating the integer code? Clipping An analog to digital conver ter has an input range, e.g. 0 10 volts (unipolar), or -5 to +5 volts (bipolar). Different ADC's have different input ranges. You must make sure your signal lies within this range. For example, for an input range of 5V, signals greater than 5 volts have the same codes as 5 volt signals and signals less than -5 volts will have the same codes as

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-5 volt signals. That is, the ADC perceives signal A in Figure 1 to be signal B shown in Figure 1. This phenomenon is known as clipping. This is a highly nonlinear effect.

Figure 1: An illustration of signal clipping.

Voltages to Integer Codes Having ensured that clipping will not take place we now need to sample the signal and generate integer code. Since a computer uses binary coding (1's and 0's), only a finite number of bits (binary digits) are available to represent the input voltage. At this point let's assume that the integer conversion happens instantaneously. So we are measuring the signal at intervals T seconds apart and converting the voltage to a code.

Figure 2: Signal being sampled

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The ADC subdivides the input range VADCmin

VADCmax into ( 2 n 1 ) intervals, where

n is the number of bits. Each bin is Q (VADCmax VADCmin ) /(2 n 1) volts wide. This is called the quantization interval or resolution of the ADC. Now some ADC's only code positive VADCmin is coded as 0 and VADCmax is coded as 2n 1. Other ADC's may code with both positive and negative integers so one possible coding scheme may result in:

VADCmin is coded as 2 (n

1)

and VADCmax is coded as 2 (n

1)

where n is the number of bits. Note that with this scheme 0 Volts gets coded as 0, negative voltages are coded with negative integers and positive voltages are coded with positive integers. The code generated for a particular voltage, Vi coming in, for an n-bit ADC that only codes positive integers is:
code nearest integer to (Vi VADC min ) (2 n 1) (VADC max VADC min )

(1)

For an n-bit ADC that codes both positive and negative integers,
code nearest integer Vi (2 n 1) . (VADC max VADC min )

(2)

Results of a static calibration of an ADC would look like the graph shown in Figure 3. This is a 4 bit unipolar ADC with a true input range of 0 to 7.5 volts. Notice that any voltage between 0 and 7.5 volts could be incoming to the ADC, but the computer will only generate 16 possible voltages corresponding to the 16 integer codes it is possible to generate with 4 bits. In general, the number of integers that can be coded is 2 n , where n is the number of bits.

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Figure 3: Static calibration curve for an ideal analog to digital converter: input range 0-7.5 Volts, 4 bits, positive integer codes only. Q = 7.5/(16-1) = 0.5 Volts. Max quantization error = Q/2 = 0.25 Volts.

Codes to Voltages Once on the computer, this code can be turned into an estimate of the incoming voltage,

V i

code Q offset ,

where offset is the voltage corresponding to a code of 0. So for a 16 bit ADC with a true input range of 10 volts that codes only positive integers
V i code 20 (2
16

10 volts , 1)

and for an ADC with the same characteristics except that it codes both positive and negative integers 20 code V , i (216 1) i.e., offset = 0 because a zero code corresponds to 0 volts.
Now any voltage between V i Q and V i 2 Q 2

would get the same code. So

Q is the maximum quantization error. Therefore we can say that 2 Vi lies in the following interval.

V i

Q 2

Vi

Q/2 V i

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So we know the true input within Q/2 volts. True Input Range vs Nominal Input Range In many practical ADC's the input range is quoted as being R Volts but in fact the true input range is R to R-Q Volts. To have +R as well as R coded would require 2n 1 codes. Since we only have 2 n codes, +R does not get coded and the highest voltage to be correctly coded is R-Q volts. When calculating Q we can take the true span and divide by ( 2 n 1 ) or we can take the nominal span and divide by 2 n .
Q true span (2
n

nominal span 2
n

, i.e. Q

2R Q (2
n

2R 2n

(3)

1)

1)

Note that both calculations give the same value for Q. Recall that the true span equals maximum input voltage - minimum input voltage, and thus the nominal span equals the nominal maximum input voltage - minimum input voltage.

Example

A 16 bit analog to digital converter has a nominal input range of 15 Volts and codes with positive integers only. (a) (b) (c) What will the integer code be if the incoming voltage is -2 Volts? What is the estimated incoming voltage calculated by the computer from the integer code? What is the range of incoming voltages that would receive the same code?

Solution
(a)

Incoming voltage VADCmin nominal span

2n

( 2) ( 15) 16 2 30

28,398.93.

where we use the nominal span of eq. (3) instead of true span as in eq. (1). Code is then 28,399.
(b)

Estimated voltage is: Code x Quantization Interval + Offset = 28399

(c)

15 1.99997 volts. 216 Maximum quantization error is half the quantization interval (Q).

30

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Q 30/216

0.0004577

and the range of voltages with a code 28399 is: -1.99997 0.0002288 volts. Example Repeat the previous example but now assume that the analog to digital converter codes positive and negative integers, and the range of integer codes is 2n 1 to 2n 1 1, where n is the number of bits in the ADC. Solution Incoming voltage n (a) 2 nominal span (b) Estimated voltage is: Code (c) Quantization Interval + Offset =

2 16 2 30

4369.0666. Code is then -4369.

4369

30 216

1.99997 Volts.

This is the same as in part (c) above.

Sampling and Aliasing When you sample a signal, do you lose information? If n, the number of bits in the ADC, is large, the quantization error will be small. So let's ignore the quantization error, assuming that there are a large number of bits in the ADC and we have utilized the input range well when we acquired the signal. If we sample the signal fast enough it is possible to use the samples to drive a digital to analog converter (DAC) and, with the use of filters, reconstruct the original signal. We need to sample the signal so that no information is lost during the sampling process. If this is the case then we can reconstruct the original signal. The reconstruction process is illustrated in Figure 4a.

integer codes from the computer

Digital to Analog Converter Zero-Order Hold

Low Pass Reconstruction Filter

fc 1 f 2 s

Figure 4a: Signal reconstruction. So what do we mean by fast enough? It turns out that sampling the signal at a rate over twice the highest frequency in the signal will ensure that no information is lost. Denoting the sample rate by fs and the highest frequency in the signal by f highest ,

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sample rate,fs

2 fhighest .

In many controls applications, where signals are sampled in order to use digital controllers, because of the characteristics of the zero-order hold digital to analog converter (DAC) and other considerations, people often choose a sample rate greater than ten times the highest frequency in the signal. However, here we will concentrate on the aliasing problem, which is caused by not sampling fast enough and thus losing information in the sampling process. If you do not sample fast enough, you can get a result (set of samples) that is identical to the result of sampling another signal of a different frequency. Hence, when you only have the samples, you do not know which of the many possible signals was sampled to produce this result. To avoid this problem you need only sample at a rate above twice the highest frequency in the signal.
Low Pass (anti-aliasing) Filter analog signal Cut-off frequency fc e.g., fc Analog to Digital Converter Sampling frequency = n-bit integer codes

1 f 2 s

fs

Hz

Storage Medium e.g. Computer Disk

1 f 4 s

Figure 4b: Data acquisition with anti-aliasing filters. To ensure that the highest frequency in the signal is known, and therefore the sample rate can be chosen correctly, low-pass filters are often used to filter out high frequencies before the signal is sampled. A block diagram of this part of the measurement system is shown in Figure 4b. The low-pass filter will remove frequencies well above its cut-off frequency and pass frequencies well below the cut-off frequency without affecting them greatly (see the chapter on filters and op-amps for a more detailed description of filters). When you do not have these filters, often referred to as anti-aliasing filters, you need to do some checks on whether you are aliasing or not. A typical check is to repeat the data acquisition at different sampling frequencies, to see if the frequency content changes. This is illustrated in Figure 5a.

Figure 5a: Seeing higher frequencies appear in the signal as the sample rate is increased. Signal is x(t) = 10 sin 187tt + 2 sin 200nt .

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Notice that when the sampling frequency reaches 400 Hz, an additional higher input frequency appears. An infinite set of sine waves at different frequencies (e.g., f1, fs f1, fs f1, 2fs f1, 2fs f1, etc.) can all produce the same set of samples. The phenomenon is illustrated in Figure 5b.

Figure 5b: An illustration of aliasing: two signals producing the same samples. You can see this mathematically: A sinewave signal, Asin 1t, sampled every T seconds gives samples:

Asin( 1nT) n = 0,1,2, ....

The sampling rate, i.e., the number of samples taken per second, is fs
1 . T

Now add 2 nK to the argument, for any integer K. This does not alter the sample value because all you have done is add an integer multiple (nK) of 2 to the sinewave argument.
A sin( 1nT) A sin( 1 nT 2 nK) A sin 2 T nT ,

which is A sin ( 1 2 Kfs )t sampled every T seconds. You can show that you get the same result if you sample
A sin K2 s
1

t .

When you plot the samples the wave will appear to be the one with the lowest frequency, so we say that the high frequency components appear to be at a lower frequency. In Figure 6 is shown the frequency the signal appears to be after sampling, versus the frequency of the original signal prior to sampling. So as you increase the frequency and keep the sample rate constant, frequencies in the range 0 fs/2 appear in the range 0 fs/2, frequencies in the range fs/2 fs appear in the range fs/2 0 , frequencies fs 3fs/2 appear as 0 fs/2 etc.

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Figure 6: Relationship between apparent signal frequency and true signal frequency.

Example If fs 100 Hz or 100 samples/second what is the apparent frequency of the sampled signal, if the incoming signal is cos(2 f2t) and f 2 = 30 Hz, 60 Hz, 90 Hz, 140 Hz? 30 60 90 lies in the range 0

fs/2 50 Hz , therefore signal frequency appears to be 30 Hz.

is > 50, 60 = 100 40 and therefore this signal frequency will appear to be 40 Hz. > 50, 90 = 100 10 , therefore signal frequency appears to be 10 Hz.

140 > 50, 140 = 100 + 40 therefore signal frequency appears to be 40 Hz. General rule: Express signal's true frequency, f true as:

f true
where fappear Example

Kfs fappear

fs /2 and K is an integer. Signal frequency will appear at fappear .

After a signal was sampled and stored on a computer, an analysis of frequency content was performed. The signal was found to contain components at 20, 40 and 90 Hertz. The sample rate was 200 samples per second, but unfortunately no anti-aliasing filters were used prior to sampling. However, it is known that the original signal only had frequencies up to 320 Hertz. List the candidates for the original frequencies in the signal.

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Solution Let's take the components one by one. 20 Hz.

f true

f true

K fs fappear K 200 20 320

Therefore for K = 0 we have f true = 20 Hz, for K = 1 we have f true = 180 Hz or 220 Hz. For K larger than 1 we have frequencies that are too large. So the 20 Hz component could have been a 20 Hz, 180 Hz or a 220 Hz. component. 40 Hz. Similar logic to above, the 40 Hz component could have been a 40 Hz, a 160 Hz (= 200 40) or a 240 Hz (= 200 + 40) component. 90 Hz. Again the 90 Hz component could have been a 90 Hz, a 110 Hz (= 200 90) or a 290 Hz (= 200 + 90) component. Additionally, by setting K = 2 and taking the minus sign in the formula, this component could also have originally been 2 200 90 = 310 Hz, which is still in the range of possible frequencies. Aperture Time An ADC takes time to come up with the correct code. The ADC generates a binary code, converts it to a voltage and compares it to the voltage coming in. When the difference between the incoming voltage and the voltage generated from the binary code is less than Q/2 the code is stored. When the difference is outside this range, a new binary code is generated, converted to a voltage and compared with the incoming voltage. Codes are generated until the correct one is found. There are many ways to come up with a sequence of codes to try, some can be very slow. While the conversion takes place the signal changes. This leads to an error in the code. This is illustrated in the Figure below.

Figure 7: Aperture Time Errors We wish t a , the aperture time, to be small enough so that the error caused by it is less than the quantization interval. There is no point in making the aperture time errors much smaller than this because the quantization errors will be much larger, and reducing the aperture time error will

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have little effect on the overall error. Let's assume we have an n-bit ADC with a nominal input range of R Volts. A sinewave signal V(t) = R sin 2ft is input to the ADC, i.e., we are maximizing our usage of the ADC range. Then V, the change in the signal during the conversion, is given by

V ta
Also we wish

which is approximately

dV dt

2 fR cos 2 t and so Vmax

2 fRt a .

Vmax

2R 2n

, so that the aperture time is less than the ADC resolution.

2R
n

Hence we require, 2 fRt a

, where f is the highest 2 f 2n frequency in the incoming signal, and n is the number of bits in the ADC. Note: If t a is large there will be large errors and not all the bits will be significant. Similarly, if f is very high.

, which simplifies to, t a

In questions that ask, how many bits will be significant if the aperture time is ..... and the highest frequency is ....., you may calculate n to be a number greater than the number of bits in the ADC. Your answer will then be the number of bits in the ADC. Examples (1) A 12 bit ADC converts voltages to integers in 3 s. What is the highest incoming frequency that you should have?
f 1 ta 2
n

1 3 10 6 212

25.9 Hz.

(2) What is the maximum allowable aperture time for an 8 bit ADC if the maximum incoming frequency is 1000 Hz?
ta 1 f 2n 1 1000 28 1.24 s.

(3) If ta

10 s, fmax
2n 1 taf

2 Hz and it is a 12 bit ADC. How many bits are significant?

1 10 5.2 n 13.95

However we only have 12 bits, therefore all 12 bits are significant. (4) As above with fmax

200

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n 7.3143 , therefore, 7.3 bits are significant. 10 5 200 Note: we do not round here to a whole number of bits. It is traditional to keep it as a fraction.

2n

1 taf

Sample and Hold Devices You will notice that even for fairly low frequencies the aperture time needs to be very small. These aperture times are difficult to achieve in practice, so we use a sample and hold circuit. This holds the signal constant at the desired voltage while the conversion takes place. The effect on the signal is illustrated below:

Figure 8a: The effect of the sample and hold circuit. The circuitry to do this is illustrated below:

Figure 8b: A sample and hold circuit. When the switch is in position (1), Vout follows the input signal. The capacitor ensures that, when the switch is in position (2), Vout remains at a constant voltage. With a sample and hold the aperture time errors become negligible. Always remember, when purchasing data acquisition boards, to ask if the ADC boards come with sample and hold devices. It is especially important when you wish to make simultaneous acquisition on a number of channels. Multichannel acquisition is often done with a single ADC and a multiplexer is used

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to cycle through the channels in sequence. If you wish to have simultaneous acquisition on all channels, the sample and holds for each channel must be synchronized, so that all channels are held
constant while the integer codes are calculated for each channel in turn.

Representation of Integers in Binary Integers are stored in a computer or in digital instrumentation as a series of 1's and 0's. You have to understand which coding scheme has been used before you can interpret the binary code. Lets first consider the case whereby only positive integers are used. We will describe two types of code here. Positive Integers (a) Straight binary In the base 10 system that you are familiar with, we write 175 to mean 1 100 + 7 or 1 102 + 7 10 + 5 101 + 5 1 100

In the binary system the columns represent powers of two: 2 0, 21, 22, 23, .... so 175 = 128 + 32 + 8 + 4 + 2 + 1 = 27 + 25 + 23 + 22 + 21 + 20 and hence Example Represent (31)10 in 8 bit binary 31 = 16 + 8 + 4 + 2 + 1 = 24 + 23 + 22 + 21 + 20

1 0 1 0 1 1 1 1 27 26 25 24 23 22 21 20 2

102 101 100 10

(31)10

(0001 1111) 2

Note that we filled in the "blanks" with zeros. (b) Binary Coded Decimal - BCD In digital instruments with LED's integers are often stored in BCD where each digit in base 10 is stored as a 4 bit binary number e.g. (175) 10 = (0001 0111 0101) BCD Since 110 710

(0001)2 (0111)2

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and 510 Negative Numbers

(0101)2

(a) Sign bit convention Here the most significant bit is used to denote the sign, 0 signifying + and 1 signifying -. Note that since we have lost one bit to a sign only half the number of positive integers can be coded. Example Code -125 in 8 bit binary using sign bit convention. (+125)10 = 64 + 32 + 16 + 8 + 4 + 1 = 26 + 25 + 24 + 23 + 22 + 20 (0111 1101)2 therefore (-125)10 = (1111 1101)2 sign bit convention. In BCD we can add an extra bit so that we would have 13 bits (-125)10 =(1 0001 0010 0101)BCD (b) 2's complement When the computer does addition and subtraction with negative numbers the logic becomes very complicated with sign bit convention. So numbers are often stored using other conventions e.g. 2's complement. So say we wish to store (-128)10 to (127)10 with 8 bit binary. We store (0 127)10 in the usual way for positive integers using the last 7 bits and 0 in the most significant bit. We then store (-128 -1)10 as (128 to 255)10 or, if you like, -q gets stored as (28- q) so -20 gets coded as 256 20 = 236. (236)10 = 128 + 64 + 32 + 8 + 4 = 27 + 26 + 25 + 23 + 22 = (1110 1100)2 2's comp. Interestingly enough, the most significant bit is still 1 if the number is negative but the rest of the code is different to that for sign bit convention. Positive integers are identical in both conventions. A quick way of doing 2's complement is illustrated below. (+20)10 = 16 + 4 = 24 + 22 = (0001 0100)2 Starting from the least significant bit (the right most bit), copy down each digit up until and including the 1st 1, giving here (-20)10

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100 Now switch the 1's to 0's and 0's to 1's to get (1110 1100) 2 as before. Using the 2's complement representation all subtractions become additions. Example + 12 32 = -20 in base 10 (+12)10 = (0000 1100)2 (- 32)10 = (1110 0000)2 Add (1110 1100)2 which indeed equals (-20)10. Example -1 10 = -11 in base 10 (-1) 10 = (1111 1111)2 (-10)10 = (1111 0110)2 Add (1111 0101)2 To convert back to base 10 use the same short cut. Start with the right most bit and write down all the digits up to and including the first 1. Then switch 1's to 0's and 0's to 1's. (1111 0101)2 - (0000 1011)2 = - (1 + 2 + 8)10 = (-11)10 Note, when we did the addition a bit "fell off the end". Don't worry about this. The only cause for concern is when the correct answer lies outside the range of integers that can be coded with the given number of bits. See the following example. Example -127 5 = -132 in base 10. Note -132 cannot be coded with 8 bit binary using two's complement for negative numbers. (-127)10 = (1000 0001) 2 (-5)10 = (1111 1011) 2 Add (0111 1100)2 Convert back to base 10. Note this is a positive number as indicated by the leading 0. The base 10 number is (4 + 8 + 16 + 32 + 64) = 124 which is not -132, the correct answer.