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Small Signal Amplifiers - BJT

Definitions Small Signal Amplifiers Dimensioning of capacitors

Definitions (1) Small signal condition When the input signal (vin and, iin) is small so that output signal (vout and, iout) is confined in the active region of the output characteristics of the device, the device is operating in a condition of small signal. More specifically, the condition of small signal are verified when the variations in output are so small that the values of the parameters of the device can be regarded as constant. In these conditions, the amplifiers can be analyzed using the small-signal models of the BJT. The small signal conditions occur, in general, for the first stages constituting an amplification system. Linearity In conditions of the small signal, the amplifier can be considered linear. The output signal is proportional to the input signal. This property derives from the fact that the components of the circuit are described by linear equations. If the system is linear applies the principle of superposition. Amplitude and phase distortion So that a waveform is not altered across the amplifier is necessary that each of its sinusoidal component is equally modified in amplitude and phase.

Definitions (2)
The transfer function or network function Complex function that describes the relationship between the output signal and the input signal. It is defined in the Laplace domain (s) or in the frequency domain (s = jw) Amplitude and phase response Real functions obtained by specifying amplitude and phase of the transfer function with s = jw. Describe the variation of modulus and phase when the frequency changes. Gain and phase shift of an amplifier In the case of an amplifier transfer function is also called amplification (or gain) and can be expressed in magnitude and phase. Relatively to the various electrical quantities considered for entry and exit there are various definitions of gain

Voltage amplification
Iin

Av Ai

RS
Vs + Vin
-

IL + VL
-

Current amplification
RL

Transconductance amplification Transresistance amplification

AG

VL ; Vin IL ; I in IL ; Vin VL ; I in

AR

Definitions (3) Input impedance It is the impedance viewed by the source of the input signal.

Z in

Vin ; I in

Output Impedance It is the impedance viewed from the output port. This impedance can be interpreted as the Thevenin impedance at the output port.

Z out

Vout ; I out
Iout + Vout
-

Iin RS Vs + Vin
-

IL + VL
-

RS RL

Zin

Zout

Definitions (4) Three configurations can be considered


VCC VCC + + Rs Vs + Vin R2 C1 R1 RC
BJT

VCC C2 + RL VL Rs Vs + Vin R2 RE R1 C1
BJT

C1 R 1

RC
BJT

C2
C3

C2 RL + VL -

R2 RE

RL VL Rs Vin Vs -

RE

Common Base Conf..


RP R1 // R2

Common Emitter Conf.


CEC RC // RL
1 h fe RE
Av Rin RL

Common Collecttor Conf.


CCC

CBC

Av Ai Rin Rout
Av Rin RL

h fe hie

RC // RL
RC h fe RL 1 h fe

h fe hie

RC // RL RE

1 hie

h fe 1 h fe

RE // RL RE // RL

RC

Av

Rin RL
1
hie 1

Rin RL
h fe RE // RL RP

RE //

hie 1 h fe
RC

RP // hie

1 h fe RE
RC

RP

RP // hie

RE //

RP // RS h fe

Electronics: a systems approach by N. Storey

Definitions (5)
ib hie vin RC//RL Common Base C.
+

hfeib
+

RE

vout -

ib
+

hfeib
+

RC//RL

Common Emitter C. v in -

hie R1//R2 RE

vout
ib hfeib

RE//RL

Common Collecttor C. vin R1//R2

hie
+

vout -

RC

Definitions (6) Coupling capacitor The amplifier is used to provide voltage and current levels adequate to drive the load connected to the output. The use of a single BJT is sometimes not sufficient to achieve this result. This limitation can be overcome by connecting in cascade several amplifiers, so that the signal emitted by the source is increased by each amplifier constituting the cascade. Each individual amplifier is called stage. Capacitors are used to connect one stage to another, they are referred coupling capacitors. The coupling capacitors have the function of providing insulation in DC so that the bias of one stage does not affect that of the next stage. These capacitors have to pass the AC signal from one stage to another with minimum distortion.
Iin RS Vs + Vin
-

IL RL + VL
-

Zin

Zout

Definitions (7) By-pass capacitors These capacitors are connected in parallel to a resistor, so AC signals on the resistor are short circuited. In this way the AC and DC circuits are different.

For example, in the case of CEC, a bypass capacitor on RE allows to obtain a higher voltage gain.

AV

h fe RC // RL hie 1 h fe RE

AV

h fe RC // RL hie

For the capacitor by-pass the following configurations can be used :


BJ T BJT BJ T

C3

C3

RE

RE
R3

C3

Re R3

Gain variation with frequency Because of the introduced reactive elements and the parasitic reactive elements the response of the amplifier is function of frequency.

Definitions (8)

Mid-band
To simplify the study, it is useful to assume that there is a range of frequencies (bandwidth) in which all the reactive effects are negligible. Therefore in this range, gain (A0), input and output impedances are real quantities (Rin Rout). Three different frequency ranges (low, medium and high frequencies) can be considered. Three different frequency ranges correspond to three different dynamic circuits.

Cut-off frequencies The mid-band is delimited by two frequencies, the lower cut-off frequency fl (determined by coupling and by-pass capacitors) and the upper cut-off frequency fu (determined by the junction capacitance and the parasitic effects). The cutoff frequencies are defined by:

Freq.

A fl

A fu
dB

A0 2
dB

A fl

A fu

A0 dB 3dB

Freq.

Electronics: a systems approach by N. Storey (13.7)

Definitions (9)

Iin RS + Vin
-

IL
+ VL
-

Vs

RL Zout

Zin

Av

VL Vin VL Vin

Av
in

VL Vin 0

VL Vin

e j(

in )

VL Vin

Common Emitter C.

ej L ;
Av ;
Common Collector C.

Mid-band

Definitions (10)

Observation When the small signal conditions are verified the bias conditions are not influenced by signals present, and the full analysis can be divided into two sub-analysis: DC and AC. The AC analysis is often made by assuming the existence of the intermediate band and analyzing the circuit in this band, where the reactive effects can be neglected. Therefore, it is important to know the cutoff frequencies that define the mid-band.

Syntesis of a small signal stage In general, a synthesis process, without the computer aid is carried out taking into account the behavior of the circuit in DC and in AC and estimating the effect of the capacitors on the cut-off frequencies. At last, the synthesis, of a stage which works at small signal, can be realized in the following steps:
1. Synthesis of the bias network. 2. Change of the bias network to meet the design specifications. 3. Choice of the capacitors to obtain the request lower cutoff frequency.

Small signal amplifiers

To design an amplifier, that by means of a suitable RL value, ensure a specific current gain and voltage amplification equal to one.

AI
The circuit solution is the:

IL I in
Iin R1
BJT

VCC

common collector stage


RS Vs

C2 IL + VL -

+ C1 Vin
-

RL R2

RE

Synthesis steps 1. Synthesize the bias network (R1, R2, RE) . 2. Select the RL value which ensures the desired current gain. 3. Choose the appropriate values for C1 and C2 which ensure the lower cutoff frequency given in the project specifications.

Synthesis steps: 1 Synthesis of bias network for the CCC

3 resistors Bias network for the CCC


VCC

3 relations
VCC VCE RE ( I CQ I BQ ) (VBEQ VE ) I CQ hFE VCC R2 R1 R 2 I CQ hFE 1 10 VBEQ I BQ 1 hFE RE R1// R 2 I BQ

R 1 VB

BJT

R2
Rbase I2 RE

VE

I2 R2

I BQ Rbase 10

I 2 10 I BQ 10 R2 1 h R 10 FE E

Synthesis steps: 1 Synthesis steps of bias network:


1) Choose the supply voltage VCC and the transistor working point: IC, VCE. 2) From the datasheet VBEon and hFE values can be obtained. If only hFEmin and hFEmax values are provided, hFE can be estimated using:

hFE = hFE min hFE max

3) RE is obtained by:

RE

VCC VCEQ IC

4) R2 is obtained by:

R2

1 hFE RE 10

5) R1 is obtained by:

R1

VCC

VBEQ VE VBEQ VE

R2

Synthesis steps: 2 RL is obtained by the circuit analysis.

AI

R AV in RL

RP // hie

1 h fe RE // RL RL

1 RL AI
RL

1 RP

1 h fe RE // RL

h fe

1 RL AI

1 RP

RE

RE RL

RL

h fe RE 1 AI h 1 fe RE RP
RL

h fe AI

If hfeRE>>RP or hfeRE> 10RP If hfeRE> 10RP and hfe>10AI

RP h fe

RL

RP AI

To perform the AI and Rin measurements :

Mount the circuit introducing a test resistor RT

RT

R1 // R2
Iin

VCC R1
BJT

Measure VRT (using two probes) RS Vs

+ VRT RT + C1 Vin
-

C2 IL + VL -

Calculate Iin and IL

Iin

VRT ; IL RT
IL I in

VL RL

RL R2 RE

Calculate AI

AI

Calculate Rin

Rin

Vin I in

To design a stage which ensures, in the passband, the desired voltage amplification. V

AV

Vin
VCC R C1 Rs + Vin R2
1

If the load can be selected a possible solution is the:

common emitter stage

RC
BJT

C2 + RL VL -

Vs

RE

Synthesis steps

C3

1. Synthesize the bias network (R1, R2, RC, RE) . 2. Select the RL value which ensures the voltage gain desired. 3. Choose the appropriate values for C1, C2 and C3 (C3 >> C1 and C2) which ensure the lower cutoff frequency given in the project specifications

Synthesis steps: 1 Synthesis of bias network for the CEC (and CBC)
VCC

4 resistors

4 relations

R1 VB

ICQ
BJT

Rc
VCC VCC RC I C VCEQ R2 R1 R 2 VCC 10 I CQ hFE 1 10 VBEQ I BQ 1 hFE RE RE ( I CQ I BQ ) (VBEQ VE ) R1// R 2 I BQ

Rbase R2
I2

VE RE

VE

I2 R2

I BQ Rbase 10

I 2 10 I BQ 10 R2 1 h R 10 FE E

I CQ hFE

Synthesis steps: 2 Synthesis steps of bias network:


1) Choose the supply voltage VCC and the transistor working point: IC, VCE. 2) From the datasheet VBEon and hFE values can be obtained. If only hFEmin and hFEmax values are provided, hFE can be estimated using:

hFE = hFE min hFE max


3) RE is achived by:

RE

VE I CQ

VCC 10 I CQ

4) RC is obtained by:

RC

VCC VCEQ VE ICQ

5) R2 is calculated by:

R2

1 hFE R E 10
VCC VBEQ VE VBEQ VE

6) R1 is calculated by:

R1

R2

Synthesis steps: 2 RL is obtained by circuit analysis.


VCC C1 Rs Vs + Vin R2 R1 R C
BJT

C2 + RL VL RS Vs

ii

ib hie
R1//R2

ib hfe

RE

C3

RL

AV

h fe

RC // RL hie

1 RL

h fe hie AV

1 RC

To design a stage to ensure, in the passband, a voltage amplification

AV

VL Vin
VCC R1 C1
BJT

If the load is fixed a possible solution is the:

common emitter stage with emitter degeneration


Rs Vs +

RC

C2
+ C3 RL R3 VL -

Vin -

R2 RE

The emitter resistor is replaced with RE//Series (C3-R3) to obtain different impedance values in DC and AC. Synthesis steps

1. Synthesize the bias network (R1, R2, RC, RE). Same approach of the CEC. 2. Select the R3 value. 3. Choose the appropriate values for C1, C2 and C3 (C3 >> C1 and C2) which ensure the lower cutoff frequency given in the project specifications.

Synthesis steps: 2
VCC R1 RC C1
BJT

C2 C3 +
RS

ii

ib hie

ib hfe

Rs Vs

+ Vin R2 RE

RL R3

VL
Vs R1//R2 RE//R3 RL

AV

h fe hie

RC // RL 1 R3

1 h fe RE // R3

RC // RL RE // R3 AV RC // RL 1 RE

AV RC // RL

1 RE // R3