Silicon RF transistors II: LDMOS

Silicon RF transistors II: LDMOS

Lars Vestling Uppsala University, Sweden

2006-02-23

Lars Vestling - Uppsala University

Silicon RF transistors II: LDMOS

Outline
Introduction Manufacturing LDMOS Models State-of-the-art LDMOS techniques Future LDMOS concepts Summary References

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Silicon RF transistors II: LDMOS

What is a DMOS?
LDMOS Lateral double-diffused MOS VDMOS Vertical double-diffused MOS

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Silicon RF transistors II: LDMOS

History
1969 the first LDMOS was presented 1972 the LDMOS as a microwave device was presented Switching devices
Power supplies Motor controls etc.....

From mid-90s Base station applications

NMT, GSM, 3G, (900 MHz-3 GHz) Philips, Freescale (Motorola), Infineon (Ericsson)

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Silicon RF transistors II: LDMOS

Base stations RF power transistors

Power amplifiers (PA) Base stations
Source: Ericsson

RF power devices has other demands than CMOS

Output power Efficiency Linearity
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RF-devices

Silicon RF transistors II: LDMOS

Why LDMOS in base station applications?

Compared to Bipolar Junction Transistors (BJT) Better linearity Grounded substrate
source connected to substrate => no bondwire required => substrate inductance decreased packaging, BeO can be avioded

Reliability
negtive temperature coefficient

Higher gain The VDMOS has some of the BJT drawbacks as well
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Silicon RF transistors II: LDMOS

Typical transistor data

Power
5-10 W up to 150 W per transistor

Frequencies
900 MHz to 2.7 GHz today

Supply voltage
VDD=26-28 V which implies a BV>60 V

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Silicon RF transistors II: LDMOS

Market
Base station applications, market share of 90% for LDMOS
Devces working at 28 V, up to 2.7 GHz, gain of 15dB and efficiency of 25%.

RF-LDMOS market
dominated by Freescale (former Motorola) with ~80% of market others are: Philips, Infineon, STMicroectronics

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Silicon RF transistors II: LDMOS

Cross-section of a modern LDMOS device

source: Freescale

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Silicon RF transistors II: LDMOS

Important transistor parameters

ID,sat saturated current BV breakdown voltage RON vs BV onresistance vs breakdown voltage fT, fMAX cut-off frequencies

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Silicon RF transistors II: LDMOS

Outline
Introduction Manufacturing LDMOS Models State-of-the-art LDMOS techniques Future LDMOS concepts Summary

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Silicon RF transistors II: LDMOS

Manufacturing
Specific issues compared to CMOS Substrate
Resistivity and epi-thickness sets BV 10 cm, 10 m => BV=60-100V

P+sinker
Area comsuming Temperature budget

Gate
Polycide, gate resistance Oxide thickness, VT, BVOX Gate length, Cgd, gate length not equal to channel length

Double diffused Channel engineering Drain engineering Drift region, RESURF technology
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Silicon RF transistors II: LDMOS

Double-diffused
p-well and n+source are double-diffused to create the channel

LDMOS for Power ICs

Suitable for circuit integration Device design for avalanche ruggedness
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LDMOS for RF
Deep p+sinker to provide substrate contact Device design for superior RF performance

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Silicon RF transistors II: LDMOS

Channel engineering
By modifying the doping in and near the channel, different behaviour can be obtained VT Lch
channel length determines speed channel doping level sets threshold voltage and controls punch-through p-well curvature controls junction breakdown

NA

BV

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Silicon RF transistors II: LDMOS

Drain engineering
Used to reduce peak electric field
Tailoring doping profiles through implantation and annealing

Minimizes IDQ drift Do not affect BV and RON Drain engineering applied in this region

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Silicon RF transistors II: LDMOS

Drift region, RESURF

RESURF
REduced SURface Field

Lateral and vertical diodes interact to provide 2D-depletion Not LDMOS specific
Works for all lateral HV devices

Charge balance Lower RON

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Silicon RF transistors II: LDMOS

Layout
Device divided in gate fingers to reduce gate resistance

Gate

Example
each finger is 100 m total width is 20 mm

Drain
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Silicon RF transistors II: LDMOS

Outline
Introduction Manufacturing LDMOS Models State-of-the-art LDMOS techniques Future LDMOS concepts Summary

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Silicon RF transistors II: LDMOS

Models
Ordinary MOS-models (SPICE) are not sufficient. SPICE sub-circuits may solve the problem.
Enhancement MOS for channel region JFET for drainunder-gate region JFET or R(V,I) for extended drain

Difficult to extract model parameters!

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Silicon RF transistors II: LDMOS

Models - problems
The channel/drain-end potential, VX
Decides the channel transistor

How model the drift region

JFET Resistor, R(I,Vgs,Vds) Analytical expressions

VX

All LDMOS devices are different => difficult to have a generic LDMOS model

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Silicon RF transistors II: LDMOS

MOS model 20 (Philips)

SPICE model Combination of MOS model 9 and MOS model 31
MOS model 9 enhancement type MOSFET model for the channel region. MOS model 31 - junction-isolated accumulation/depletion-type MOSFET model. Used for the drain extension of high-voltage MOS devices.

Model includes:
charge dynamics of the drain extension region. not the quasi-saturation (current compression) effect.

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Silicon RF transistors II: LDMOS

The Chalmers model

Generic large-signal model Analytical expression for the drain current, Ids Parasitics appended
C=const. or C=C(V)

I ds = I pk (1 + tanh( )) tanh(Vds ) (1 + Vds )

2 3 =P 1 (Vgs V pk ) + P 2 (Vgs V pk ) + P 3 (Vgs V pk ) L

drain current

Pout PAE drain voltage input power

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Silicon RF transistors II: LDMOS

Thermal modeling
Power devices generate heat The heat is distributed unevenly depending on the layout Problem characterizing the thermal properties
Pulsed measurement removes heating Pulsed S-parameter measurements with thermal chuck

Big challenge!!!

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Silicon RF transistors II: LDMOS

Outline
Introduction Manufacturing LDMOS Models State-of-the-art LDMOS techniques Future LDMOS concepts Summary

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Silicon RF transistors II: LDMOS

What is done to improve the performance?

Miller capacitance Shielding Metal sinker
Better temperature budget Less area consuming

Metalization
Gold, AlCu

Plastic encapsulation
Lower cost but worse thermal properties than ceramics

Scaling
tOX, LG, thinner substrates (<100 microns)
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Silicon RF transistors II: LDMOS

Miller effect - gate-drain capacitance

Feedback capacitance affects gain
Vgs must be maximized for max gain Vgs determined by Miller capacitance
GA ( g mVgs ) 2 Ropt VS2 /(4 RS )

Must minimize Cgd to minimize gain reduction due to Miller effect

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Silicon RF transistors II: LDMOS

1GS

2GS

Shielding
Example (Motorola)

Re-designing the metal shield lower CGD lower IM3 IM3 vs PAE CGD vs VDS 1GS 2GS

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Silicon RF transistors II: LDMOS

Freescale (Motorola) MRF5S19060

Typical characteristics
Power gain, GA = 14 dB Drain efficiency, D = 23 % IM3 = 37 dBc @ VDD=28V, IDQ=750 mA, 1960 MHz, Pout=12W BV=65 V

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Silicon RF transistors II: LDMOS

Outline
Introduction Manufacturing LDMOS Models State-of-the-art LDMOS techniques Future LDMOS concepts Summary

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Silicon RF transistors II: LDMOS

Future concepts
The supply voltage will increase to 50 V. [ITRS] BV must increase from 60 to more than 100 V New device concepts for higher supply voltages are needed. Avaliable devices (28 V) can not be directly scaled to 50 V. Solution?: Novel LDMOS device concept with a dual-layer extended drain region, which shields the active gate region from high voltage.

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Silicon RF transistors II: LDMOS

UU LDMOS project
Objective
Implement a new type of LDMOS in a standard CMOS process Breakdown voltages above 100 V and at the same time fT and fMAX at around 10 GHz Demonstrate RF-performance for frequencies relevant to telecommunication, 1-3 GHz.

Challenge
How to combine high voltage with a short channel?

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Silicon RF transistors II: LDMOS

Standard LDMOS concept, CMOS compatible

Source Gate n+ poly p+ p-base
channel kanal

Drain

n+

n+

n- drift region p-substrate

Lateral diffusion of p-base -> short channel 0.3 m Long poly-gate -> low gate resistance Long drift region -> high breakdown voltage

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Silicon RF transistors II: LDMOS

Double depletion LDMOS

Source Gate n+ poly p+ p-base
channel kanal

Drain

n+
p-top

n+

n- drift region p-substrate

Lateral diffusion of pbase => short channel Long poly-gate => low RG Long drift region => high BV
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Buried p-top => more effective drift region depletion => higher drift region doping => lower resistance for preserved BV => higher current
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Silicon RF transistors II: LDMOS

Dual conduction layer LDMOS

Source Gate n+ poly p+ p-base
channel kanal

Drain

n+

n-top p-top

n+

n- drift region p-substrate

Lateral diffusion of pbase => short channel Long poly-gate => low RG Long drift region => high BV
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Buried p-top => more effective drift region depletion => higher drift region doping => lower resistance for preserved BV => higher current N-top at surface => higher current for preserved BV
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Silicon RF transistors II: LDMOS

Enhanced dual conduction layer LDMOS

Source Gate n+ poly p+ p-base
channel kanal

Drain

n+

n-top p-top

n+

n- drift region p-substrate

Lateral diffusion of pbase => short channel Long poly-gate => low RG Long drift region => high BV
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Buried p-top => more effective drift region depletion => higher drift region doping => lower resistance for preserved BV => higher current Blanket N-top at surface => even higher current for preserved BV
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Silicon RF transistors II: LDMOS

Dual depletion effect

LDMOS without p-top layer
Badly distributed field over the drift region

LDMOS with p-top layer

Uniformly distributed field over the drift region

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Silicon RF transistors II: LDMOS

UU LDMOS performance
World record results were achieved.
2 W/mm @ 70 V and 1 GHz 1 W/mm @ 28 V and 1 GHz High linear gain 23dB 1 W/mm @ 50 V, 3.2 GHz 0.6 W/mm @ 28 V, 3.2 GHz Comparable with SiC MESFET f=1.9 GHz Vds=48 V Vgs=1.1 V

POUT PAE

Input power (dBm)

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Silicon RF transistors II: LDMOS

UU LDMOS
This device concept offers
RF performance in a wide voltage range Very high breakdown voltages (fMAX=4 GHz @ BV=400 V)
LDMOS
33 32 31 30 29 28 27 26 10 20 30 40 D ra in v o lta g e (V ) 50 60 1 0 .9 0 .8 0 .7 0 .6 0 .5 0 .4 p a tte rn e d n -to p f= 3 .2 G H z Pout -3dB compression (W /mm)

fT and fMAX vs BV ft fmax

Pout -3dB compression (dBm)

10 Cut-off frequency [GHz] 1 10 100 BV [V] 1000

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Silicon RF transistors II: LDMOS

Linearity
The linearity performance of LDMOS is very critical for the overall PA performance Output power normally backed-off in order to meet linearity requirements power efficiency also drops drastically The linearity may be improved with some methods, e.g. combining transistors with different VT more ideal transfer characteristic Major improvement can probably be achieved if the device structure itself is changed (doping profiles, dimensions etc.) The key is to understand the silicon
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Modified device

Silicon RF transistors II: LDMOS

Better linearity with modified channel

Simulation has shown that by changing the doping profile in the channel the transfer characteristic is improved
A uniform channel doping provides more ideal transfer curve and has a higher VIP3 than the usual graded doping profile. This modification can be achieved with modified process steps VIP3 is a linearity measure
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8 7 6 5 4 3

VIP3

1
8 7 6 5

vip3 uniform channel vip3 graded channel

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

Gate Voltage (V)

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Silicon RF transistors II: LDMOS

Further improvements
Other transistor parasitics may also make the device less ideal less linear Parasitics also influence other parameters, such as output power and efficiency One important parasitic is the coupling to the silicon substrate This will affect the transistor output resistance in off-state

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Silicon RF transistors II: LDMOS

Why off-state ROUT important?

ID

Load line

PA operates along a load line. In on-state ROUT (Rds) is mainly determined by the channel output conductance The ROUT in off-state determines the losses. Affects the power efficieny of PA

VD

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Silicon RF transistors II: LDMOS

HR silicon substrate improves ROUT - Efficiency

Simulation have shown that both substrate resistivity and thickness strongly affects the off-state ROUT
Cds Source Cjs Cjsub Vx Gsub Gd

109

Optimized 1 kcm substrate p- epi/p+ substrate

ROUT (mm)

Drain

107

Increasing drain voltage

105

Csub

103
Substrate

10X improvement in off-state output resistance when using high resistivty bulk-Si (1 kcm)
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101 107

108

109 Frequency (Hz)

1010

1011

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Silicon RF transistors II: LDMOS

LDMOS on SOI?
The use of SOI may further reduce the coupling to the substrate HR SOI may therefore be interesting Traditionally (CMOS) SOI also reduces other parasitics, which may lead to better overall device performance

Bulk LDMOS
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SOI LDMOS
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Silicon RF transistors II: LDMOS

LDMOS on SOI?
It has been shown that very effective RESURF can be achieved on SOI substrates good RON vs. BV Self-heating may be a problem LDMOS on high resistivity SOI has shown impressive RFperformance (40% PAE @ 7.2 GHz) However, inversion and accumulation charge underneath the BOX severely degrades the RF-performance, and must therefore be dealt with.

inversion accumulation
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depletion
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Silicon RF transistors II: LDMOS

Low-voltage LDMOS
The LDMOS transistor may also be scaled down in voltage. A CMOS compatible LDMOS concept enables integrated PA solutions, e.g. mobile handsets
10 9 80 12 7.5

R
On-Resistance [mm] 8 7 6 5 4 3 2 0 1

70 10 60 50 40 30 Breakdown Voltage [V] Frequency [GHz]

MAX

ON

Transconductance [mS]

g
8

6.5

BV

f
4

20 10

5.5

2 3 Gate Length [m]

Gate Length [m]

RON, BV vs LG
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fT, fMAX, gm vs LG
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Silicon RF transistors II: LDMOS

Low-voltage LDMOS - RF performance

Impressive performance with 400 V design rules!
30 25 Output Power [dBm] 20 15 10 5 0 -10 60

VG=3 V VD=6 V f=1 GHz

P
out

50 40 30 20 10 0 20

Power Added Efficiency |%]

PAE

2 mm LDMOS for on-wafer characterisation

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-5

0 5 10 Input Power [dBm]

15

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Silicon RF transistors II: LDMOS

Outline
Introduction Manufacturing LDMOS Models State-of-the-art LDMOS techniques Future LDMOS concepts Summary

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Silicon RF transistors II: LDMOS

Summary LDMOS
Main advantages
Majority carrier device -> carrier speed is larger than for BJT Backside source contact - reduced source inductance, no toxic BeO in the package, improved cooling High gain Better thermal uniformity compared to BJT Excellent back-off linearity
LDMOS (28V) benchmarking results showed > 5 dBc better IM3 and 2% worse efficiency @ fixed WCDMA back off power (Pavg) compared to GaAs (12V).

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Adjustable BV -> Adjustable application voltage Mature technology Ease of CMOS integration Reasonable ease of scaling up device size
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Silicon RF transistors II: LDMOS

Summary LDMOS
Main disadvantages
Frequency response limited by gate charging and transit time required through N- drift region -> < 3 GHz operation Excess efficiency degradation with increasing frequency operation -> Cds Hot electron injection or IDQ drift issue

Future
LDMOS device concept for higher voltages (required by ITRS) has successfully been demonstrated. LDMOS definitely has a bright future for RF power applications.

If you can do it in Silicon. Do it!

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Silicon RF transistors II: LDMOS

Acknowledgements
Klas-Hkan Eklund, COMHEAT Microwave AB Jrgen Olsson, Uppsala University

The work reported here was performed in the context of the network TARGET Top Amplifier Research Groups in a European Team and supported by the Information Society Technologies Programme of the EU under contract IST-1-507893NOE, www.target-org.net

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Silicon RF transistors II: LDMOS

References
J. Ankarcrona, High Frequency Analysis of Silicon RF MOS Transistors, Ph.D. Theses, Uppsala University, Uppsala, Sweden, 2005. J. A. Appels and H. M J. Vaes, High Voltage Thin Layer Devices (RESURF Devices), IEDM Tech. Dig., pp. 238-241, 1979. H. Brech et al., Record Efficiency and Gain at 2.1GHz of High Power RF Transistors for Cellular and 3G Base Stations, IEDM Tech. Dig., pp. 359-362, 2003. W. Burger et al., RF-LDMOS: A Device Technology for High Power RF Infrastructure Applications, IEEE CSIC Dig., pp. 189-192, 2004. The International Technology Roadmap for Semiconductors, 2005, http://public.itrs.net/. A. W. Ludikhuize et al., Extended (180V) Voltagein 0.6um Thin-Layer-SOI A-BCD3 Technology on 1um BOX for Display, Automotive & Consumer Applications, Proc. ISPSD, pp. 77-80, 2002. Bob Metzger, LDMOS turns up the power, Compound Semiconductor Magazine, June 2002. J. Olsson et al., 1 W/mm RF Power Density at 3.2 GHz for a Dual-Layer RESURF LDMOS Transistor, IEEE Electron Dev. Let., vol. 23, no. 4, pp. 206-208, 2002. J. Scholvin, J. G. Fiorenza, and J. A. del Alamo, The impact of substrate surface potential on the performance of RF power LDMOSFETs on high-resistivity SOI, IEDM Tech. Dig., pp. 363-366, 2003. A. Sderbrg et al., Integration of a Novel High-Voltage Giga-Hertz DMOS Transistor into a Standard CMOS Process, IEDM Tech. Dig., pp. 975-978, 1995. L. Vestling, J. Olsson, and K.-H. Eklund, Drift Region Optimization of Lateral RESURF Devices, Solid-State Electronics, vol. 46, no. 8, pp. 1177-1184, 2002.

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