Using FPGAs G and a LEON3FT O Processor to Build a "Flying Laptop"

Sandi Habinc (1), Barry Cook (2), Paul Walker (2), Jens Eickhoff (3) Rouven Witt (4), Hans-Peter Rser (4)
(1) Aeroflex Gaisler, Kungsgatan 12, 411 19 Gteborg, Sweden sandi@gaisler.com (2) 4-Links Ltd. Suite EU2, Bletchley Park, Milton Keynes, MK3 6EB, UK Barry@4Links.co.uk, Paul@4Links.co.uk (3) Astrium GmbH - Satellites, 88039 Friedrichshafen, Germany eickhoff@irs uni-stuttgart de eickhoff@irs.uni-stuttgart.de (4) Institute of Space Systems, Universitt Stuttgart, Pfaffenwaldring 31, 70569 Stuttgart, Germany witt@irs.uni-stuttgart.de, roeser@irs.uni-stuttgart.de

RESPACE/MAPLD 2011

The Flying-Laptop (FLP) Satellite

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Activity lead by Institute of Space Systems, y , University y of Stuttgart g ( (D) ) 3-axis stabilized LEO satellite Box size of 60cm x 70cm x 80cm Deployable solar panels Mass of 120kg AOCS including star trackers, wheels, GPS Launch envisaged 2013 on ISRO PSLV launcher Payloads:

Panoramic camera camera, Multispectral camera, Laser link terminal

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The Flying-Laptop (FLP) Satellite

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FLP Spacecraft Electrical Block Diagram

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Flying-Laptop Onboard Computer

CCSDS Processor Boards

Power Supply Boards

I/O Boards

On-Board Computer Boards

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Onboard Computer Board

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Eurocard size single board computer based on UT699 LEON3FT device, , operating p g at 33 MHz 4 MB NV RAM, 8 MB SRAM 4 SpaceWire p interfaces ( (2x CCSDS board, , 2x I/O Board) ) 1x UART (OBSW Service I/F) 1x 44 Pin mixed connector with JTAG, , Power Supply, pp y, etc.

Clearance for publication by Aeroflex Corp., Colorado Springs, USA

Information from DASIA 2011 presentation by Astrium
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I/O Board
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I/O boards form the bridge btw OBC and S/C I/O-boards mimic the digital interface function of a RIU The I/O boards are connected to the OBC boards via a SpaceWire connection running the RMAP protocol The I/O board are developed by 4Links Ltd., UK. The I/O boards Th b d SpaceWire S Wi functionality f ti lit and d data d t routing ti between SpW and the low level I/O and bus interfaces is implemented in a ProAsic3 FPGA I/O board incorporates MRAM for S/C HK TM storage and for S/C state vector storage for reconfigurations Generic board design with I/Fs and SpW and central ProAsic3 FPGA and also used for CCSDS processor
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I/O Board block diagram

FPGA Actel ProASIC 3e A3PE3000 (Industrial temperature version)

LVDS Buffers SpaceWire CODECs Remote Memory Access Protocol (RMAP) Target

IBIS

I2C

UARTs

Digital I/O

Memory / I/F

MRAM
RS422/485 Buffers O/C Buffers RS422/485 Buffers Digital line Buffers

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I/O Board PCB layout (Draft)

Information from DASIA 2011 presentation by Astrium

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CCSDS Processor Board

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FLP applies CCSDS/PUS standards for S/C command and control To implement this, the FLP is equipped with a CCSDS processor built on the same basic PCB design and ProAsic3 FPGA as the I/O Board CCSDS board manufactured by 4Links Ltd. CCSDS IP cores designed by Aeroflex Gaisler CCSDS processor breadboard from Aeroflex Gaisler

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CCSDS SpacePackets over SpaceWire

Aeroflex Gaisler has developed a method to transfer CCSDS Space Packets over SpaceWire links based on Remote Memory Access Protocol (RMAP). The Space Packet is transferred as part of the data field of the RMAP write command. The write access is done to memory areas in the target that are dedicated to different Packet Telemetry Virtual Channels Channels. The success of the transfer is acknowledged by an optional RMAP reply. The Space Packet is protected by means of the RMAP data field CRC. Additionally, y, the RMAP command header (containing the addressing information, e.g. for Virtual Channel routing) is protected by means of CRC.
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GRLIB IP core library

GRLIB is a complete design environment: Processors Peripherals Serial interfaces Parallel interfaces Memory controllers AMBA on-chip bus with Plug & Play support Fault tolerant & standard version Support for tools & prototyping boards Portability between technologies: Actel, Aeroflex, Altera, Artisan, Atmel, DARE, eASIC/Nextreme, Eclipse Lattice Eclipse, Lattice, Synopsys DesignWare Ramon Chips / RadSafe, TSMC, UMC, Virage, Xilinx, etc.
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GRTM Encoder & GRTC Decoder IP cores

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CCSDS TC Decoder / TM Encoder FPGA

Data Link P rotoc ol Sub-Lay er Coding Sub-Lay er Ps eu udoDerandomizer Start t sequenc e searc h Phys ic al Layer B CH Dec oder A MB A AHB Mas ter NRZ -L

DMA

F IF O

T elecom m and C LT U

Configur ation A MB A AHB Slave All F rames R Rec ept. V CP kt Extra action P ac ket Ex tra ac tion A MB A

P ath Recov very

VC R ecept tion

T CU AR T
8k Mem ory A HB S lav e Descr iptor p Mem ory A HB S lav e 16k B uffer Mem ory A HB S lav e 16k B uffer Memor y AH B Slave

Hardware Com mands

MCDemu ux

VC D emu ux

Telecom mand Decoder

C LC W C ros s-c oupling

A MB A APB Slave

Data Link P rotoc ol Sub-Lay er

Configur ation

A MB A AHB Mas ter

DMA

2k FIFO

Telem etry Encoder

V ir tual Channel Fram eS ervice Mas ter Channel G t eneration V ir tu ual Channel Multiplexer All F ram es G eneration

Coding Sub-Layer P seudo Random izer Reed-S olom on

Phy sical Lay er

Spac eW ire

G RSPW RMA P AHB M aster t

A HB S lave

V C G enerate

AMB A AHB M as t ter AMB A AHB M as ter AMB A AHB M as ter Idle Fr ame

V C1

A HB S lave G RSPW RMA P AHB M aster

V C G enerate

V C2

Spac eW ire

A HB S lave

V C G enerate

V C3

VC7

NRZL

S lave

G enerate

V C0

S ync Marker

A HB

V C

Convolutional

AMB A AHB M as ter

T elem etry C AD U

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TMTC FPGA

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CCSDS TM/TC breadboard

GR-MCC-C + GR-TMTC-ADAPTER + GR-CPCI-RS422

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Conclusions
The re-programmable ProASIC3 FPGA technology fits well in applications with low radiation requirements. The in-situ programmability enables the development of highly miniaturized systems which can be adapted to customers needs late in the development cycle. Porting a combined SpaceWire and CCSDS system to Flash-based FPGA technology went smoothly, with much of the IP core library work already done. done Main processing power located in UT699 device, with peripheral functions such as I/O and CCSDS processing implemented in custom designed FPGAs.
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Contact information
Processor and IP core information: http://www.Aeroflex.com/Gaisler Board and component information: http://www 4Links com http://www.4Links.com Flying y g Laptop p p information:
http://www.kleinsatelliten.de/index.php/en/flying-laptop.html

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