UNIVERSITY OF CALIFORNIA, SAN DIEGO

Electrical characterization of thermally and mechanically exfoliated silicon films

for flat panel display applications

A dissertation submitted in partial satisfaction of the requirements for the degree

Doctor of Philosophy

In

Materials Science and Engineering

By Felix Paul Lu

Committee in charge:

Professor Paul K.L. Yu, Chair

Professor S.S. Lau, Co-Chair
Professor Harry H. Wieder
Professor Jan Talbot
Professor M. Lea Rudee

2004
 Copyright

Felix Paul Lu, 2004

All rights reserved.

The dissertation of Felix Paul Lu is approved, and it

is acceptable in quality and form for publication on

microfilm:

____________________________________________

____________________________________________

____________________________________________

____________________________________________

____________________________________________
Chair

University of California, San Diego

2004

iii
 DEDICATION

To my parents, teachers and friends without whom this would not be possible.

iv
 TABLE OF CONTENTS

Signature Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii

Dedication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . iv

Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . v

List of Symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix

List of Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x

List of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xix

Acknowledgements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xx

Vita, Publications and Fields of Study. . . . . . . . . . . . . . . . . . . . . . . . .xxi

Abstract. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxii

I. Introduction

1.1 The evolution and requirements for flat panel displays. . . . . .1

1.2 Organic light emitting diodes. . . . . . . . . . . . . . . . . . . . . . . . .15
1.3 Pixel addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.4 Optimization of active matrix addressing . . . . . . . . . . . . . . .19
1.5 Material requirements for FPDs. . . . . . . . . . . . . . . . . . . . . . .22
1.6 Wafer bonding and film exfoliation. . . . . . . . . . . . . . . . . . . .26
1.7 Thesis overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
1.8 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

II. Chapter 2: Wafer bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

2.1 Wafer bonding theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

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 2.1.1 The wafer surface . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.1.2 Wafer cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
2.2 The effect of plasma activation of the surface . . . . . . . . . . . .41
2.2.1 Bonding procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.2.2 Discussion of bonding procedure . . . . . . . . . . . . . . . 44
2.2.3 Bond strength vs. RF plasma power . . . . . . . . . . . . . 46
2.2.4 Explanation in terms of plasma physics . . . . . . . . . . 47
2.2.4.1 Plasma etching physics . . . . . . . . . . . . . . . . 48
2.2.4.2 UV light emission . . . . . . . . . . . . . . . . . . . .51
2.2.4.3 Particle bombardment . . . . . . . . . . . . . . . . . 54
2.2.4.4 Plasma effects on Si oxidation . . . . . . . . . . .54
2.2.4.5 Effect of plasma on surface silica chemistry 57
2.3 Wafer bonding results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3.1 Si to Si bonding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3.2 Si to Oxide bonding. . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.3.3 Si to Glass bonding. . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.4 Wafer to wafer bond strength measurement. . . . . . . . . . . . . 63
2.5 Key experiments and results. . . . . . . . . . . . . . . . . . . . . . . . . .69
2.6 Summary of the mechanics of Si/OX plasma activated
hydrophilic wafer bonding. . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2.7 Summary for wafer bonding chapter. . . . . . . . . . . . . . . . . . . 76
2.8 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

III. Chapter 3: SOI film preparation and characterization . . . . . . . . . . . . . . 88

3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.2 Ion implantation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
3.2.1 Single ion implantation. . . . . . . . . . . . . . . . . . . . . . . .96
3.2.2 Plasma Immersion Ion Implantation. . . . . . . . . . . . . .97

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 3.3 Implantation induced damage profile. . . . . . . . . . . . . . . . . .106
3.4 Electrical characterization of films . . . . . . . . . . . . . . . . . . . 106
3.4.1 Hall effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
3.4.2 Hot Probe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
3.5 Thermal donors in Si. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
3.5.1 Phenomenological introduction . . . . . . . . . . . . . . . .109
3.5.2 Origin, formation and thermal evolution of thermal
donors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
3.6 Experimental considerations: annealing and measurement
details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
3.7 Si film characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
3.8 Electrical measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . .122
3.8.1 Silicon on Insulator structures . . . . . . . . . . . . . . . . .122
3.8.1.1 Si on glass experiment . . . . . . . . . . . . . . . .123
3.8.1.2 Si on glass results . . . . . . . . . . . . . . . . . . . .124
3.8.1.3 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . 128
3.8.2 Si on wet thermal oxide . . . . . . . . . . . . . . . . . . . . . 129
3.8.2.1 Thermally exfoliated films . . . . . . . . . . . . .130
3.8.3.1 Mechanically exfoliated films . . . . . . . . . . 136
3.8.3.2 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . 139
3.9 Strain characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
3.10 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
3.11 Summary and conclusions . . . . . . . . . . . . . . . . . . . . . . . . . 156
3.12 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158

IV. Chapter 4: Fabrication and characterization of MOSFETs

4.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
4.1.1 Electrical characterization . . . . . . . . . . . . . . . . . . . 164

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 4.1.2 Mobility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
4.1.3 Leakage current measurement . . . . . . . . . . . . . . . . .169
4.2 Si on insulator (SOI) structures for devices . . . . . . . . . . . . . .173
4.2.1 Effect of film thickness . . . . . . . . . . . . . . . . . . . . . . 175
4.2.2 Partially and fully depleted TFTs . . . . . . . . . . . . . . 177
4.3 Background Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
4.4 Experimental details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
4.4.1 SOI MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
4.4.2 Conductivity conversion . . . . . . . . . . . . . . . . . . . . . 181
4.4.3 Process conditions . . . . . . . . . . . . . . . . . . . . . . . . . .182
4.5 Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
4.6 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
4.6.1 Hot cut vs. cold cut devices . . . . . . . . . . . . . . . . . . .191
4.7 Summary and conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
4.8 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

V. Summary, conclusions and suggestions for continued research . . . . . . . . . . 196

VI. Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

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 LIST OF SYMBOLS

ID = IDS Drain to source current

VD = VDS Drain to source voltage
VGS = Vg Gate voltage
W Gate width
L Gate length or channel length
µ carrier mobility
µH Hall effect mobility
µeff Effective mobility
µFE Field effect mobility
µsat Saturation mobility
r scattering factor
xdmax depletion width at strong inversion
εSi permittivity of Si
ΦF Fermi potential
Na Acceptor concentration
ni intrinsic carrier concentration
Cox Gate oxide capacitance
σ(θ) Scattering cross sectional area
θ deflection angle with respect to incident
Zn Atomic number of particle n
E incident kinetic energy
Mn Mass of particle n

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 LIST OF FIGURES

Figure 1-1: Relative power consumption of various subcomponents of a portable

notebook type computer with an LCD flat panel display. . . . . . . . . . . . . . . . . . . . . .2

Figure 1-2: Power draw of various subcomponents of a portable notebook type

computer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Figure 1-3: Evolution of screen size and pixel density for notebook flat panel
displays. ppi stands for pixels or points per inch, VGA, SVGA, XGA, SXGA, and
UXGA signify the display resolutions and are 640×480, 800×600, 1024×768,
1280×1024, 1400×1050, and 1600×1200 pixels respectively. The numbers are the
horizontal × vertical number of lines in the screen.. . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 1-4: Side by side comparison of OLED pixel (left) and LCD pixel (right). It
can be seen that the OLED pixel has fewer layers and is thus simpler to fabricate, not
to mention correspondingly higher yields.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Figure 1-5: Layer structure of organic light emitting diode. The EIL and HIL layers
are basically contact layers, and the ETL and HTL layers are basically the n and p
doped layers. The anode and substrate have to be optically transparent.. . . . . . . . . .17

Figure 1-6: Schematic of simple passive matrix (left) and active matrix (right) grids.
The active matrix has at least 1 TFT at each pixel location as shown by the MOSFET
icon. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Figure 1-7: 2 TFT configuration for active matrix control of pixel. The input TFT
(Q1) allows charge to flow into the storage capacitor, which holds Q2 on, turning on
the LED. The second half of the cycle reverses the charge, discharging the capacitor.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 1-8: Semi-log plot of I-V characteristic for amorphous Si TFT. Note the
extremely low reverse bias leakage current.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 1-9: MILC schematic of the layer structure (left). The right half shows a
zoomed in area near the gate edges. This indicates that the gate edges hardly or do
not see the metallic contamination.. . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 2-1: different configurations for water attaching to silanol bonds at the surface
of the oxidized silicon surface. (a)-(c) show an isolated silanol bond, (d) shows an
associated silanol bond. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

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Figure 2-2: Illustration of the “flat and smooth” silicon surface at the atomic scale.
The bond strength relies on the effective contact area, which can be increased. . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Figure 2-3: Illustration of the TTV – total thickness variation used to characterize the
flatness of the silicon wafers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Figure 2-4: The gap between the bonded silicon wafers (or maybe to be bonded). The
water molecules are able to bridge the gaps between the silanols proving a weak
temporary bond. Closing the surface would bring the silanol groups closer together
to form a stronger siloxane bond. As is shown, the separation is not far (~11 Å in this
case). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Figure 2-5: The effect of the RF input power on the bond strength. From 100-200 W,
the difference is small, but going up to 400W actually makes the bond strength
weaker! (bonded at UCSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 2-6: Surface roughness measured by AFM as a function of plasma process

time. Circles and squares correspond to hydrogen (H series) and argon (A series)
treatments, respectively. Triangles correspond to hydrogen treatment after argon
treatment (AH series).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 47

Figure 2-7: Comparison of UV activated samples to samples (■,▲) with no surface

activation (♦). The ambient in the chamber was either ozone or (UHP) nitrogen. The
wafers were all RCA cleaned before bonding. At room temp (far left), the bond
strengths are similar. At higher anneal temperatures, the UV activated samples seem
to be slightly stronger. The measured bond strengths match up with those given in
the literature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .53

Figure 2-8: surface of SiO2 with a crack/pore. The isolated silanols (left side) are less
likely to interact (and form an associated silanol on a flat surface. In the pore, the
slope forces the isolated silanols to get closer making it more likely to form an
associated silanol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Figure 2-9: sample cross section for multiple interference transmission FTIR
measurement. The thick gray area is the wafer bonded interface and where the
molecular species of interest are. The edges are beveled to facilitate coupling of IR
beams at the appropriate angles such that they are confined within the waveguide.. . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 2-10: Comparison of Si/Si bonding (left figure) to Si/OX bonding (figure on
right). The images were taken using a scanning acoustic microscope (SAM) at VTT
electronics in Finland. The small bubbles are not visible under an IR transmission
imaging (not shown). This shows the benefit of using Si/OX rather than Si/Si

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bonding. (4 inch bonded Si wafers, SAM imaged by T. Suni at VTT electronics,
Finland) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 2-11: The razor blade measurement method. The blade is inserted between the
wafers which creates a separation seen with an IR camera (right picture). The crack
length is measured and varies inversely (to the fourth power) with the bond strength.
The thing to watch out for is the tapered tip of the blade. It will effectively shorten
the crack length making the bond strength seem stronger than it really is, especially
for strong bonds.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 2-12: figure of bond strengths with and without blade taper in calculation.. 66

Figure 2-13: The crack length shown in figure 8, will increase as a function of time.
It slows down after about 2 minutes.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 2-14: This plot demonstrates several things. The plasma activation makes a
significant difference in the bond strength, Activating both wafers (Si and OX)
results in stronger bond strength than activating either alone. . . . . . . . . . . . . . . . . . 70

Figure 2-15: Plot of bond strength with varying “native oxide” thicknesses. This was
to show that something diffused across the oxide, and the increase in bond strength
was proportional to the amount of diffusant. The thinner the oxide the larger the
expected bond strength, which is what is seen. The values are spaced close enough
that plotting on a log scale does not spread out the data points much, if any. . . . . . .72

Figure 2-16: Plot of amount of water diffused across the thin oxide as a function of
temperature. This shows that at 200 °C, a lot of water has diffused across the wafer
bonded interface and through the native oxide. Comparing this with the bond
strength profile (vs. temperature), it matches up nicely. Note that the oxygen
diffusion profile is also shown for reference. The water diffusion profiles were
calculated assuming a finite source (Gaussian) and an infinite source (erfc). Values
used: for water: D0 = 1×10-6 cm2/s, EA = 0.79 eV; for oxygen: D0 = 2.7×10-4 cm2/s,
EA = 1.16 eV after Tsai (1983). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Figure 3-1: SRIM/TRIM simulations (20,000 ions) of implanted H ion

concentrations and implantation induced vacancies in Si. Column (a) is the
implanted ion concentration profile of atomic hydrogen into silicon for various
implantation energies 10, 20 30 and 50 kV. Column (b) shows the damage
distributions for the respective implantation energies. The given “ion range” is the
projected range (depth of the implanted ion), the straggle (standard deviation),
skewness and kurtosis are the second, third and fourth moments of the ion
distribution.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

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Figure 3-2: (a) Optical micrograph of 1×1017 H+/cm2 after annealing to 475 °C (Mag.
90×). (b) AFM image of a 15 µm ×15 µm region of the same sample as in (a). . . . .91

Figure 3-3: The Smart-CutTM process. Step 1: Hydrogen ions are implanted into the
surface of the (donor) silicon substrate (typically, prime grade silicon) at energies of
~30-150 kV at a dose of ~ cm-2. They roughly end up at ~1000Å per 10 kV per
proton, which is where the damage region lies. Step2: The stiffener (usually glass or
oxidized silicon with a wet thermal oxide of 2000-5000 Å) and the implanted wafer
are then cleaned and then have the surfaces activated with plasma (oxygen, nitrogen
or argon) for ~30 s at ~100 W plus any appropriate post plasma treatment. Step 3:
The wafers are contacted and Step 4: they are annealed in air first at 100 °C (to
strengthen wafer-to-wafer bond strength to prepare for dicing) then at temperatures
of 200-400 °C to exfoliate the film.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 3-4: Schematic set up of PIII. It can be seen that the implantation dose is
independent of wafer size. A typical dose rate is 1×1016 cm-2 s-1. . . . . . . . . . . . . . . .98

Figure 3-5: SIMS analysis done on PIII DC and Long Pulse Si on glass samples. The
thickness of the film is denoted by the dotted line(s) close to 1500Å. The glass was
Corning 1737F glass. Note the thickness of the silicon film is different for the DC
and AC mode implantations. This is the result of the broadened implantation/damage
profile produced by the low energy implants characteristic of the AC mode . . . . .101

Figure 3-6: Differences between DC and AC mode PIII implantation. (a) The finite
rise/fall times for AC mode PIII implantation. (b) The low energy implants
effectively make a continuum of distributions, increasing the width of the cleavage
depth. (c) multiple ion implants introduce more discrete distributions and therefore
more discrete cut depths. The central peak of the integrated damage distribution will
tend to be larger due to more overlap. The effect of this is that the implanted ions are
spread out more smoothly (b), compared to the DC mode which has more discrete
cut depths (c). Because of this broader distribution, the cut depth is not precisely
defined. The effect is to give a much larger range of possible cut depths. This will
result in the cut depth varying over the film giving a long range surface roughness
(AC mode) and a short range surface roughness (DC mode). . . . . . . . . . . . . . . . . 102

Figure 3-7: Cross sectional TEM of DC mode PIII for silicon on Corning 1737F
glass. In (a), the layers of the glass, silicon and damaged silicon layer are clearly
seen. The damage layer is 500 Å thick and the total cut depth for the silicon film is
~1500 Å for the 30 kV implantation. The diffraction pattern is for the middle silicon
layer and shows that it is still mono-crystalline. In (b), a close-up of the silicon-glass
interface is shown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

xiii
Figure 3-8: (a) 3-5 mm on a side sample with indium solder dots. (b) Illustration of
indium wetting and not wetting the surface for good ohmic contacts to silicon.
Essentially, the contact angle should be small. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 3-9: PIII DC mode silicon on Corning 1737F glass measurements as a

function of annealing ambient. It is relatively clear that annealing in air has a
detrimental effect, making the sheet charge values jump erratically. Annealing in
nitrogen seems to solve this problem. The expected type of the silicon film is n-type
for the as-exfoliated film and p-type for the annealed samples. It is for this reason
that the sheet change at time zero is not included. . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 3-10: Thermally exfoliated (hot cut) silicon on wet thermal oxide sheet charge
depth profile as a function of annealing ambient and whether or not the damage layer
existed. In general, the presence of the damage layer reduced the electron sheet
charge and annealing in an argon ambient resulted in the highest electronic sheet
charge. “H.R.” is highly resistive, which means that the samples could not be reliably
measured. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

Figure 3-11: Plot of required film resistivity so that mobility is at least 100 cm2/V·s
as a function of carrier concentration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

Figure 3-12: Average carrier concentration depth profile for plasma immersion ion
implanted (PIII) silicon on corning 1737F alumino-silicate glass. The donor wafer
(implanted wafer) was implanted with H+ at 30 kV giving a cut depth of roughly
1500 Å with a 500 Å damage layer at the surface. The as-exfoliated data is n-type
and increases throughout the damaged region before dropping off. The data for all
three sets stops short of the final hundreds of Angstroms because the film becomes
highly resistive and is not measurable using Hall effect. . . . . . . . . . . . . . . . . . . . . 125

Figure 3-13: Single ion (as opposed to PIII), as-exfoliated implanted silicon on glass
films. The different anneal times are for the wafer bonded pair (before the film was
exfoliated.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Figure 3-14: Comparison between thermally exfoliated AE and EA samples annealed

in nitrogen. From the way the graphs line up at about a depth of 2000-2500 Å, one
can speculate that the annealing may cause the defect migration to that depth for the
case where the damage layer is left intact. [diffusion of ~1000 Å for 4 hours at 650
°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Figure 3-15: Thermally exfoliated silicon on wet thermal oxide. The difference
between this data and the data for the 650 °C anneal in figure 3-14 is significant. The
AE data jumps all over the place compared to the EA data. This may suggest that the

xiv
diffusion of the defects from the damage layer has gone all the way through the film.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Figure 3-16: Thermally exfoliated silicon on wet thermal oxide annealed at 1050 °C
for 1 hour in nitrogen. This was done to see if the thermally exfoliated samples could
be turned back to it’s original p-type doping. Higher temperatures were not
attempted because the temperatures approached the softening temperature of the
quartz tube. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Figure 3-17: Thermally exfoliated silicon films on oxide depth distribution. The as-
exfoliated data is superimposed as a reference. The annealed samples have had the
damage layers etched off before annealing. The main difference between the
annealed samples and the as-exfoliated sample is the drop off point. The higher the
anneal, the more sloped the profile becomes. This is an indication of a more uniform
distribution of carriers since this is a plot of the (average) electron sheet charge. . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Figure 3-18: comparison of as-exfoliated data for cold cut and hot cut films. The
vertical dotted line denotes the visible extent of the damage layer (through TEM). . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Figure 3-19: The effect of etching before annealing and vice versa for cold cut films
as well as the effect of differing anneal temperatures. The basic trend is that
annealing at higher temperatures raises the carrier concentration and etching off the
damage layer before annealing, increases it even more. VTT indicates that the
samples were implanted and exfoliated at VTT electronics, Espoo, Finland; and
HKUST indicates that the sample was implanted and exfoliated at the Hong Kong
University of Science and Technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

Figure 3-20: Comparison of EA and AE samples for cold cut silicon on wet thermal
oxide annealed at 1000 °C for 1 hour in nitrogen. . . . . . . . . . . . . . . . . . . . . . . . . . .138

Figure 3-21: (Leftmost figure) Cross section of the nominally oriented (001) SOI
substrate indicating the relative orientation of the (001) planes in the film and the
substrate by the direction of the diagonal lines (exaggerated). (Rightmost figure) the
azimuthal direction of rotation with respect to the wafer normal (which may not
coincide with the [001] normal of the film.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Figure 3-22: (a) the hydrogen implanted wafer has a convex curvature [1], which is
bonded to a thermally oxidized silicon wafer which also has a convex curvature due
to the volume expansion of the oxide. (b) because both wafers are convex and facing
each other, the balance each other out (figure not to scale) and the wafers are bonded
in a flat state. (c) as the film is delaminated, the much thicker oxidized substrate

xv
reverts back to it’s convex curvature stretching the film and putting it in a state of
tension even though the overall curvature is convex. . . . . . . . . . . . . . . . . . . . . . . . 147

Figure 3-23: AFM topograph of cold cut and hot cut films. . . . . . . . . . . . . . . . . . .151
Figure 3-24: Plot of effective wafer bonded surface energy as a function of anneal
temperature. The surface is the “effective” energy because the implanted hydrogen
interface is weakened and becomes weaker upon annealing. This plot shows that the
bond strength holding the film to the rest of the wafer actually depends on the carrier
concentration (Fermi level) and not the doping concentration. . . . . . . . . . . . . . . . .152

Figure 3-25: The implantation is done through the wafer bonded interface. The cut
depth is the region of maximum damage. There is a characteristic region of highly
damaged material is seen from TEM which is distinct from the H+ concentration
profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Figure 3-26: Comparison of cold cut and hot cut films. They can really only be
compared in this thesis at temperatures above ~950 °C since they are opposite
conductivity types below that. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154

Figure 3-27: To see if the implantation/exfoliation damage could be singled out,

some electrical measurements were done on p-type BESOI and n-SIMOX wafers.
The resulting behavior is what was expected for implanted and non-implanted films.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Figure 4-1: (a) p-channel MOSFET with a positive gate bias produces no channel
between the source and drain (dark gray regions). (b) negative gate bias produces a
conducting channel between the source and drain. If a bias is now applied between
the source and drain, a current can flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164

Figure 4-2: example MOSFET drain to source current as a function of drain to

source potential bias and gate to source bias. The sloped region is referred to as the
linear region, and the flat (horizontal) part is referred to as the saturation region. . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Figure 4-3: MOSFET drain to source current as a function of gate to source potential
bias for a fixed drain to source potential bias. Note that the y-axis is a log scale. The
level at which the current settles is the base leakage current (off state current). The
subthreshold slope determines how quickly the device can turn on or off and is
measured as a certain number of millivolts per decade of current. . . . . . . . . . . . . 166

Figure 4-4: diagram showing preferred setup for low current probing. The box
should be light tight and grounded, effectively serving as a radiation shield. . . . . 170

xvi
Figure 4-5: example of how to connect triaxial cable to probe box interlock
connection to coaxial cable inside the probe box. This provides maximum sensitivity
for low current measurements. . . . . . . . . . . . . . 171

Figure 4-6: Noise floor for the HP4155B semiconductor parameter analyzer. The
connector configuration used was tri-axial guard connect to the co-axial shield. The
short integration time was the setting used in the measurements. It has the largest
spread but fastest measurement time. As it turned out, it doesn’t matter which setting
was used for the measurements here since the currents were all greater than 1 pA. . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172

Figure 4-7: Illustration of the kink effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Figure 4-8: Band diagram in bulk (A), a thick-film SOI (B), and a thin-film SOI
device (C). All devices are represented at threshold (front gate voltage = threshold
voltage). The shaded areas represent the depleted zones. SOI devices are represented
for a condition of weak inversion (below threshold) at the back interface. . . . . . . 175

Figure 4-9: Calculation of depletion width due to the doping level. After annealing
to ~1000 °C the electron concentration is in mid 1016 cm-3. This gives a range of
0.14-0.20 µm for the space charge region under the front gate. The depletion width is
only a slow function of temperature.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Figure 4-10: Final structure of p-MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179

Figure 4-11: (a) Optical micrograph of the final MOSFET. Shown are the aluminum
contact pads for the source, drain and gate. The smaller squares are the windows
through the gate oxide through which the metal contacts the doped silicon. (b)
Optical micrograph of the channel area of the MOSFET. The gate length is 38 µm
and the gate width is 128 µm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Figure 4-12: (a)-(b) ID-Vds plots for p-MOSFET fabricated on hot cut/cold-cut Si. . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Figure 4-12: (c) ID-Vds plots for p-MOSFET fabricated on bulk Si. . . . . . . . . . . . .184

Figure 4-13: (a) p-MOSFET fabricated on hot cut silicon. The different biasing
conditions all gave similar curves as shown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

Figure 4-13: (b) p-MOSFET fabricated on cold cut silicon ID-Vgs characteristics.
The different biasing conditions resulted in the widest variation of characteristics.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

xvii
Figure 4-13: (c) p-MOSFET fabricated on bulk Si. The gate oxide was 1000 Å thick.
The biasing conditions didn’t affect the I-V characteristics much if any. . . . . . . . .187

Figure 4-13: (d) Plot of Ids-Vgs in the off and turn-on states for TE, ME and bulk p-
MOSFETs with Vds = 2.5 volts. The bulk p-MOSFET had the same lateral geometry
as the SOI MOSFETs but differed in oxide thickness (~500 Å for SOI MOSFET vs.
~1000 Å for bulk MOSFET) and starting p-type doping concentration (~1015 cm-3 for
bulk MOSFET and ~1016 cm-3 for SOI MOSFETs) so they may not be directly
comparable.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Figure 4-14: Plot of n-channel polysilicon TFT off-state leakage and turn-on
characteristics for conventional (conv.) polySi and increased grain size (new) polySi
films. The inset shows the effective electron mobility as a function of gate bias. . 189

Figure 4-15: I-V characteristic for amorphous silicon TFT . . . . . . . . . . . . . . . . . . 192

xviii
 LIST OF TABLES

Table 1-1: Comparison of several parameters associated with displays. CRT is

cathode ray tube, PM-LCD is passive matrix addressed LCD, AM-LCD is active
matrix addressed LCD, and OLED is for active matrix addressed organic LEDs. The
passive and active addressing methods are discussed below.. . . . . . . . . . . . . . . . . . 15

Table 1-2: Specifications for Corning 1737F glass from Corning. . . . . . . . . . . . . . 22

Table 2-1: Bond strengths of wafer pairs before annealing. The bond strengths are
the same regardless of whether plasma activation was done or not. . . . . . . . . . . . . .69

Table 3-1: RMS roughness of PIII silicon on glass for the different implantation
modes as measured by AFM. Short pulse = 30 µs/300Hz, Long Pulse = 300µs/75Hz..
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 3-2: thermal donor type as a function of anneal temperature range. . . . . . . 112

Table 3-3: Hall effect and hot probe measurement data for DC mode PIII silicon on
glass. The sheet charge as a function of time was plotted in figure 3-10. Hot probe
measurements only give conductivity type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 3-4: measured strain values of the film after correcting for the substrate and
film offcuts using a triple axis X-ray diffractometer. . . . . . . . . . . . . . . . . . . . . . . . 143

Table 4-1: Summary of MOSFET characteristics for hot cut, cold cut and bulk Si.
The mobility listed is the field effect mobility. (W/L = 128/38) . . . . . . . . . . . . . . 190

xix
 ACKNOWLEDGEMENTS

I would like to thank my advisors Paul Yu and S.S. Lau for their advice and

for looking out for me, Arthur Clawson for advice and practical expertise, Drs.

Robert Welstand, Guoliang Li, Rebecca Welty, Yimin Kang, Philip Mages, Paul

Rosenthal and Ivan Shubin for helpful advice, moral support and for asking

questions that mattered, Justin Bickford and Clint Novotny for helping out with the

X-ray diffraction measurements, Ming Cai for his enthusiasm and very helpful

discussions, Michelle Parks for her quick administrative assistance in all sorts of

matters, Professor Karen Kavanagh (now at Simon Frasier University, B.C., Canada)

for giving me a starting glimpse of graduate school and a taste of materials science,

Chris and Teresa Mckinney for encouragement and dietary support, my high school

science teachers, Ms. Wilder (O’neil), Mr. Emmerson, and Mr. Stimson, who made

science fun, and last but not least my family who pushed and guided me along this

path.

xx
 VITA

1996 B.S. Engineering Physics, University of California, San Diego

1998 M.S. Materials Science and Engineering,

University of California, San Diego

1996-2003 Teaching Assistant, Dept of ECE, University of California, San Diego

2004 Ph.D. Materials Science and Engineering,

University of California, San Diego

PUBLICATIONS

F. Lu, D. Qiao, M. Cai, P. K. L. Yu, S. S. Lau, R. K. Y. Fu, L. S. Hung, C. P. Li, P.

K. Chu, H. C. Chien, and Y. Liou, “Ion-Cutting of Si onto Glass by Pulsed and
Direct-Current (DC) Plasma Immersion Ion Implantation”, Journal of Vacuum
Science & Technology B 21(5), Sep/Oct 2003.

F. Lu, J. Bickford, C. Novotny, S.S. Lau, P. K. L. Yu, K. Henttinen, T. Suni, and I.

Suni, “Strain and Material characterization of mechanically and thermally
exfoliated silicon films”, Submitted to Journal of Vacuum Science & Technology A.

PRESENTATIONS

F. Lu, D. Qiao, M. Cai, P.K.L. Yu, S.S. Lau, R.K.Y. Fu, C.P. Li. L.S. Huang, Paul.
K. Chu; “Characteristics of Si thin films transferred onto glass by ion-cut
employing pulsed and direct-current (DC) plasma immersion ion implantation”
2003 TMS Electronic Materials Conference, Salt Lake City

xxi
 ABSTRACT OF THE DISSERTATION

Electrical characterization of thermally and mechanically exfoliated silicon films for

flat panel display applications.

By

Felix Paul Lu

Doctor of Philosophy in Materials Science and Engineering

University of California, San Diego, 2004

Professor Paul K.L. Yu, Chair

Professor S.S. Lau, Co-Chair

For the next generation of flat panel displays (FPDs), higher resolutions and
sharp, full motion video are expected. To meet these requirements, high quality
semiconductor material on glass substrates are a desirable way to fabricate the thin
film transistors (TFTs) needed to drive the pixels and to quickly and precisely
control the currents. Single crystal silicon films can be exfoliated onto Corning
1737F glass substrates using ion-cutting techniques. Because the ion-cutting
technique requires ion implantation through the film material, the electrical
properties of the exfoliated film have to be examined to understand the behavior as it
goes through temperature cycling inherent in the TFT fabrication process. After the
film exfoliation, Hall effect, hot probe and four point probe measurements are used
along with layer by layer etching to get a picture of the carrier depth distribution.
The electrical properties of mechanically exfoliated and thermally exfoliated films
are compared and discussed in the context of using these for MOSFETs. Finally, p-
MOSFETs are fabricated and the transistor parameters such as leakage current,
subthreshold slope, on/off current ratio and mobility compare and contrasted with
MOSFETs made from bulk silicon. The mechanically exfoliated films show superior
performance with respect to the p-MOSFET off-state, drain to source leakage current

xxii
compared to the thermally exfoliated films. This difference is attributed to the lower
temperature the mechanically exfoliated film is subjected to even before film
delamination. The temperature difference of the exfoliation temperatures is
responsible for a higher density of oxide precipitates in the thermally exfoliated film
which leads to higher leakage currents.

xxiii
Chapter 1 Introduction

1.1 The evolution and requirements for flat panel displays

DISPLAYS - PURPOSE

The purpose of a display is to convey information to the viewer. Electronic

displays do this by transforming electrical signals to a visible image. For the image to

efficiently convey information, it should be able to resolve very finely detailed aspects

of the image. To do this requires the display to have a dense array of points which can

be individually controlled in color and brightness. Since the advent of the computer,

the display has been the main output component which then allows user interaction

with the electronics. The cathode ray tube (CRT) was the initial, popular display form

which allowed the convenient output of information from the computer. However, the

CRT was large in volume and weight due to its requirement for a vacuum for the

electrons to travel through; but since the computers were not intended to be easily

portable at the time, it made little difference. As the popularity of portable, “notebook”

type computers increased, the requirements for the flat panel display (FPD) became

increasingly strict. Due to power limitations from the battery, economics, and weight

considerations, the ideal FPD has to be thin, lightweight, consume minimal amounts

of power, have a high resolution, have a sufficiently high brightness (be sunlight

readable), and have a reasonably low cost. The amount of power the display draws

compared to other subcomponents of a portable computer is shown in Figures 1-1 and

1-2. To incorporate all these features into a single device is not a trivial task. This

thesis will focus on how to create a high quality material layer structure which will, in

1
 2

turn, allow the minimization of power consumption while maintaining high brightness

and low pixel turn-on/off times, as will be explained in the following sections.

Figure 1-1: Relative power consumption of various subcomponents of a portable

notebook type computer with an LCD flat panel display. [After Pochang Hsu et
al., “Developing low power mobile platforms” Intel Developer Forum, Spring
2001]

Displays in computer systems were initially designed to show static images.

However, full motion video at frame rates (a.k.a. vertical refresh rate) of 24 frames per

sec (fps) and higher are now commonplace. The capability to clearly display video

information is required for the display to be useful. The display attributes required to

clearly display a series of fast moving images are the on-to-off contrast ratio and the

response time of the picture element (pixel). The contrast ratio, which is essentially

how well the pixel can turn off (become black) compared to the brightness level,

should be as high as possible and the on-off response times should be as short as
 3

possible. Ideal response times have the shape of a step function with an "on time"

(total time the pixel is on during 1 frame, and not to be confused with “turn-on” time)

of 1/(frame-rate × number of horizontal pixels per row). As will be shown, the

response times, contrast ratios and power consumption are a strong function of the

technology used to implement the pixels.

Platform Idle power consumption

LCD 15"

GFX

Power Supply Loss

HDD

Audio/Modem

PIII 600 MHz 1.3V

Card Bus

I/O subsystem

0 1 2 3 4
Idle power consumption (W)

[Data from Pochang Hsu et al., “Developing low power

mobile platforms” Intel Developer Forum, Spring 2001]

Figure 1-2: Power draw of various subcomponents of a portable notebook type

computer.

The vertical screen refresh rate can be compared to the shutter speed on movie

projectors which use film to display still images one frame at a time. The faster the
 4

shutter speed, the more frames you can display per unit time and hence, the more

subtle the movement can be per frame. Perhaps the main difference between this type

of movie projector and a FPD is that because the light source used in a projector is

always on, the shutter (or chopper) is the mechanism which determines the frame rate.

Thus, each frame is displayed all at once. With an FPD, the pixel data supplied into

the display is input, not one frame at a time but serially, pixel by pixel per horizontal

line. Because the information is supplied at a sufficiently high rate, the picture can be

drawn quickly enough. The limiting factor lies not with the input rate to the FPD, or

with the switching rate of each pixel, but with the signal used to control the switching

characteristics of the pixel. The higher the density of pixels, the shorter the amount of

time allowed to address each pixel. For current controlled devices such as OLEDs, this

is a tradeoff between brightness (more current means more photons generated), and

lifetime. To produce high brightness displays would then require the OLEDs to be

driven with high currents which would then decrease the lifetime of the pixels. For

notebook type computing, driving the displays at a higher power quickly depletes the

limited power source, but arguably more important, especially with current driven

emissive displays, is the off-state leakage current. After all, a pixel that is not emitting

light should ideally not draw any power.

DISPLAY PARAMETERS
 5

The basic metrics that characterize the display are the pixel density and the

screen dimensions. The trend is to increase the pixel density. The physical screen

dimensions (typically given by the diagonal length or the side length and the screen

aspect ratio) also tend to increase but are restricted from increasing indefinitely in

portable computer FPD applications as a tradeoff for portability. In CRTs, each pixel

is individually addressed until all the pixels in the whole display have been addressed

before the cycle restarts. That means that the larger the pixel density, the shorter the

time each

Figure 1-3: Evolution of screen size and pixel density for notebook flat panel
displays. ppi stands for pixels or points per inch, VGA, SVGA, XGA, SXGA, and
UXGA signify the display resolutions and are 640×480, 800×600, 1024×768,
1280×1024, 1400×1050, and 1600×1200 pixels respectively. The numbers are the
horizontal × vertical number of lines in the screen. [After Kai Schleupen, IBM
(M.I.T. 6.976 Flat panel display devices, spring 2001)]
 6

pixel is addressed. Since pixel brightness is proportional to the pixel addressing time

for FPDs and CRTs, the shorter time means that the display brightness will be

comparatively reduced as mentioned above.

PIXEL TYPES - EMISSIVE AND LIGHT VALVE

In a display, there are two classes of pixels: emissive and light-valve. Emissive

pixels emit light when stimulated and otherwise remain inactive (off). Light-valve

pixels are color shutters which selectively allow the partial transmittance of a broad

band light source behind the pixel plane. Emissive pixels are typically current driven

whereas the shutters in the light-valve pixels are typically voltage driven. Examples of

emissive pixels include phosphors in CRTs, plasma displays where the phosphors

luminesce by electrons generated in the plasma; field emission displays, where an

array of sharp metal tips and a large electric field are the source of electrons for the

phosphor, and electro-luminescent (EL) or light emitting diodes (LEDs). Examples of

light-valve pixels include backlit liquid crystal displays (LCDs) and reflective displays

which reflect ambient light back to the observer. The backlight in the light-valve

displays can be any broad spectrum light source and are typically fluorescent lights or

an array of bright, white colored LEDs which are always on. (It is conceivable that an

array of bright, white LEDS could also be "rastered" along with the screen signal to

make it more energy efficient but that also makes the device more complex than it has

to be.)
 7

EMISSIVE PIXELS

The phosphors in a CRT are a common type of emitting pixel. The light

emission occurs when electrons strike the phosphor (cathodoluminescence). The

electron source in a CRT is typically a heated filament at the back of the vacuum tube

and the electron beam is steered by electrode plates to the phosphor screen. Because

the electrons have to travel some distance (on the order of several centimeters to tens

of centimeters), a high vacuum is required to ensure the mean free path of the

electrons is long enough such that enough electrons arrive at the phosphor screen. A

high vacuum requirement means that the tube must be constructed in a way to provide

the necessary strength so as not to collapse under the weight of the atmosphere.

Because of this, the CRT is typically very heavy and large in volume which is not

suitable for portable applications. Advantages of the CRT are relatively simple design

and operation which result in low cost.

Flat paneled variants of the CRT are the plasma display and the field-emission

display. Rather than having a single source of electrons at the back on of a large

vacuum tube, an array of electron sources is available very close to the front phosphor

screen. In a plasma display, a plasma is generated in a small chamber behind each

pixel by the application of a large potential between parallel electrodes. The plasma is

the source of charged particles which strike the phosphor causing it to light up. With a

field-emission display, each sharp metallic tip is biased such that the electric field is

extremely strong and the work function for electron emission is lowered causing

electrons to strike the phosphor. Both of these techniques require rugged construction
 8

to maintain the pockets of vacuum and/or gas for the plasma, making these displays

relatively heavy. More recently, however, Fujitsu has developed a plasma display for

large scale applications (1200 mm × 1800 mm) (i.e. cannot be easily scaled down for

personal notebook computing) which does not require lithography and is relatively

simple and economical to produce. These are fabricated using small diameter (1 mm)

red, green and blue phosphor coated tubes and passively addressed by electrodes

running the length of the tubes on one side and the width of the tubes on the front side.

This eliminates the individual pockets of gas for the plasma which form the pixels and

does away with the heavy glass plates. [IEEE Spectrum, March 2004, p. 18]

LEDs are solid-state devices and that makes them particularly attractive

compared to the previous techniques. Because they are solid state devices, there are

fewer mechanical considerations to account for in the construction of the display

frame, e.g. no vacuum to design the frame around, and thus the weight aspect for

portability takes a big step forward. However, with a solid state device, there are also

the complications of crystal growth, especially for alloys, material compatibility in

terms of lattice match and thermal expansion with films and substrates. The wiring of

LEDs, in its most basic design, is simply a connection to the cathodic and anodic ends

of the device.

LIGHT VALVE PIXELS

Light valve pixels are in their simplest form, an optical shutter. To obtain

colors, each sub-pixel is outfitted with a color filter. The blacklight source can be any
 9

broadband white light sources such as white LEDs or cold cathode fluorescent lights

(CCFLs). With LCD FPDs, the backlight is blocked or allowed to pass by controlling

the orientation of the liquid crystals with a high voltage. The main drawbacks to this

approach are that the optical transmittance is reduced due to the color filters and that

the backlight is always on. This means that the backlight has to effectively be brighter

in order to maintain a reasonably bright image, and because the backlight is always on

(even when the screen is dark), there is unnecessary power consumption.

Comparing Brightness levels

Photometric units are used in the discussion of brightness levels. The different

units and methods of measuring the brightness are defined and discussed below.

Photometric units: [1]

Light is an electromagnetic wave; and electromagnetic power or radiant flux

can be measured in Watts. However, since the human eye is responsive only to a

certain range of wavelengths, the number in Watts does not give a good indication of

how bright an object is. A weighted power measurement which is correlated with the

spectral response of the human eye is used and is known as luminous flux and has the

units of lumens. [1] A lumen is defined from 1 Watt of radiant power at 555 nm (peak

sensitivity of the eye) which is equivalent to 683 lumens. The strange choice of 683

lumens is to make the value identical to that obtained with the previous version of the

unit: the emission from 1 square centimeter of glowing, solidifying platinum.

 10

1. Luminous intensity (candle power) which has units of candela, is defined as the
light density within a small solid angle *in a specified direction*. This can be
direction dependent.

2. Luminance or Brightness is the luminous intensity of a surface in a given direction

per unit area. This has units of candela per square inch, footlambert(luminance of a
surface emitting 1 lumen/sq. foot), or lambert (luminance of a surface emitting 1
lumen per sq. cm).

3. Luminous flux (units of lumens) is the light flux emitted in 1 unit solid angle by a
1 candela uniform point source. The lumen is independent of direction, unlike the
luminous intensity, and is connected with the response of the human eye.

4. Illumination is defined as the density of luminous flux on a surface. This has units
of footcandle (illumination of a point on a surface which is 1 foot and perpendicular to
a uniform point source of 1 candela, so footcandles = lumens/area) or lux, which is
used in the S.I. system, where 1 lux = 0.0929 footcandles).
luminous efficiency is the ratio of luminous to radiant flux at a specific wavelength.

efficacy is the efficiency of converting electrical power to luminous power.

1 candela (cd) = 1 lumen/steradian

1 lux = 1 lumen/sq. meter

1 phot = 1 lumen/sq. cm

1 nit = 1 candela/sq. meter

Examples as a quick reference :[1]

Brightness scale [luminance (cd/m2)]

"typical" notebook computer flat panel LCD display - ~100

bright sunlight 3000-6000
movie theater screen 300-600
office 12-18
Full moon .0006-.006
 11

LEDs

LEDs can be classified into two subgroups: organic and inorganic LEDs. The

inorganic LEDs are constructed from semiconductor crystals and the organic LEDs are

typically a carbon based polymer chain where the periodicity of the constituents of the

chain determines the electronic and optical properties of the material. Inorganic LEDs

are grown in MBE or CVD reactors at temperatures of ~500 °C [2] because the degree

of crystallinity (or lack of defects) is required to prevent the quenching of the

recombination of carriers which produces light emission. Organic LEDs can be

vacuum evaporated or spin coated as an amorphous layer which makes them

convenient and easy to process.

Summary of OLED advantages over LCD:

• simpler design - higher yield, and less material means lower weight.

• Brighter and higher contrast with higher luminous efficiency because of

lack of color filters.
• Faster turn-on/turn-off times (~10 µs) compared to LCD (~10 ms).

• General consensus is that OLED are more power efficient because no

backlight which is always on, however, because of differences in
backlight types, brands and configurations, a direct comparison is not
easy to make.

DISCUSSION

The term "portable computing" includes, by definition, lightweight, low power

consumption, and will have a high performance which is defined to be high resolution

and the ability to show full motion video free of "ghosting effects". "Ghost effects" are
 12

seen as smears of an object as it moves across the screen and are due to pixels

switching off too slowly. This happens to fast moving objects in full motion video.

Organic LEDs are favored for the pixel elements due to their simpler design which

allows for higher yield and lower weight, for their inherently brighter intensity due to

a lack of a color filter, for their faster response and for their lack of a requirement for a

backlight which improves power efficiency and contrast ratio. CRTs and their variants

(discussed above) require specialized construction for the vacuum or gas environments

and as a result are typically heavy which rules this out for portability. Light-valve

pixels require a backlight which is always on and so will consume more power than is

necessary compared to emissive pixels.

To compare power consumption between light valve and emissive displays is

not as trivial as one might think. This is essentially because the light valve displays

have many factors which affect the net brightness of the screen such as the type of

backlight source, the aperture sizes between the light source and the color filters. The

listed luminous efficiencies of the backlights commonly used in LCD FPDs, cold

cathode fluorescent lights (CCFLs), are listed as 35-50 lumens/Watt with luminences

in the range of 27000 cd/m2 [3]. This is considerably more efficient than other light

sources, with white OLEDs listed as ~1.5 lumens/Watt with a luminance of over 1000

cd/m2. [4]

What is not known from the given information is whether the peak luminescent

efficiencies are obtained at a particular current or power and how that affects the

battery life. Also, the fact that the CCFLs are always on versus OLEDs which are only
 13

turned on adds to the ambiguity with respect to battery life. The mechanics of the

LCDs and the OLEDs also play a role. With voltage controlled color shutters (which

ideally don't draw any current). LCDs might be thought to consume less power

compared to the equivalent emissive OLED display because of the rapid switching of

the OLEDs may introduce current spikes which will draw a lot of power. However, it

has been shown that due to the MOSFET acting as a constant current source in the

active matrix addressing for OLED displays, current spikes are virtually non-existent

and thus no additional power is drawn [5]. In addition, the light valve shutters will

reduce the brightness of the backlight such that an even brighter backlight is required

to match the inherent brightness of the unfiltered emissive display.

Because of these ambiguities, we will assume without any calculation, the

general concensus (and Table 1-1) that OLED displays would be more power efficient

over LCDs based on the points mentioned previously. This does not change the main

motivation of this thesis, which is to study methods of obtaining single crystal silicon

films on amorphous substrates for the purposes of thin film transistor fabrication.

The use of OLEDs or CRTs is tied in with the flicker phenomena, which as the

name imples, is an apparent perceived brightness modulation of the screen on the

order of 10 Hz. It is more noticeable at screen vertical refresh rates of ~60 Hz and for

non-black colored dominated colors. The flicker of the screen is perceived at different

vertical refresh frequencies for different people with the general trend that above 85

Hz or so, for most people, the flickering becomes unnoticeable. This effect is

apparently a function of such factors as the gender of the user and has physiological
 14

origins along environmental factors such as the 60 Hz flickering of fluorescent lights,

etc. A discussion of this is beyond the scope of the subject matter in this thesis. 1 An

interesting observation is that the flicker effect is not observable with LCD (light-

valve) FPDs. This is assumed to be because intensity of the individual pixels are

continuously varied [6].

Figure 1-4: Side by side comparison of OLED pixel (left) and LCD pixel (right).
It can be seen that the OLED pixel has fewer layers and is thus simpler to
fabricate, not to mention correspondingly higher yields. [After
www.pctechguide.com]
Useful definitions:

Summary of acronyms used:

CRT = cathode ray tube - the typical large monitor with electron gun, beam
steering plates, vacuum tube and phosphor coated screen.

LCD = Liquid crystal display - current standard for flat panel displays: uses
backlighting (a fluorescent tube and electrically driven polarizing filters
(liquid crystal) to open and close apertures for different colored pixels.

PM = passive matrix - method of addressing individual pixels by turning on

the corresponding row and column line. Simple and effective but
limited to lower resolution and lower performance displays.

1
For an interesting and more detailed discussion, see slides from lecture 5 from M.I.T.’s 6.976 Flat Panel Display devices:
Luminescence in display technologies, spring 2001, currently on http://hackman.mit.edu.
 15

AM = active matrix - method of addressing individual pixels by using at least

1 TFT and a capacitive element per pixel as well as the row and column
addressing in PM scheme to improve response characteristics for higher
performance displays at higher resolutions.

OLED = organic light emitting diode : lighting element for pixels which is
current driven and does not require backlighting as in LCD displays.
The organic nature stems from the use of polymers as opposed to the
traditional inorganic elemental semiconductors. The use of organic
materials allows more flexibility in the tailoring of the characteristics to
optimize it for a particular application. This comes at a cost of
increased research and developmental time.

Table 1-1: Comparison of several parameters associated with displays. CRT is

cathode ray tube, PM-LCD is passive matrix addressed LCD, AM-LCD is active
matrix addressed LCD, and OLED is for active matrix addressed organic LEDs.
The passive and active addressing methods are discussed below.

DISPLAY VIEWING CONTRAST RESPONSE BRIGHT OPERAT- POWER LIFE-

TYPE ANGLE RATIO SPEED -NESS ING (W) TIME
(cd/m2) VOLTAGE
(V)
CRT > 190 ° 300:1 ~< 1ms * 220-270 100’s + ~180 Years
PM-LCD ~49-100 ° 40:1 300 ms 70-90 100’s + 45 60K Hrs
AM-LCD > 140 ° 140:1 25 ms 70-90 100’s + 50 60K Hrs
OLED > 160 ° 100-250:1 ~< 1ms 150 5 < 50 ** Depends
***

references: http://www.kodak.com (KODAK website) and http://www.pctechguide.com/07pan3.htm

* based on response time of phosphor
** the power consumption for OLED based displays was not listed at the time but based on the fact that
there is no backlighting, it is probably less than the AM-LCD power consumption.
***Lifetime of OLEDs will vary inversely with brightness

1.2 Organic light emitting diodes

The basic structure of organic light emitting diodes (OLEDs) is the same as the

conventional (inorganic) LED. There is a p-n junction and contact layers to the p and n

type material for the cathode and anode. As current is injected into the junction,

electrons combine with holes and emit light at a specific energy determined by the

material(s) at the junction. One feature with OLEDs is that the materials which make
 16

up the layers of the diode are not required to be grown at high temperatures as do

semiconductor layers. This is possible through the use of polymers which can be

chemically designed to have the desired electrical conduction and energy gap among

other properties. With the LED, a recombination (depletion) region is naturally

formed, however with the OLED, a separate layer is used for the light emitting area

(figure 1-5).

There are two classes of polymers that are used for the light emitting layer.

They are differentiated by the size of the molecules of which they are composed from

– “small molecules” and “long molecules” (conjugated polymers). The most common

small molecule material used is hydroxyquinoline aluminium (Alq3) and the most

common conjugated polymer used is poly-paraphenylene-vinylene (PPV). The

materials are organic because of a carbon backbone present in the molecules. The

electronic conduction is apparently done through the bonds which are orthogonal to

the backbone [7]. A characteristic of the molecule, the conjugation length,2 which is

determined by the length of the molecule, determines the effective bandgap of the

material. A long conjugation length (like the PPV material) results in a smaller

bandgap and a short conjugation length (like the Alq3) results in a larger bandgap. This

makes the PPV material more suitable for emitting longer wavelength light (e.g. red

light) and the Alq3 material more suitable for shorter wavelength light (e.g. blue light).

The simplest diode structure is an organic layer sandwiched between the cathode and

2
The conjugation length is the number of alternating single and double bonded molecules that are tied together. This
single/double alternating bond configuration allows a smaller energy separation between the split energy levels when single atoms
are merged together to form a molecule. The longer the conjugation length the closer energy levels.
 17

anode. Over the years, researchers have migrated to a multilayer structure which

optimizes the properties of the layers (figure 1-5).

Some notable drawbacks include short lifetimes for blue emitting materials and

that the OLED typically has to be encapsulated due to sensitivity to moisture [8]. The

organic materials might also be difficult to work with since they may not be

compatible with current commonly used solvents, which are commonly used to

Figure 1-5: Layer structure of organic light emitting diode. The EIL and HIL
layers are basically contact layers, and the ETL and HTL layers are basically the
n and p doped layers. The anode and substrate have to be optically transparent.
[After Patrik Stark and Daniel Westling, Master’s Thesis, Dept of Science and
Technology, Linköping University, Sweden 2002]

remove organics in the lithographic process [9].

1.3 Pixel addressing

All modern FPDs are active matrix displays, as opposed to passive matrix

displays. All this means is that each pixel is controlled by it's own transistor(s) to

regulate when and how much current should be pumped in, in order to maintain the
 18

desired brightness. With earlier FPDs, the picture and video requirements were less

demanding in terms of frame rate, resolution and power consumption, and so the

simpler approach to fabricating FPDs (i.e. passive matrix addressing) was justifiably

taken.

Passive matrix addressing of the pixels was done by using a grid of wires. The

light emitting elements were at the intersection points of the wires (figure 1-6). When

a particular pixel was to be lit, the wires corresponding to the coordinates of the pixel

V
Figure 1-6: Schematic of simple passive matrix (left) and active matrix (right)
grids. The active matrix has at least 1 TFT at each pixel location as shown by the
MOSFET icon.

were given a voltage. The combination of the voltages from the 'x' wire and the 'y'

wire was enough to overcome the potential barrier of the diode and cause it to light up.

The problems associated with this approach were rooted in scaling to larger displays

and higher resolutions (which degraded picture quality). The cause was due to several

factors:

- the metal grid lines had to be thinner so they wouldn't stand out compared
to the size of the pixels. This resulted in the current density being higher
which led to larger ohmic losses
 19

- the fact that in order to scan the voltages across the array of wires, it
became more difficult to control precisely how much current was going
into the pixels and thus how bright they were supposed to be.

For example, to scan across 240 pixels, each pixel would receive a pulse of current

that was 1/240 of the frame time. [For arguments sake, let us assume that frame time is

1/60 of a second (60 Hz vertical refresh rate)] To double the number of pixels would

halve the time of the pulse applied to the line. This would limit the current with the

result of reducing the brightness. Reducing the brightness reduced the quality of the

picture being displayed. A remedy to this problem was to increase the magnitude of

the pulsed currents such that the average current injected gave the desired brightness.

While this worked, the tradeoff was that the lifetime of the emissive elements was

drastically shortened due to the high currents. Active matrix addressing of pixels

became popular because of the limitations of passive matrix addressing. With active

matrix addressing, at least one transistor acted as a current buffer between the grid

lines and the diode element. The idea was that, the current would be conditioned and

controlled such that the optimum amount was injected into the diode junction to

produce the desired brightness without excessive currents. The tradeoff was then

added complexity in the fabrication steps and as a consequence, reduced

manufacturing yield.

1.4 Optimization of active matrix addressing

The definition (in relation to the resolution and contrast) of the image

displayed is directly correlated with the consistency of the brightness of the

appropriate pixels. For emissive pixels, the brightness of the pixels are directly
 20

proportional to the magnitude and uniformity of the current passing through them.

With passive matrix addressing, in order to obtain a brightness level for comfortable

viewing, the pulsed current has to result in a brightness level, averaged out over the

pulse period, that gives the desired average brightness. This, as was mentioned, leads

to a reduction in pixel lifetime as well as a lower quality image because it now

depends on the decay time of the charged up device, which may vary from point to

point on the display screen, resulting in non-uniform brightness in random spots. To

improve on this, a uniform current profile with sharp turn on/off times are required

and can be done with configurations of two to four MOSFETs (figure 1-7).

Figure 1-7: 2 TFT configuration for active matrix control of pixel. The input
TFT (Q1) allows charge to flow into the storage capacitor, which holds Q2 on,
turning on the LED. The second half of the cycle reverses the charge, discharging
the capacitor. [After Stewart et al., 2001]

The storage capacitor is charged up and holds the voltage to the current controlling

gate for the period of the pulse width with a constant current. To quickly charge up the

capacitor, a large current is necessary. A relatively high mobility requirement for the

input MOSFET can help meet this requirement.

 21

For the case of one MOSFET per pixel, the current into the OLED is buffered

but not quite to the extent that the current profile is uniform. However, this makes a

good reference point for calculation of worst case requirements: The average current

necessary to produce a reasonably bright display of ~100 cd/m2 is about 10 mA/cm2

[10]. For a 21" display (diagonal) with a 2048 × 2048 pixel resolution (side length is

15 inches or 381 mm) the pixel length is 62 µm (for each of the red, green and blue

sub-pixels]. Let's assume 50 µm × 50 µm pixels for convenience, that means that a

current of 0.25 µA is required when the pixel is lit. The screen is rastered at a fixed

vertical and horizontal frequency (refresh rate) and so the higher the resolution the less

time each pixel is connected to the signal. Only the vertical screen refresh rate is of

consequence here because for video images the pixel should ideally be on for the

whole frame. For a resolution of 2048 pixels, the on-time for each pixel is then (the

number of address lines of the frame time)-1, or (1/2048)(1/100Hz) = 5 µs/pixel. This

was assuming that 100 Hz is the vertical refresh rate (has to be greater than 60 Hz for

flicker free display). In order to maintain an average current of 0.25 µA (for the worst

case scenario of the whole line being turned on) each transistor will have to be able to

sustain a maximum current load of 0.25 µA × 2048 = 0.5 mA. Assuming that the

MOSFET is operating in the saturation region (to minimize fluctuation in current with

small changes in Vdrain)

I max
µ=
W
C ox (Vgs − Vth ) 2max
2L
 22

the worst case required mobility is ~100 cm2/V⋅s depending on the actual pixel size,

which affects how much current is required (using Imax = 0.5 mA, W/L=2, Vgs-Vt = 10

volts, Cox = εSiε0/d is normalized to channel area, and d = 500 Å). This requirement is

for the worst case (and not ever used because 1 TFT/pixel would not include the

capacitance element needed) and is extended from the current high end FPDs on the

market. Using two or more TFTs per pixel significantly reduces the drive requirements

and thus the mobility requirements [11]. This is because the driving current is not the

same current used to light up the LED.

1.5 Material requirements for FPDs

For flat panel displays, at least one side has to be transparent so that the image

can be displayed. This transparent and mechanical backplane are required to have a

reasonable cost, to be chemically resistant to the process chemicals used, and to have

as high a strain point as possible so that the various processes are not restricted and to

have a coefficient of thermal expansion close to that of the semiconductor material

Table 1-2: Specifications for Corning 1737F glass from Corning.

Description – Alkaline Earth Aluminosilicate

Forms Available – Fusion drawn sheet
Principal Uses – Substrates for Active Matrix flat panel displays
3
Density (20 ºC, 68 ºF) 2.54 g/cm
37.6×10 / °C
-7
Expansion
14.5 o
Strain Point (10 poises): 666 C
o o
Dielectric Constant : 5.7 (20 C/68 F – 1 kHz)
 23

bonded to it. The strain point of a glass is defined as the highest temperature before

viscous flow of the glass occur. There are several kinds of glass made by Corning that

satisfies all these properties to varying degrees that was especially created for flat

panel display applications. The one that was used for experiments in this thesis was

Corning 1737F glass. It is a alkaline earth aluminosilicate and has specifications as

shown in Table 1-2 [12].The simplest approach to fabricate the TFT drivers on this

glass requires that the semiconductor material be deposited first on the glass. Herein

lies the first of many problems in making a high performance display. The starting

material is undoubtedly very important in the final performance the devices. Ideally,

single crystal material offers the best combination of high carrier mobility and low

leakage currents. Growing single crystal material on amorphous glass has been

difficult if not impossible. The easiest choice was then amorphous silicon because this

could be sputtered onto arbitrarily large glass sheets and the inherent nature of the

material resulted in extremely low leakage currents (figure 1-8). However, the same

feature of amorphous Si, which was its lack of atomic order that allowed low leakage

currents, also caused the carrier mobility to be exceedingly low. With such a low

mobility, the displays fabricated from this technology could only support low

resolutions and sizes, not to mention fast, full motion video due to the slow response.

The next major step in material quality developed to address the extremely low

mobility involved recrystallizing the deposited amorphous Si layer by various methods

including laser annealing and metal induced crystallization. Laser annealing, also

called excimer laser annealing (ELA) or pulsed laser annealing, uses XeCl excimer
 24

laser pulses at temperatures lower than 300 °C at a pressure lower than 10-6 Torr to

recrystallize amorphous hydrogenated silicon films with an energy density of about

160 mJ/cm2, the threshold of crystallization.[13]

Figure 1-8: Semi-log plot of I-V characteristic for amorphous Si TFT. Note the
extremely low reverse bias leakage current. [After R.A. Street and P. Mei]

There is also an amorphization threshold which is higher than the crystallization

threshold [13]. In order to get large grain sizes (or minimize grain boundaries and to

hopefully minimize leakage currents), the energy density should be just below the

amorphization threshold [14, 15]. The channel mobilities became high after annealing

(640 cm2/V⋅s for n-channel TFTs, and 400 cm2/V⋅s for p-channel TFTs) [14, 15] but

the leakage currents were also characteristically high, given as ~10-10 A/µm (at -5V

gate bias), where the “µm” refers to the gate width. The leakage current could be

reduced dramatically by using an offset [16, 17]. The offset is the shortening of the
 25

gate length such that it is shorter than the channel it covers (see figure below, fig 9 on

ref. 20, A. Kohno et al.). It was determined that the excess leakage was from high

electric fields near the drain region. So moving the gate edge further away reduces this

as shown in the plot (also figure 9 of ref. 20).

Metal induced crystallization is the formation of a polycrystalline silicon phase

from an amorphous phase using a thin metal layer as a form of energy barrier reducing

stage. It apparently works only with Pd and Ni [18, 19], has been studied and a lot of

experimental data has been collected [20,21] but the phenomena is still not well

understood. The result, nevertheless, is that the (poly)crystallized area contains a high

Figure 1-9: MILC schematic of the layer structure (left). The right half shows
a zoomed in area near the gate edges. This indicates that the gate edges hardly or
do not see the metallic contamination. [After T.-H. Ihn, et al., 1999]
 26

concentration of metals which is required for the crystalline phase to form. The

metallic atoms would introduce deep level states within the energy gap and increases

leakage currents, so another method, metal induced lateral crystallization (MILC) was

developed which would minimize the amount of metals in the (poly) crystallized area.

A method of offsetting the metal layer such that it is not too close to the channel area

allows the recrystallized area to be relatively free of metal impurities was developed

by T-H Ihn et al.[22] as shown in figure 1-9. The reduction of metals shows a dramatic

improvement over the conventional crystallization method. While this is a good

approach, it can possibly be improved by complete elimination of metals using single

crystal films to start with.

The device characteristics for recrystallized poly-Si films is reasonably good,

but for ever higher resolutions and lower power consumption due to massive

integration of many devices, even these properties have to be improved. A further

improvement is to use single crystal films on glass. Single crystal films offer high

mobility due to the crystal lattice and low leakage currents due to the lack of grain

boundaries. One way to obtain single crystal films on an amorphous substrate is to use

wafer bonding and thin film exfoliation techniques such as Smart-CutTM.

1.6 Wafer bonding and film exfoliation.

Wafer bonding and thin film exfoliation is an alternative to depositing a high

quality film on the amorphous substrate. Arguably, the main requirements for wafer

bonding are that the two substrates to be bonded be flat and smooth enough. The

wafers should have a total thickness variation (TTV) of less than ~5 µm and an RMS
 27

roughness of < ~5-10 Å [23]. Two wafers are cleaned to be free of particulates,

pressed together and annealed at elevated temperatures to accelerate the formation of

covalently bonded siloxane (Si-O-Si) structures between the surfaces of the two

wafers. The end result is that the two wafers will not be able to be separated without

breaking either wafer. The elevated temperatures used are typically around 1000 ºC.

With respect to the application in this thesis, that temperature is unsuitable due to the

use of the Corning 1737F glass substrate which has a strain point of 666 ºC.

Fortunately, it turns out that by using plasma activation of the surface, the annealing

temperature can be reduced to < 400 ºC while still attaining the same interwafer bond

strength. The mechanisms behind this are not well understood but there is some

interesting data which may enhance our understanding. The potential mechanisms are

discussed in chapter 2.

To exfoliate a thin film, the ion-cut or Smart-CutTM technique is used: a donor

wafer is first ion implanted with hydrogen ions to a characteristic depth which depends

on the energy, substrate, and dose (typically 1500-5000 Å). This donor wafer is

bonded using the low temperature plasma activation technique. The pair is annealed at

~300 ºC for several hours to strengthen the bond. When the anneal temperature is then

raised to ~450 ºC, the layer of hydrogen causes bubble nucleation [24] at the implant

depth and splits the surface layer from the rest of the donor substrate. Cross sectional

TEM evaluation of the surface reveals that there is a heavily damaged layer (not quite

crystalline) and a crystalline layer which may have some defects from the ion

implantation.
 28

1.7 Thesis overview

This thesis will investigate the aspects of using low temperature plasma

assisted surface activation for wafer bonding, film exfoliation onto glass and thermal

oxide, electrical and optical characterization of these films and finally the performance

of the MOSFET drivers that are designed for use in flat panel display applications.

The reasons for choosing organic light emitting diodes as the lighting element has

been discussed earlier in this chapter and it is from the requirements of these elements

among other processing restrictions that set the boundary conditions and specifications

for the devices and ultimately the material. The details of creating a good display for

flat panel applications which include features such as high brightness, high contrast

and the ability to display sharp, moving images will lead to the requirements for the

current limits, and turn on/off times of the TFTs. This is directly related to the

mobility and leakage current limits of the material for a given TFT control

configuration. Keeping this in mind, the process procedures and requirements will be

described in detail with particular attention to the practical aspects and how this is tied

in to the device characteristics. There will be a foray into the possible mechanisms for

why the plasma activation is able to create strong bonds and some ideas for future

research which may be able to elicit the mechanics in more detail. In an attempt to

better understand the behavior of the exfoliated thin films, films were exfoliated onto

wet thermal silicon dioxide so that higher anneal temperatures could be used. This

opens up a host of new doors which can be divided up into two main categories

depending on the exfoliation mechanism (hot cut or thermal exfoliation, and cold cut,
 29

or mechanical exfoliation). This naturally led to the comparison of MOSFETs

fabricated on both types of substrates (using the two different exfoliation methods).

The aim of this thesis is then, to explain why there are electrical differences

between the mechanically and thermally exfoliated silicon films by hydrogen ion

implantation and how these differences affect MOSFET device performance.

 30

1.8 References
[1] Mikhail Dubinovsky, lighting Frequently asked questions white paper, High
end systems, 2105 Gracy Farms Lane, Austin, TX 78758 USA; David Gibson,
BCRA Cave radio & electronics group, Journal 27, Sept. 1997, page 9.; white
paper from Electro Optical Industries, Inc., 859 Ward Drive, Santa Barbara CA
93111

[2] H.P. Xin, C.W. Tu, Yong Zhang, A. Mascarenhas, Appl. Phys. Lett. 76
(2000):1267

[3] Soonseok Lee, Sungkyoo Lim, J. of the Inst. of Electron. Eng. of Korea Sd,.
vol.39-SD, no.12, Dec 2002, pp.16-21

[4] T.A. Ali, A.P. Ghosh, W.E. Howard, Society of information display 1999
International symposium. 1999, pp. 442-5.

[5] R.M.A. Dawson et al. "The impact of the transient response of organic light
emitting diodes on the design of active matrix OLED displays", 1998 IEEE
IEDM, p. 875

[6] http://www4.tomshardware.com/display/99q2/990624/tft1-08.html

[7] Patrik Stark, Daniel Westling; Master's Thesis : OLED . Evaluation and
clarification of the new Organic Light Emitting Display technology,
Department of Science and Technology, Linköping University SE-601 74
Norrköping, Sweden, pp. 10

[8] T. Tohma, Yamazaki S, Wzorek D. The future of active-matrix organic LEDs.

Information Display, vol.17, no.11, Nov. 2001, pp.20-3.

[9] D. Pribat, F. Plais, Thin Solid Films 383 (2001) 25-30

[10] C.W. Tang and S.A. Van Slyke, Organic electroluminescent diodes, Appl.
Phys. Lett., vol.51 pg. 913-5, 1987

[11] Stewart M, Howell RS, Pires L, Hatalis MK. Polysilicon TFT technology for
active matrix OLED displays. IEEE Transactions on Electron Devices, vol.48,
no.5, May 2001, pp.845-51.

[12] Corning specification sheet for 1737F glass, http://www.corning.com

[13] A. Kohno, T. Sameshima, N. Sano, M. Sekiya, and M. Hara; IEEE Trans. Elec.
Dev., Feb. 1995, vol.42, (no.2):251-7
 31

[14] J.S. Yoo, C.H. Kim, K.C. Park, M.K. Han; (Edited by: Morreale, J.)
Conference Record of the 1997 International Display Research Conference and
International Workshops on LCD Technology and Emissive Technology,
(Conference Record of the 1997 International Display Research Conference
and International Workshops on LCD Technology and Emissive Technology,
Proceedings of 1997 International Display Research Conference and
Workshops, Toronto, Ont., Canada, 15-19 Sept. 1997.) Santa Ana, CA, USA:
Soc. Inf. Display, 1997

[15] H. Wang, M. Chan, S. Jagar, V.M.C. Poon, M. Qin, Y. Wang, P.K. Lo; IEEE
Trans. Elec. Dev., Aug 2000, vol.47, (no.8):1580-6

[16] G.A. Bhat, Z Jin, H.S. Kwok, and M. Wong, Effects of longitudinal grain
boundaries on the performance of MILC-TFT’s, IEEE Electron Device Lett.,
vol. 20, pp.97-99, Feb 1999

[17] J.E. Palmer, C.V. Thompson, and H.I. Smith, Grain growth and grain size
distributions in thin germanium films, J. Appl. Phys., vol. 62, pp. 2492-7,
Sept. 1987

[18] S.W. Lee, Y.C. Jeon, S.K. Joo; Appl. Phys. Lett., 1995; 66(13):1671

[19] S.W. Lee, S.K. Joo, IEEE Elec. Dev. Lett. 1996; 17(4):160-2

[20] Konno, T.J.; Sinclair, R. Metal-contact-induced crystallization of

semiconductors. Materials Science & Engineering A (Structural Materials:
Properties, Microstructure and Processing), vol.A179-A180, (Eighth
International Conference on Rapidly Quenched and Metastable Materials,
Sendai, Japan, 22-27 Aug. 1993.) 1 May 1994. p.426-32

[21] G. Radnoczi, A. Robertsson, HTG Hentzell, SF Gong, M-A Hasan; J. Appl.

Phys, 1991; 69(9):6394

[22] T-H Ihn, T-K Kim, B-I Lee and S-K Joo; Microelectronics reliability
39(1999):53-8

[23] Q.-Y. Tong and U. Gosele, Semiconductor Wafer bonding, Science and
Technology, 1999, John Wiley and Sons, pp. 46-7

[24] Hochbauer, T.; Misra, A.; Verda, R.; Zheng, Y.; Lau, S.S.; Mayer, J.W.;
Nastasi, M. The influence of ion-implantation damage on hydrogen-induced
ion-cut. Nuclear Instruments & Methods in Physics Research, Section B
(Beam Interactions with Materials and Atoms), vol.175-177, (Ion Beam
 32

Modification of Materials. Twelfth International Conference, Canela, Brazil, 3-

8 Sept. 2000.) Elsevier, April 2001. p.169-75

[25] R.A. Street, and P. Mei, Amorphous and Poly-Silicon materials and devices for
large area electronics, conference slides. (no year listed)
Chapter 2. Wafer bonding

Wafer bonding is the permanent joining of two ultra-flat, ultra smooth surfaces

without the use of a secondary medium, e.g. some kind of glue. The basic idea is to

bring the two surfaces as close to each other so that chemical bonds can form. The

difficulty comes about because microscopically, the surface is never perfectly flat.

This is usually dealt with by annealing at high temperatures so that mass flow can

occur and maximize contact area. An alternative is to use plasma activation of the

surface to effectively carry out the same idea but with an added feature: the formation

of the wafer-to-wafer bonds will maximize at much lower temperatures. This will be

the main focus of this chapter. For silicon wafers, there are two types of bonding:

hydrophilic bonding and hydrophobic bonding. Hydrophilic bonding is the bonding of

two oxidized surfaces and hydrophobic bonding is for two bare Si surfaces (no oxide).

In this thesis, hydrophilic bonding is dealt with exclusively.

Overview of the process:

The wafer surfaces are physically (gently scrubbed) and chemically cleaned.

The wafers are then contacted (hoping that no particles get between them) and

annealed. The annealing increases the bond strength (or bond energy) a small amount

for low temperatures and a much larger amount for high temperatures (~ >800 °C [1].

The characterization of bond strength is done by insertion of a razor blade between the

wafers and measuring the crack length that is formed. The shorter the crack length, the

stronger the bond. The details will be discussed in detail later in this chapter.

33
 34

Annealing at temperatures in excess of 800 °C brings the bond strength close or equal

to the fracture strength of Si. This means that the bond between the two wafers

approaches the fracture strength of the Si wafers and that using the blade insertion

method of measuring the bond strength could result in the wafers breaking. More

recently, it was discovered that by using a plasma to “activate” the surface before

contacting the wafers together, the bond strength could approach the fracture strength

of Si after annealing at relatively low temperatures of 200-400 °C. The chemistry of

this process is assumed to be essentially the same but the mechanics are not well

understood. Some data will be presented that sheds more light on this and likely

explanations discussed. Finally, Si on glass bonding will be discussed in reference to

TFT fabrication.

2.1 Wafer bonding theory

2.1.1. The wafer surface

Silicon wafers taken out of the box have a native oxide of roughly 5-10 Å. This

oxide surface may be hydrophilic or hydrophobic depending on the state of the local

oxidation conditions at that point. This is contrary to the simple, binary, method for

determining whether there is silicon dioxide on the silicon wafer surface or not.

Typically, oxidized surfaces are hydrophilic and bare silicon surfaces are hydrophobic.

The oxidized surfaces are typically hydrophilic because of the dangling hydroxol (-

OH) group at the surface. Silicon likes to form 4 bonds per atom in a 3-D lattice.

However, a surface breaks this 3-D symmetry and leaves one bond free. This free
 35

bond can potentially react with whatever is near the surface. In a solution, hydroxyl

groups attach themselves to the dangling bond to form Si-OH, (silanol groups) at the

surface of the silicon dioxide. The hydrogen then forms hydrogen bonds to nearby

water molecules (see figure 2-1), creating a thin layer of water at the surface - making

it hydrophilic. However, oxidized surfaces can also be hydrophobic to a degree when

the Si-O bonds wrap back upon the surface, closing the bond. The lack of a dangling

O atom, makes it much more difficult for water to attach to the surface. This closed

bond is an Si-O-Si, or siloxane bond. This is similar, yet different from the mechanism

which makes bare

Figure 2-1: different configurations for water attaching to silanol bonds at the
surface of the oxidized silicon surface. (a)-(c) show an isolated silanol bond, (d)
shows an associated silanol bond. [after Tong and Gosele, (1999) p. 81]

silicon hydrophobic. For hydrophobic silicon surfaces in air, the Si atoms on the

surface are terminated by hydrogen. Since hydrogen can cap each dangling Si bond
 36

due to its one free electron forming a H-Si bond, there is no room for other molecules

to latch on. The wafer bonding done in this thesis will exclusively deal with

hydrophilic bonding using a fresh, chemically grown oxide from RCA (Radio

Corporation of America) cleaning solutions.

So far, it has been assumed that the surfaces of the two wafers will contact

each other completely, and that the bonding interaction is due entirely to chemical

bonding. The surfaces of real wafers have roughness and waviness, which results in

partial contact of the surfaces (see figure 2-2). This turns out to be a very important

issue, and possibly the factor which limits the ultimate bond strength between the

wafers. There are two types of roughness that are of concern: long range roughness

Figure 2-2: Illustration of the “flat and smooth” silicon surface at the atomic
scale. The bond strength relies on the effective contact area, which can be
increased.

and short range, or atomic scale roughness. Long range roughness, or surface flatness

would be roughness that might be visible at optical wavelengths and can be

characterized by a parameter called "total thickness variation" or TTV (figure 2-3).

This is typically a parameter measured by the wafer manufacturer and is typically in

 37

micrometers. Prime grade wafers typically have a TTV of ~ < 7 µm (Virginia

Semiconductor).

Figure 2-3: Illustration of the TTV – total thickness variation used to

characterize the flatness of the silicon wafers.

If the TTV were too large, visible unbonded areas might be the result. Short range

roughness is typically measured using an atomic force microscope (AFM) and given

as Ra (mean roughness), or Rq (RMS roughness). The definition of Ra is the mean

value of the surface relative to the center plane and Rq is given as the standard

deviation of the height values within a given area [2]. This value is usually in the

single digit Angstrom to sub-Angstrom range for prime grade Si wafers. Detailed

studies of the effect of roughness on bondability have been published [3-6] so I will

not go into much detail here.

In order for two wafers to bond when they come into contact, several things

must happen. The roughness must be small enough such that the two wafers are not

only "touching" at a few points, and that the distances between the two surfaces are

not so far as to make formation of chemical bonds between them unlikely; the

chemical nature of the surfaces must be ready to react in such a way to allow chemical

bonding to take place between the wafer surfaces. (see figure 2-4)

For the surfaces to be reactive, a high density of silanol bonds should be at the

surface. These bonds will allow the eventual formation of siloxane bonds (which are
 38

much stronger) between the wafers with the chemical release of water upon addition

of thermal energy [1, p.59-61]:

Si-OH + HO-Si Æ Si-O-Si + H2O

Of course, this conversion to the stronger siloxane bonds is not expected to happen

spontaneously. For that to happen, the surfaces must be close enough to either allow

the silanol bonds to connect or for a bridge of hydrogen bonded water molecules to

form. Being a weak bond, the surface must be mostly free of particles in order to let

this start, and that is where the RCA cleaning solutions come in.

Figure 2-4: The gap between the bonded silicon wafers (or maybe to be
bonded). The water molecules are able to bridge the gaps between the silanols
proving a weak temporary bond. Closing the surface would bring the silanol
groups closer together to form a stronger siloxane bond. As is shown, the
separation is not far (~11 Å in this case). [After Tong and Gosele (1999)]
 39

2.1.2 Wafer cleaning

The RCA solutions were created at RCA labs in the 1970s [7] to remove

organic (RCA-1) and metallic (RCA-2) contaminants from the silicon surface. RCA-1

(or SC-1) is a mixture of ammonium hydroxide, hydrogen peroxide and water in a

ratio of 1:1:5. RCA-2 (or SC-2) is a mixture of hydrochloric acid, hydrogen peroxide

and water in a ratio of 1:2:6. These two solutions are used with intermediate

hydrofluoric acid (HF) dips to remove the oxides formed from the hydrogen peroxide.

The general procedure would start with an HF dip to remove native oxide, rinsing in

DI water, dipping in RCA-1 at 70-80 ºC for 7-10 minutes, rinsing in DI water, HF dip,

RCA-2 at 70-80 ºC for 7-10 minutes, with the final HF when appropriate. Naturally,

people became curious about the state of the surface after all this etching and it was

found that several factors actually increased the roughness of the chemically treated Si

surface. The RCA-1 ratio was modified to 1:1:30 (NH4OH: H2O2: H2O), essentially

reducing the quantity of ammonium hydroxide, and it was recommended that the HF

solution be dilute (0.5-2 % HF in de-ionized water) [8-10]. The RCA-1 solution

works by using NH4OH as a slow oxide etchant [11] along with the H2O2 as the strong

oxidizer. Because of this, RCA-1 can lift particles that have been embedded or are just

strongly attached (by Coulombic attraction) to the oxide surface. It also keeps particles

from redepositing back onto the surface by charging both the particle and wafer with a

negative potential [12,13]. This potential is created when the surfaces adsorb the OH-

groups. In addition to the chemical cleaning, megasonic cleaning is often used.

Megasonic cleaning uses ~750 KHz – 3GHz acoustic waves to basically allow a fast
 40

flowing stream of liquid to get very close to the surface (small acoustic boundary),

pushing sub-micron particles away [14,15]. While we are on the topic of removing

particles, I'll talk about the practical aspects of this. There were several sources of dust

particles in the clean room fume hood:

1. clean room cloths: these should be lint/dust free but sometimes they
have a lot of dust in them so minimize contact of the wafer with these
cloths.

2. inside the fume hood: be sure not to cover the set of holes in the hood
table that are closest to the edge. These holes are denser than the evenly
spaced holes deeper inside the hood table. The denser holes allow a
quicker air flow at the entrance, trapping any particles that try to get in.

3. Be sure the nitrogen gun has a good air filter (< 0.2 µm preferable) and
do not blow the wafers dry near the clean room cloths.

4. The D.I. water seems to be a major source of particles if not filtered

properly. There should be a 0.2 micron filter on the line and I typically
let the water run for at least 30 minutes to 1 hour before using it. At
other times, it should be left dripping to minimize bacteria growth and
keep dust out of the line.

To start off cleaning the wafers, I spin clean the wafers using acetone, isopropanol

(IPA) and filtered DI water. Use the Q-tips that have the softer foam tips. Check for

particles using a bright, white flashlight to scan the surface at various angles. If there's

a sizable particle there, you should be able to see it. It can then be removed by blowing

it off or by further spin cleaning, first with DI water. Apparently, blow drying the

surface with nitrogen can charge up the surface. In the early stages of this research, we

were concerned that this might be a problem and purchased a nitrogen gun with a

neutralizing (ionizing) tip. However, if this is the case, it does not seem to make any

difference that I could see. After spin cleaning, do the RCA cleans before proceeding.
 41

The following observations were noted and could be of further use to the reader : the

wafer bonding should be performed a short time (within a few hours) after doing the

chemical (RCA) clean. The state (reactivity or hydrophilicity) of the chemical oxide

formed changes over a period of several hours. The purpose of growing the chemical

oxide is to have a consistent surface to work with on each bonding run. Since RCA-2

does not have the same particle removal capability as RCA-1, using RCA-2 may

introduce more particles on the surface, therefore RCA-2 was not used just before

bonding. The HF dip for oxide removal may also introduce particles (only a problem

if you use RCA-2 due to the order of chemicals used) since particles that fall onto the

surface of the HF will stick to the wafer surface as it is pulled out of the solution. One

way around this was to put some IPA in the HF. It forms a layer on top of the HF and

due to its slightly higher viscosity, it sheets off the wafer as it is pulled out of the HF,

bringing along particles [16].

2.2 The effect of plasma activation of the surface

As mentioned briefly, the cleaned wafers are pressed into contact and they

bond together but this is just a weak Van der Waals bond [1]. The wafers can easily be

pried apart and re-bonded without detrimental effects (as far as I could tell. No

measurements were done on this though). To get strongly bonded wafers, the pair

must be annealed at high temperatures (>800 ºC). This causes the oxide to undergo

viscous flow and creates the strong siloxane bonds between the wafers [1]. After this,

the wafers cannot be pried apart without breaking one or both of the wafers.
 42

Annealing to such high temperatures is the simplest method of obtaining very strong

bond strengths, however, if there are pre-existing features with fine physical/chemical

structures and specific diffusion profiles on the wafer(s), these will be broadened or

possibly destroyed. Since plasma processes are often used to simulate the effect of

high temperature reactions (e.g. PECVD) it was soon discovered that by using various

plasmas, the high bond strength could be attained at relatively low anneal temperatures

of 200-400 ºC [17]. One factor, pointed out by B. Roberds [3], provided by the plasma

activation was the removal of water from the surface before contacting the wafers.

This fits into the general chemical picture since water would be more difficult to

absorb into any material (compared to a gas) and would only impede the intimate

contacting of the two opposing surfaces. However, there is a delicate tradeoff,

hydrophilic surfaces are desired (lots of silanol groups) to create wafer to wafer

siloxane bonds but the copious amounts of water they attract to the outer surface is

undesirable. The plasma activation can create more favorable conditions for bonding

by the application of ion bombardment and UV emission. This process, however, is

rather complicated and not very well understood. With the numerous parameters

involved in the materials, cleaning and plasma activation processing, results from the

literature were sometimes consistent and sometimes contradictory and often not

directly comparable [18-22].

The plasmas used for bonding in this thesis are oxygen, argon and nitrogen.

Argon plasmas were only used at VTT Electronics in Finland (our collaborators).

There was also some interest in using ultraviolet light as the surface activator but the
 43

results were difficult to reproduce, partly due to particles and cleanliness. A discussion

of the effect of these plasmas and UV surface activations is given in a later section.

2.2.1 Bonding procedure [23]

1. Spin clean with acetone, 2-propanol, D.I. water and RCA clean leaving
the final chemical oxide on the surface.

2. Put wafers face up in a parallel plate type plasma reactor (RIE or

similar etcher, I used a Technics PE-IIa or IIb parallel plate etcher.
Collaborators at VTT electronics in Finland used an RIE). Trying the
surface activation in a barrel etcher has mixed results depending on the
manufacturer of the etcher. (The Technics barrel etcher does not seem
to have any effect on the bond strength, whereas the Tegal Plasma-line
etcher does.)

3. Plasma etch the wafers using either oxygen, nitrogen, or argon plasma
at power of 100-150 W (11” diameter plate ( 0.16 – 0.25 W/cm2 ),
pressure 10-300 mTorr, and short time (30 secs).

4a. if using oxygen plasma in step 3: dip in RCA-1 (75 ºC) for 45 secs, the
running DI water for 2 minutes, dry and bond.

4b. if using nitrogen or argon plasma in step 3: rinse in running DI water

for 5 minutes, dry and bond.

5. At UCSD, bonding took place by hand (using PVC, powder free gloves
and squeezing the wafers together), in air at room temperature. At VTT
electronics, they used a wafer bonding machine (Electronic Visions
EV801 manual wafer bonding station) in a class 100 clean room,
which could do bonding in air or vacuum at various temperatures.

6. anneal the samples on a hot plate at 100 ºC for a minimum duration of

30 minutes.

Differences between the bonding procedure used at UCSD and VTT Electronics

(Finland) were the plasma etcher (VTT used an RIE, where UCSD used a parallel

plate plasma etcher which has less control over the plasma conditions), the bonding

conditions (VTT used a machine made for the purpose of wafer bonding and included
 44

a megasonic D.I. water clean before contacting the wafers), and the annealing

conditions (VTT annealed bonded wafer pairs for 2 hours, UCSD annealed the bonded

pairs for 30 minutes).

2.2.2 Discussion of bonding procedure

The wafers were taken out of the container box, examined under a Nomarski

phase interference optical microsope for smoothness, and the smoothest wafers were

chosen for the bonding process. Wafer WorldTM 2”, p-type (boron doped) ~1×1015 cm-
3
prime grade wafers were used. The batch of 25 wafers per box had roughly 1/3 to ½

of the wafers which did not have large features as observed under the Nomarski

microscope. Out collaborators at VTT electronics used OkmeticTM 4” prime grade Si

p-type wafers and these were featureless under the Nomarksi microscope and ideal for

bonding. To start the bonding process, the wafers were spin cleaned in acetone, IPA

and DI water using soft, foam tipped q-tip swabs and then spin dried. These were then

dipped in a dilute HF solutions (0.5-2% in water) to remove the native oxide and

cleaned in RCA-1 and RCA-2 to grow a hydrophilic, chemical SiO2 layer. If the

wafers were to be oxidized, they were then put into a wet oxidation furnace for 1 hour

at 1000 °C, resulting in a 3300 Å oxide layer. The oxidized wafers are then cleaned

with RCA-1 again (no RCA-2 or HF dip this time) and rinsed in DI water to make the

surface hydrophilic again. The thermally grown oxide tends to “close” the surface

bonds forming more siloxane bonds rather than silanol bonds. This is seen as a slightly

hydrophobic surface even though there is an oxide there.

 45

The wafers are placed into the plasma chamber and the surfaces activated.

With oxygen plasma, a post plasma RCA-1 dip (45 secs, 75 °C) and a 2 min DI water

rinse is necessary to obtain strong bond strengths (> 2000 mJ/m2) [23,24]. With

nitrogen or argon plasmas, the RCA-1 dip may slightly increase the bond strength if at

all [23,25]. These observations were from T. Suni’s thesis [23] and suggest that the

plasma surface activation is due, at least partly to physical ion bombardment since the

nitrogen and argon plasmas give similar results and are not chemically reactive

plasmas. Oxygen plasmas are known for their oxidative properties and along with the

additional RCA-1 post plasma dip, suggests that oxygen plasma has a chemical

component associated with the surface activation. It is likely that the RCA-1

treatment, which acts as a mild oxide etchant, offsets the effect of the chemical

oxidation. It may be questioned what the oxygen plasma could oxidize on the thermal

oxide? It is known that the thermal oxide, being amorphous has surface charges that

can arise from local excesses of Si. It is this excess Si which can react with the oxygen

ions in the plasma.

At this point, the wafers are either placed into the bonding apparatus where a

megasonic clean may be done or the wafers, if they are clean enough, can be pressed

together taking care not to trap any air bubbles between them. If the samples will be

diced into strips, the 100 ºC anneal will strengthen the bond enough such that the

sample will not debond under the vibrations of the dicing saw.
 46

2.2.3 Bond strength vs. RF plasma power.

The RF input power used for the surface plasma activation was 100 Watts.

Other input powers were used with the result that ~100-200 W gave roughly

equivalent bond strengths, 400 W (figure 2-5) and 50 W (not shown) gave lower bond

strengths. The reasons for this are not clear but this was done to show that different

input RF powers of the plasma etcher would not significantly change the final wafer to

wafer bond strengths.

Bond strength at various plasma powers

(30 sec nitrogen plasma)

2000
Bond strength (mJ/m )
2

1500

1000

100 W
500
200 W
400 W
0
0 100 200 300 400

Anneal temperature (C)

Figure 2-5: The effect of the RF input power on the bond strength. From 100-
200 W, the difference is small, but going up to 400W actually makes the bond
strength weaker! (bonded at UCSD)
 47

2.2.4 Explanation in terms of plasma physics

Just what is going on in the plasma chamber when the wafer surfaces are

subjected to these gases? Oxygen plasma is typically used for photoresist descum of

the surface; it works by the action of physical bombardment and oxidation of the

organic material. The CH groups in the organic are then converted to CO, CO2 and H2

and pumped away. Nitrogen plasma has been used for nitridation of the wafer surface

but typically at higher implant energies. Silicon oxynitrides can form with longer

exposure to nitrogen plasmas but for short exposures (< ~30 s) this does not seem to

be the case [26,27]. Argon plasma is used mainly to physically bombard the surface

(e.g. sputtering). At the energies used, it may seem that there should be little if any

sputtering of the surface. However, it appears that even light bombardment from Ar

Figure 2-6 : Surface roughness measured by AFM as a function of plasma

process time. Circles and squares correspond to hydrogen (H series) and argon
(A series) treatments, respectively. Triangles correspond to hydrogen treatment
after argon treatment (AH series). [After I. Umezu et al [28] ]
 48

ions causes a smoothening effect (see figure 2-6) as well as creating defect sites which

make up the reactive surface [28-30]. Argon plasmas are also speculated to be able do

some surface densification at these low energies [31]. Observation of the color of the

plasmas shows that the spectral emissions are different though the UV spectrum for

oxygen and nitrogen plasmas are in the same input RF energy range [32]. The masses

of the ions, electrons and neutral particles are also different. Clearly, the wafer is

subjected to several things: UV emissions, ion/neutral particle physical bombardment,

possibly electron bombardment, and a large bias from the plasma reactor used to

power the plasma.

2.2.4.1 Plasma etching physics

The classical definition of a plasma is a partially ionized gas of electrons,

positive ions (same number as electrons) and neutral particles. It is electrically neutral,

and commonly has energy coupled into it (to maintain its ionization) either

capacitively or inductively. The plasma reactor used for bonding in this thesis used a

parallel plate capacitively coupled reactor with energy coupled in at a frequency of

13.56 MHz (due to FCC regulations). A gas is continually bled into a chamber (and

being pumped out) such that the pressure is low (typically ~10-800 mTorr), and a high

voltage is applied between the parallel plate electrodes to ionize the gas.

A plasma in the reactor is initiated by field emission from a sharp edge and

high electric fields. The electrons undergo a cascade of collisions ionizing other

atoms/molecules. The pressure in the chamber should typically be in the range of ~1-

1000 mTorr. If the pressure is much lower, there are too few atoms/molecules to
 49

participate in the cascaded collisions and the plasma cannot be sustained. With too

high a pressure, the high number of collisions, which are close together, do not allow

the electrons to gain enough kinetic energy to excite other atoms/molecules to sustain

the plasma. The ability to sustain the plasma, however, is a function of the input

power.

The input power provides a continuous source of excitation to sustain the

plasma, and this is seen in the characteristic glow which is the result of the electronic

transitions induced by the high energy electrons. The requisite power must also be

sufficiently high to offset the losses of electrons lost through collisions with the

chamber sidewalls and the plasma species. There are plasmas that are excited by a DC

source (more often and properly called a glow discharge) and AC sources which

oscillate at specific frequencies dictated by the FCC such that they don't interfere with

communications channels (if the plasma system is shielded well enough, however, it

can operate at other frequencies). AC plasmas have the advantage that non-conductive

substrates can be treated without being charged up, and that the electrode surface does

not have to be conducting (which could introduce metallic contamination because the

metal may get sputtered off by the impinging ions) [33].

If a non-conductive substrate is placed in the chamber with the plasma, a dark

space or sheath will form above it. This sheath originates from the difference in mass

of the components of the plasma. Because the plasma is composed of electrons and

various ions with significantly different masses, there tends to be a separation when

the oscillation frequency is sufficiently high. The electrons are light enough to fully
 50

respond to the frequencies used, but the more massive ions only see a time averaged

oscillation. The outcome of this difference in mass is that the electrons strike the

substrate more often than the ions with the result that the substrate tends to become

more negatively charged -- repelling the electrons. This sheath thickness will depend

on the energies of the impinging electrons and ions and will equilibrate to a certain

value. Because the electrons are no longer colliding with the ions in the sheath region,

there is no light emission. This sheath thickness ranges from microns to millimeters in

thickness. The important thing is that since the electrode is negatively charged, ions

can travel across the sheath and collide with the substrate surface. The ions are

accelerated across a potential difference given by the plasma potential Vp and the

floating potential (of the substrate). Vp actually oscillates in phase with the applied

potential Vo(t).

In a parallel plate plasma etcher, there are two electrodes - the powered

electrode and the grounded electrode with the electrodes facing each other and their

surfaces horizontal. The sample typically sits on the powered electrode (bottom). The

potential difference across the sheath (also referred to as self bias or DC bias) is a

function of the geometry of the reactor (plasma etching chamber). In the Technics PE-

IIa (later used model b) plasma etcher, the electrodes have the same size (same

diameter), whereas in most reactive ion etchers (RIEs), the powered electrode is

typically smaller than the grounded electrode [34]. This has the effect of increasing

the potential drop across the sheath which spans the plasma and the powered

electrode. This point is noted because of an observed difference in wafer to wafer

 51

bond strength after plasma activation between bonded pairs activated at VTT

Electronics (who use an RIE, with different sized electrodes) and at UCSD (who use a

plasma etcher (same sized electrodes)). This geometrical difference in electrode size

could explain the bond strength differences of the wafer pairs. If the energy of the

impinging ions is a significant factor in the “activation” process, this could be a

critical feature to examine.

2.2.4.2 UV light emission

The majority of plasma components are neutral molecules (unless you use a

electron cyclotron resonance (ECR) or an inductively coupled plasma (ICP) plasma

system), various species of ions including the atomic forms of the gas(es), electrons,

and UV light. To examine the role of UV light in the surface activation, isolation of

the UV from the effect of the ion bombardment is required. UV light is known to

modify the surface of silica by dehydroxylation of the surface.[35] Dehydroxylation is

the process of removing hydroxyl groups (-OH) and converting them to siloxane (Si-

O-Si) bonds. This has the effect of making the outer surface more orderly and

relatively hydrophobic. The more orderly surface and the lack of surface water would

aid the contacting with the maximum surface area. (A UV spectrum analyzer should

be used to measure the spectral output of the plasma(s) (oxygen, nitrogen, and argon),

however, this was not available in this study.) A method to isolate the UV component

experimentally would be to cover the silicon surface with a wide bandgap material

(say double polished sapphire) to protect the surface from ion bombardment but let
 52

UV light through to the surface. This method has the advantage of using the identical

UV spectrum, however, it is not clear if a plasma would be formed in any gaps

between the sapphire and the silicon; this was not attempted due to the unavailability

of clean double polished sapphire substrates that could be used for this purpose. A less

ideal alternative is to simulate the UV spectrum by assuming that it is close to that of a

low pressure mercury lamp. Using a low pressure mercury lamp, the main spectral

peak is at 254 nm (hν = 4.89 eV). A secondary peak at 185 nm (hν = 6.71 eV) is

typically used for generating ozone ( it actually dissociates O2, which causes the

atomic O to attach to surrounding O2's producing O3). 254 nm UV light dissociates the

ozone by breaking it up. To do this, RCA cleaned Si wafers (with only a chemical

oxide) were placed in a UV/ozone stripper chamber (SAMCO UV-1) with 1.) Ozone

and UV, and 2.) Nitrogen and UV. Approximately 10 minutes of warm up time is

required to stabilize the power level of the UV lamp (low pressure mercury arc lamp)

~8 mW/cm2. As can be seen in figure 2-7, the UV treatment (■ and ▲) does result in

an increase in the bond strength (~1000-1800 mJ/m2) compared to the case with no

treatment (~900-1200 mJ/m2) (♦). However, the experiments were painstakingly slow

due to the numerous occurrences of particles which stuck onto the surface of the test

wafers, often resulting in the bonding experiments being inconclusive and the tests

were not carried further. Figure 2-7 shows only a few of the more successful cases.

In hindsight, however, after going through the details in

 53

UV surface activated Si/Si samples

(main spectral peaks at 185 and 254 nm)

2400
Bond strength (mJ/m )

no surface activation
2

2100
1800 UV-Ozone
1500
UV-Nitrogen
1200
900
600
300
0
0 100 200 300 400
Anneal temperature (C)

Figure 2-7: Comparison of UV activated samples to samples (■,▲) with no

surface activation (♦). The ambient in the chamber was either ozone or (UHP)
nitrogen. The wafers were all RCA cleaned before bonding. At room temp (far
left), the bond strengths are similar. At higher anneal temperatures, the UV
activated samples seem to be slightly stronger. The measured bond strengths
match up with those given in the literature. [37]

this thesis and getting some experience bonding wafers, this would be a direction of

research worthy of deeper investigation complementing the examination of the effects

of plasma activation. There have been many studies that have used UV to enhance the

oxidation rates of silicon [38-42,66,67], especially at lower oxidation temperatures (<

600 ºC) which seems to be one of the components of plasma activation [43]. The

mechanisms of enhancement include carrier generation and bond breaking at the

Si/SiO2 interface and can lead up an increase in oxidation rate by up to 60%.[67]

 54

2.2.4.3 Particle bombardment

D. Pasquariello et al., studied the surface energy (bond strength) of the wafer

as a function of the self bias (see §2.2.4.1 for definition) in oxygen plasma [44]. They

found that oxygen plasma has a smoothing effect on the surface independent of the

self bias voltage. Because the self bias would affect how the ions would strike the

surface, this indicates that oxygen plasma may have a chemical as well as a physical

effect on the surface energy [45]. This is not unexpected since oxygen plasma is

commonly used to decompose organic compounds (plasma ashing) by oxidation.

Collaboration with VTT Electronics (Finland) brought observations that argon

and nitrogen plasmas behaved similarly in terms of giving about the same bond

strengths but without any post-plasma chemical treatment. This fact suggests that the

main component of surface activation may actually be the ion bombardment at the

surface since Ar is inert and N2 is likely to be inert at these relatively low powers and

exposure times. [26] Physical bombardment of the surface by particles (some

charged, but mostly neutral) can have either smoothening or roughening, and/or

densifying effects depending on the plasma conditions and exposure time of the

surface to the plasma. [31]

2.2.4.4 Plasma effects on silicon oxidation

One factor worth mentioning is the effect an electric field has on the oxidation

of silicon. Since it is assumed that the bond strengthening is based on an oxidation at

the wafer bonded interface, anything that could affect this is worth a careful

examination. Just to review the big picture, the idea is that the substantial increase in
 55

bond strength is due to a significant increase in the effective contact area between the

wafer surfaces. This increase in contact area is made through the surfaces getting

closer to each other such that the silanols can bridge the gap and react to form siloxane

bonds.

The problem with the oxidation induced bond strengthening is that it

apparently has to take place at very low temperatures (~200-400 °C since that is what

we observe). Thermal oxidation is usually done around temperatures of 1000 ºC. Due

to the exponential dependence on temperature, trying to oxidize a silicon surface at

temperatures of 200-400 ºC seems hopelessly slow, if it is possible at all.

Extrapolating the oxide thickness from the Deal-Grove model gives thicknesses in the

range of fractions of Angstroms after 1 hour in wet oxygen at 300 °C [45]. In

comparison, roughly 3500 Å of wet oxide is grown after 1 hour at 1000 °C. However,

there are several points that make low temperature oxidation rather plausible: many

reports showing increased oxidation rates in very thin oxides (< 100 Å) [46-54], UV

and electric field enhanced oxidation (both of which are present when plasma surface

activation is done), and extension of the linear growth regime which is responsible for

the initial oxide formation. The initial regime of oxidation (the formation of the first

10-20 Å or so of oxide) is not well understood. The numerous reports of oxidation

rates in this regime which are faster than those expected from the “standard” rates

used to calculate thicker films [55-59] are also done at higher temperatures (> 600 °C),

making it difficult to say with confidence there is also an increased rate at lower

temperatures. Typically, the reports are that dry oxygen has a higher rate compared to
 56

oxidation by water (it’s not always clear if this means wet oxidation, with steam and

oxygen, or steam and nitrogen, which would isolate oxidation to just the reaction of

silicon with water). Oxidation with water tends to follow the typical linear-parabolic

model [60], where the linear kinetics indicates surface controlled reactions and

parabolic kinetics indicates diffusion controlled reactions. Due to this difference and

data from dielectric breakdown of wet and dry oxide [60], it is shown that the results

can be explained if micropores exist in the oxide film [60]. UV and electric field

enhanced oxidation of silicon have also been reported [61-70]. These enhancements

are based on the principle of creating new oxidation states (breaking Si-Si or Si-O

bonds) at the Si/SiO2 interface (UV) and/or driving the oxidants through the oxide at

an accelerated rate so that the oxidation is not dominated by diffusion rates through

the oxide (electric field). Of course, this approach assumes that the oxygen molecules

either decompose into atomic oxygen ions or becomes ionized in the SiO2 network.

These arguments are still controversial and still open for discussion. Another

approach, and the last one that will be discussed in this thesis is the method of

extending the linear regime of oxidation. Since the linear regime is faster than the

parabolic regime (which tapers off with time(oxide thickness) it could possibly give

insight into the mechanics of oxidation. The idea behind this is that diffusing oxygen

ions will charge up the Si/SiO2 interface, slowing down the barrage of impinging ions

behind them. By providing an electron current in the right direction to remove the

charge buildup, this charge is balanced and the oxidation becomes less diffusion

limited [68,69].
 57

While the reports of these enhancements to oxidation are all done at the time

of annealing, the conditions which provide these enhancements do not necessarily

have to be present during the annealing to reap the same benefits. The enhancement

mechanisms all have to do with either using charges/electric fields or providing more

states for easy oxidation (lowering the barrier for oxidation) which are all present in

the plasma reactor. The “growth” of the oxide can be approached from two ways: the

bottom (Si/SiO2 interface) and the top of the oxide which contain local excesses of Si.

There are reports of enhancing the growth of the oxide by using electric fields and

optical excitation (not necessarily together). These are based on the generation of

carriers (optically enhanced) or the movement of ions (using electric fields) to extend

the initial, linear (fast) growth regime. The plasma reactor contains these components,

the difference being that these “stimulants” are applied before annealing (in separate

steps). From the top surface of the oxide, ion bombardment may displace certain ions

creating Si with different oxidation states [71,72]. These may be receptive to forming

new bonds to ambient oxygen, effectively causing a small growth. These features,

coupled with the fact that the spacing between the bonded wafers is only around 10-30

Å (from RMS surface roughness of prime grade wafers) makes the possibility of

closing the atomic scale gaps quite feasible.

2.2.4.5 Effect of plasma on surface silica chemistry

To form covalent wafer to wafer bonds, siloxane bonds (Si-O-Si) have to form,

bridging the gaps between the wafer surfaces. To form siloxane bonds in this manner,
 58

a high density of silanol bonds should be present on each wafer surface. The chemical

bonding of two silanol bonds forms siloxane and water as a byproduct (see §2.1.1).

The wafer surfaces coming out of the RCA solutions have a very high density of

silanols [71,72], so high in fact that the silanols are very close together and chemically

couple into groups which form what are called associated silanols [74,75]. Associated

silanols are merely isolated silanols which are hydrogen bond coupled between the H

of one and the O of the other (figures 2-1 and 2-8). These associated silanols have

different chemical properties compared to isolated silanols. For a fully hydroxylated

surface (after RCA cleaning) the isolated silanols have an average density of ~1.4

groups/100 Å2 and the associated silanols have an average density of ~3.2 groups/100

Å2 [76,77] indicating that most of the silanols are coupled forming associated silanols.

The associated silanols also have a strong affinity for water, whereas the isolated

silanols tend to be more attracted to ammonia, nitrogen and diethylamine [78]. In a

crack or pore of the silica, associated silanols are prevalent (figure 2-8). This is

because the sloped walls of the pore bring any isolated silanols closer, thus increasing

the likelihood of hydrogen bonding between the H and O. What this means is that

there can be a relatively large amount of water stored under the surface of the oxide

due to the copious amounts of associated silanols holding on to them. The depth of

this hydroxylated layer is probably ~150 Å thick [79]. On the surface of the

hydroxylated wafers, having a high concentration of associated silanols, means that

siloxane bonds cannot form as easily with the result that a higher anneal temperature is

necessary to form covalent siloxane bonds across the interface. With plasma
 59

H H

O O H
Si Si H
O
O
O O O Si Si
SiO2 O O
Figure 2-8: surface of SiO2 with a crack/pore. The isolated silanols (left side) are
less likely to interact (and form an associated silanol on a flat surface. In the
pore, the slope forces the isolated silanols to get closer making it more likely to
form an associated silanol.

activation, however, it is speculated that the physical bombardment of the ions can

break up the associated silanols on the surface, leaving only isolated silanols. If the

wafer surfaces are then placed in contact with each other, these isolated silanols can

easily form strong siloxane bonds upon annealing, resulting in stronger bond strengths

at lower anneal temperatures. The density of these isolated and associated silanols can

be measured using multiple interference transmission FTIR (MIT-FTIR) (figure 2-9)

[80-85]. The reason why this setup has to be used and that conventional FTIR cannot

be used is that the vibrational signals from these groups are very weak since they lie

only in a plane at the interface. By using MIT-FTIR, the IR beam bounces many times

across the interface allowing sufficient absorption to take place to be detected. A dry

box is necessary for the measurement because the silanol groups are in the middle of

the water spectrum which would otherwise dominate the absorption spectra. The

purpose is to examine the interface of bonded wafer pairs and quantify the density of

isolated vs. associated silanols. An s/p polarizer can be used to flip the polarization to

get spectra which were sensitive and insensitive to the interfacial species – which are
 60

Figure 2-9: sample cross section for multiple interference transmission FTIR
measurement. The thick gray area is the wafer bonded interface and where the
molecular species of interest are. The edges are beveled to facilitate coupling of
IR beams at the appropriate angles such that they are confined within the
waveguide. [After Diego, Feijoo et al. (1994)]

then subtracted from one another to get a useable spectrum. This measurement was not

done in this research, however, it is hoped that this introduction will motivate this

characterization technique for the reader by simplifying the details involved.

2.3 Wafer bonding results

2.3.1 Si to Si bonding:

When “Si to Si” bonding is mentioned in this thesis, what it really means is

there is hydrophilic bonding of two silicon wafers. “Hydrophilic” implies that there is

a silicon dioxide layer on the surface, specifically a native oxide or a thin chemically

grown oxide (using RCA cleaning solutions) which is ~6-10 Å, but the value is not as

important as the characteristics of the oxide with respect to oxidation. The chemical

oxide was used for all bonded wafers done at UCSD. This oxide provides a fresh, and

consistent surface to start with.

 61

Cleanliness of the wafer surfaces and the surrounding lab environment is

always an issue. With the initial bonding experiments, I just tried to minimize the

number of large particles at the bonded interface. As each potential source of particles

was identified, the results were better looking and eventually, bonding could be done

with none or at most 1 particle if care was taken. The most useful steps taken to reduce

this particle count was spin cleaning (instead of using an ultrasonic clean), letting the

DI water run continuously to flush out particles, and using a bright flashlight to

examine the wafer surface for particles before bonding.

Upon annealing (30 minutes in air (on hot plate) at temperatures from 100 –

400 ºC spots would appear when the interface was viewed using transmission IR. The

number of spots was proportional to the anneal temperature. These were gas bubbles

which formed when the silicon reacted with water and a byproduct of hydrogen gas

was formed (see figure 2-10): Si +2H2O → SiO2 + 2H2. [1, p.126]

2.3.2 Si to Oxide bonding

A group from VTT Electronics (Finland) found that by bonding Si with either

a native oxide or chemical oxide to a thick wet thermal oxide (5000 Å), the bubbles

would not appear upon annealing. This was presumably due to the oxide being able to

absorb the gas from the interface, suggesting that the oxide may indeed have some

degree of porosity. To examine the bubble formation, a scanning acoustic microscope

(SAM) was used to compare Si/Si and Si/OX bonding. The results clearly show that
 62

for Si/Si bonding, the bubbles appear even though they are not visible on the IR

camera (IR image not shown).

Figure 2-10: Comparison of Si/Si bonding (left figure) to Si/OX bonding (figure
on right). The images were taken using a scanning acoustic microscope (SAM) at
VTT electronics in Finland. The small bubbles are not visible under an IR
transmission imaging (not shown). This shows the benefit of using Si/OX rather
than Si/Si bonding. (4 inch bonded Si wafers, SAM imaged by T. Suni at VTT
electronics, Finland)

2.3.3 Si to Glass bonding

For flat panel display applications, Si/Glass bonding is required because the

glass serves as the mechanical backplane as well as the window for light emission.

The glass is Corning 1737F, an alumino-silicate glass that was specifically created so

that it would thermally match the expansion of silicon for flat panel display

applications. The glass was used in the industry to make displays with amorphous or

poly silicon TFTs and suits our bonding purpose well. As was mentioned in chapter 1,

the goal of this research is to see if reasonably good transistors can be fabricated on a

thin layer of Si, on top of a glass substrate (the screen of the FPD). The silicon film
 63

will be bonded onto the glass substrate just like a typical silicon on insulator (SOI)

structure. The difference here is that the glass is not merely SiO2. Since the glass was

engineered to thermally expand in a particular way, its composition had to be altered.

These extra components can potentially cause problems if they were to migrate/diffuse

into the silicon film close to the junctions of the transistor. To address this potential

problem, a study was done using the 1737F glass by J.G. Couillard et al. [86]. It was

known that the glass acted as a gettering site for impurities such as sodium [87].

Devices which were fabricated on top of the 1737F glass had lower leakage currents

when compared to devices fabricated on top of SiO2 by a factor of 6-8 times! If the

concern is over elements such as aluminum, calcium, boron, and barium which are

present to varying degrees in the glass, doing a RCA clean will leach out these and

other metallic components in the first 6 nm of the glass [88]. Therefore, with the

proper precautions, impurity diffusion from the glass can be minimized.

2.4 Wafer to wafer bond strength measurement

The bond strength (or bond energy) is measured in units of milli-Joules per

square meter. It characterizes the quality of the wafer to wafer bond. For reference, a

weak bond (no annealing) has a bond strength of ~30-300 mJ/m2, whereas a strong

bond (annealed at 1000 ºC) would have a bond strength ~ >2700 mJ/m2. If it is

stronger, it can't be easily measured because the silicon wafers would break.
 64

The easiest way to measure the bond energy is by the razor blade test proposed

by Mazura [89] (see figure 2-11). A razor blade is inserted into the wafer interface and

an infrared camera (Black and white Sony CCD-IRIS used with halogen microscope

lamp bulb as IR source) is used in transmission mode (light passed through wafer into

camera) to measure the length of the crack that forms. A long crack is an indication of

a weak bond, and a short crack is an indication of a strong bond. Using elasticity

theory, a quantitative relation can be derived which gives the bond strength as

inversely proportional to the fourth power of the crack length for a pair of identical

wafers [90]:

3Et w3 t b2
γ =
32 L4
where γ is the bond strength or bond energy in joules per square meter, E is the

Young’s modulus of Si, tw is the thickness of the wafer (not the bonded pair), tb is the

thickness of the blade, and L is the measured crack length. For pairs of dissimilar

materials or thicknesses, more sophisticated relations are given in chapter 2 of Tong

and Gösele’s book. It is important to note the extreme sensitivity of the bond strength

to the value of the measured crack length, which goes as the fourth power.

Since the bond strength value is so sensitive to the crack length, measuring this

value accurately is very important. The best way to do this is to measure the crack

length as a number of pixels on screen and then correlate the number of pixels to an

accurately measured (preferably using a microscope) constant distance. Of course this

depends on the camera position and focus. Changing any one of these will require that
 65

the reference be recalibrated. Another factor which is even more important at high

bond strengths (short crack lengths) is the fact that the razor blade has an edge, which

contributes extra length (shortening the visible/measurable crack length) and makes

Figure 2-11: The razor blade measurement method. The blade is inserted
between the wafers which creates a separation seen with an IR camera (right
picture). The crack length is measured and varies inversely (to the fourth power)
with the bond strength. The thing to watch out for is the tapered tip of the blade.
It will effectively shorten the crack length making the bond strength seem
stronger than it really is, especially for strong bonds.

the bond strength seem larger than it actually is (figures 2-11 and 2-12).

For silicon wafers, IR light longer than 1.10 µm will pass through the material.

If the bubble is filled with air with refractive index of 1.0, the height of the bubble, H,

can be estimated by the number of fringes N: H = N·λ/2. The smallest bubble height

can be measured down to half a fringe. That means that there will only be significant

contrast in the transmitted image for crack widths greater than λ/4 = 0.275 µm [1, p.
 66

35]. What this means is that the crack length may extend up to approximately 1.5 µm

past what can be measured using the IR camera [1, p.42-3] (figure 2-12). Whether this

The effect of accounting for blade taper length

[500µm thick Si wafers, 100µm blade width, 0.36mm taper length]

3000
Bond strength (mJ/m 2)

2500
without correction
2000
with correction
1500

1000

500

0
9 11 13 15
Measured Crack length (mm)

Figure 2-12 : figure of bond strengths with and without blade taper in
calculation.

is the case or not can only be determined using a SAM with a very high frequency

scan which is not practical for every bonded sample. In either case, adding the length

of the tapered end of the blade (about 0.33-0.36 mm) can give a more accurate value

of the bond energy. What this means is that the bond strength measurement can give a

reasonable relative measure of the surface energy, however, due to bonding

parameters or calculation methods, the bond strengths between different research

groups doing these measurements may not be directly comparable.

 67

Another complication in the measurement of bond strength is that the crack

length changes (lengthens) quickly and then slows down with time (figure 2-13). The

settling point seems to change rather slowly after 2 minutes. After inserting the blade,

the crack length was measured after 2 minutes for each measurement. This slow

change in crack length might be due to water from the atmosphere attacking the crack

tip [91-94].

Normalized ∆L vs. time

1.00
Normalized ∆ L (%)

0.95

0.90

0.85

0.80
0 60 120 180 240 300

time since blade was pushed in (secs)

Figure 2-13: The crack length shown in figure 8, will increase as a function of
time. It slows down after about 2 minutes.

Optical transmission is probably the easiest method to see if the bonded pairs have any

sizable gaps/bubbles at the interface. Since silicon has an energy gap of 1.12 eV, light

with a wavelength longer than that is transmitted through. For air bubbles (therefore

assuming the refractive index of air is 1.000) with separations around 1.10 µm at the
 68

interface, interference fringes are observed. The separation distance can be estimated

by counting the number of fringes and using the relation: Height (H) = N.λ/2, where N

is the number of fringes, and λ is the shortest wavelength of light that can pass

through (1.10 micron). The lateral resolution is ~100 µm which depends on the

detector [95,96]. Another way that was available to our collaborators at VTT

Electronics in Espoo, Finland was the acoustic microscope. The acoustic microscope

used high frequency acoustic waves (depending on the application and equipment,

~700 KHz – 3 GHz is used) with water as the coupling medium. The lateral resolution

of the SAM is about 10 µm, which is much better than the IR imaging technique [97].

The wafers can have the bond strength measured using the whole wafer, or it

can be diced into strips (preferable). The bonded pairs were diced using a modified

saw in the basement of Mayer Hall (Physics Dept.) using DynatexTM blades (with 5

µm particle size). The two inch wafers first had to be annealed for 30 minutes at 100

ºC to increase the bond strength such that the vibrations from the dicing did not

separate the slices. The slices could then be annealed at different temperatures and

bond strength measured conveniently.

One thing that is worth mentioning: when the bonded pairs have a high bond

strength, measuring the bond strength by inserting the razor often shattered the wafers

before the crack length could be measured. This was determined to be due to one of

two things: the razor blade was too thick (100 ± 1 µm) and/or the wafers were too thin

(300 µm). To thin the razor blades down (Gillette #10), ferric chloride was used to

etch the stainless steel. However, it was soon discovered that the blades were not
 69

etched evenly and at best, the thickness of the blades slowly increased from front to

back. Using 500 µm thick wafers solved the problem of breaking the wafers during

measurement using the unetched blades. (wafers were prime grade, single side

polished, 2 inch, (100), n-type 1-20 Ω·cm, 500 µm). The dicing blades had to be

selected appropriately such that the total thickness of the bonded pair (now

approximately 1 mm) could be cut through.

2.5 Key experiments and results

Wafers which are RCA cleaned and activated, but not annealed have the same bond

strength (Table 2-1):

Table 2-1: Bond strengths of wafer pairs before annealing. The bond strengths
are the same regardless of whether plasma activation was done or not.

No surface activation 220 mJ/m2

Oxygen plasma activation (30 sec, 100W)
220 mJ/m2
+ DIW rinse (5 min)

Comparing bonded pairs which are surface activated and then annealed to ones that

were not surface activated and annealed in figure 2-14. For Si-Si bonding where both

wafers only have either a native or chemical oxide on the surface, there are bubbles

appearing on previously particle free interfaces (as seen by IR transmission though the

bonded wafer pair). These bubbles are presumably hydrogen gas which forms upon

annealing from the reaction [1, p. 126]:

 70

2500

Surface energy [mJ/m ]

2
2000 Both wafers activated
SiO 2 wafer activated
1500 Si wafer activated
No activation
1000

500

0
100 150 200 250 300 350 400

Annealing temperature [°C], 2h

Figure 2-14: This plot demonstrates several things. The plasma activation
makes a significant difference in the bond strength, Activating both wafers (Si
and OX) results in stronger bond strength than activating either alone. [After T.
Suni [99]]

Si + 2H2O Æ SiO2 + 2H2

Note that the bonded pairs which show the hydrogen gas bubbles evolving with

annealing are for non-thermally oxidized wafers. When a silicon wafer with a

chemical oxide is bonded to a wet thermally oxidized silicon wafer and annealed, no

bubbles appear! This is because the thick, thermal oxide probably absorbed the

evolved hydrogen gas (suggesting some degree of porosity) and due to its thickness,

has more surface area available to adsorb the hydrogen gas.

The fact that the barrel etcher (asher) doesn't seem to enhance the wafer to

wafer bond strength and that the parallel plate etcher does do something, suggests that
 71

ion bombardment is involved in the surface activation. This activation can be by

modification of the surface topography (either physically or chemically as in the case

for oxygen plasma) or a very shallow effective implant as an enhancement for

adsorption. Of course, this is not certain because one barrel etcher (TechnicsTM)

seemed to make no difference and another (Tegal PlasmalineTM) seemed to have some

improvement in the bond strength.

The bond strength increase has been speculated to be due mainly to an increase

in effective contact area enhanced by localized oxidation which could close up the

gaps. An experiment to show this was carried out (figure 2-15). The oxide thickness of

the thermally oxidized silicon wafer was the constant. The thickness was kept at 5000

Å. This wafer was bonded to a series of different wafers with different thicknesses of

wet thermal oxide ranging from 0-5000 Å. It was expected that, if there was diffusion

of something across the wafer interface and this was responsible for the bond strength

increase, the 0 Å oxide thickness would have the strongest bond strength because there

was no barrier for the diffusion. We should also see that as the oxide thickness

increased, the bond strength should monotonically decrease. This is exactly what was

seen in the experiment. There are a few points to note: The biggest jump in bond

strength was for the 200 °C anneal (2 hrs in air) for the 5000 Å / 0 Å bonded pair

whereas the other pairs marginally increased. The next step in the oxide thickness was

300 Å (which also didn’t change much) which suggests that sufficient oxidant cannot

diffuse 300 Å in 2 hrs at 200 °C to substantially increase the bond strength.

 72

Effect of "native" oxide thickness on

bond strength
(OX has 5000 Å oxide, oxygen plasma bonded)
3000

2500
Bond strength

0Å
(mJ/m 2)

2000 300 Å
1000 Å
1500 5000 Å

1000

500
0 100 200 300 400 500

Anneal Temperature (°C)

Figure 2-15: Plot of bond strength with varying “native oxide” thicknesses. This
was to show that something diffused across the oxide, and the increase in bond
strength was proportional to the amount of diffusant. The thinner the oxide the
larger the expected bond strength, which is what is seen. The values are spaced
close enough that plotting on a log scale does not spread out the data points
much, if any. (measured at VTT electronics, Finland)

Note that the peak bond strength can be attained after annealing at 200 ºC. The

calculated diffusion of water seems to peak at around this temperature (compare with

oxygen).

As has been seen, the exposure to the plasma makes a big difference. Doing

the plasma activation for 6 minutes results in a weak bond strength (though stronger

than with no activation). Doing the activation for ~30 s results in a strong bond

strength! Apparently, for reasons not particularly well understood, the first 15 s or so

of the plasma impart a “kick” to the sample being “activated” [26]. The plasma
 73

species also make a difference. Argon and nitrogen plasmas behave similarly, but

oxygen plasma requires a RCA-1 dip (45 secs) followed by a 2 min. water rinse to get

the same bond strength as Ar and N activation [27].

amount oxidant diffused through 20 Å SiO 2 (30 min

anneal) and bond strength profile as a function of
anneal temp
100% 1

strength for measured data

75% 0.75

normalized bond
percent oxidant
diffused

50% 0.5

water (erfc)
25% oxygen (erfc) 0.25
water (gaussian)
measured data
0% 0
0 100 200 300 400
anneal temperature (°C)

Figure 2-16: Plot of amount of water diffused across the thin oxide as a function
of temperature. This shows that at 200 °C, a lot of water has diffused across the
wafer bonded interface and through the native oxide. Comparing this with the
bond strength profile (vs. temperature), it matches up nicely. Note that the
oxygen diffusion profile is also shown for reference. The water diffusion profiles
were calculated assuming a finite source (Gaussian) and an infinite source (erfc).
Values used: for water: D0 = 1×10-6 cm2/s, EA = 0.79 eV; for oxygen: D0 = 2.7×10-
4
cm2/s, EA = 1.16 eV after Tsai (1983) [After Tsai, J.C.C., “Diffusion,” in VLSI
Technology, ed. S.M. Sze, McGraw-Hill, New York, 1983, Chapter 5.]

The idea might be that the oxygen plasma actually "closes up" some of the

surface pores by creating new SiO2 from non-stoichiometric and dangling Si bonds in
 74

the oxide. Since RCA-1 (actually the ammonium hydroxide in the RCA-1) slowly

etches SiO2 [100], it could unblock the entrance to the pits in the oxide and allow the

oxygen or water (the oxidant) out with a smaller barrier. This idea of the surfaces

closing up for maximal surface area contact is apparently not new. This idea, as far as

I know, was first proposed by Weldon, et al. [101], but was only discussed for the case

of high temperature annealing of non-plasma activated pairs. What is different in this

thesis is the proposal of the mechanics of the wafer to wafer bond strengthening

mechanism(s) with the addition of surface plasma activation and the possible effects

of the activation to allow these events to push forward.

2.6 Summary on the mechanics of Si/OX plasma activated

hydrophilic wafer bonding

Based on the data shown above from various sources and references, it is

plausible that the mechanics are as follows: The thick, wet thermal oxide (OX) is

somewhat porous and has many sub-Angstrom to several-Angstrom sized holes. The

surface being the first initial stage of silicon to get oxidized, it happens very fast with

the result that it can be non-stoichiometric. This leaves extra Si atoms and dangling

bonds on the surface which makes it hydrophilic also. This surface being not so flat on

the atomic scale has a high density of silanol groups which tend to clump and form

associated silanols. Associated silanols also tend to attract and hold water molecules.

If we bonded the wafers now (without plasma activation) the associated silanols would

react and form siloxanes but there would be the intrinsic surface roughness as well as
 75

an excessive amount of by-product water at the interface which would reduce the

contact area. By using plasma activation, excess water is driven off and the associated

silanols are broken up and turned into isolated silanols. However, the plasma might

not penetrate deeper into the SiO2 where the associated silanols may still lurk (in

crevices) holding onto water (see §2.2.4.5). When the wafers are then bonded together,

the isolated silanols can then form siloxane but without the excessive water being

formed as a by-product. The byproduct water and the water under the surface are

thermally released and diffuse through the thin chemical oxide to the silicon where

they oxidize the silicon locally (this explains why the 2 thick OX do not result in large

bond strength in figure 2-15). Where the gaps between the wafers are largest lie the

thinnest oxides and largest reservoirs for water and oxygen. The local oxidation, due

to the volume increase of the oxide, closes the gap between the wafers all over the

place allowing more siloxane bonds to form increasing the bond strength of the wafer

pair. There is evidence to support the occurrence of low temperature oxidation (200-

400 ºC). The well known Deal-Grove model is really only valid for long oxidation

times when the oxide is much thicker. This, along with numerous reports of enhanced

oxidation as a result of external factors (electric fields, UV light) which are present in

the plasma reactor, make the possibility within reach. The required oxide thickness for

this process is ~5-20 Å (based on the RMS roughness of the wafers) which is an

entirely reasonable range of oxide growth for the start of the oxidation process.
 76

2.7 Summary for wafer bonding chapter

The mechanics of why the bond strength is significantly increased after

annealing has been approached by several groups [102-104]. It started with an

explanation by Stengl et al., who proposed that van der Waals attraction is able to hold

the activated surfaces together forming a cyclic tetramer between the two surfaces,

followed by a dehydration reaction where siloxane bonds are then formed. Bengtsson

gave a thorough review on all things dealing with wafer bonding but dealing only with

high temperature kinetics. Farrens et al., extended Stengl’s work, adding the effect of

plasma induced charges which increases the atom mobility near the surface (described

by Cabrera-Mott oxidation kinetics) for low temperature oxidation. These groups

presented clear big picture models with the relevant ideas (e.g. low temperature

oxidation, water layers, etc.) but they always seemed to lack a simple, mechanistic

picture of what was going on. The insight to mechanism for the plasma activated bond

strengthening was what I was after in this chapter. A quantitative model was not

established, but perhaps some new insight could be obtained from the ideas presented

in this chapter.

The bonding process was presented along with what was deemed important

practical steps in the recipes. Two components of the plasma were discussed: UV light

emission and ion bombardment and their possible effects on the silica surface. What

may be more important for good insight would be the differences between nitrogen

and argon plasmas versus oxygen plasmas. The oxygen plasmas seem to have a

chemical effect in addition to the physical bombardment that the other plasmas have.
 77

This chemical effect is speculated to “seal up” the surface through the creation of a

better oxide at the top of the silica layer(s). This surface oxide would then have to be

etched away (with RCA-1, which provides a slow etch) to free up the micropores

inherent in the oxide. These micropores are the reservoirs where the subsurface water

is stored – trapped by the associated silanols. The effects of Si-Si vs Si-OX bonding is

presented. The thick thermal oxide is necessary to prevent gas bubbles from being

trapped. The oxide acts as a gas sponge soaking up excess gas. Bond strength

measurement and potential pitfalls were discussed using the blade insertion method.

Evidence from the literature [75, chapter 6] shows that porosity in the oxide has been

suspected for decades, however, because these pores are small, there have been no

direct pictures of these to prove their existence.

What these ideas are trying to show is that there seems to be a relatively

complex interplay between the surface chemistry involving isolated and associated

silanols, at and below the surface, and the physical bombardment from the plasma.

This sets up a condition which makes water (or possibly some other oxidant) available

at the appropriate time to proceed with low temperature, localized oxidation. This

ultimately brings the surfaces close enough so that siloxane bonds can be bridged.

With some understanding of the processes involved in joining two otherwise,

normally un-joinable surfaces, we can proceed to add another step to the recipe which

will allow delamination of a single crystal film on an amorphous substrate – ion

implantation.
 78

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Chapter 3: SOI film preparation and characterization

3.1 Overview
Semiconductor on insulator (SOI) structures can be fabricated using several

techniques including including “bond and etch back” SOI (BESOI), silicon by

implantation of oxygen (SIMOX), and ion-cutting, also known as Smart-CutTM. With

the BESOI technique, two substrates (of which at least one has an oxide layer) are

bonded together and annealed to obtain a strong bond. One of the wafers is then

lapped and chemical and mechanically polished (CMP) to produce the SOI layer.

SIMOX wafers are created by ion implanting a high dose of oxygen below the surface

and annealing the implanted wafer to recrystallize the surface. Ion-cut SOI wafers are

fabricated by bonding a wafer with an oxide layer to another wafer which has been ion

implanted with a light ion (e.g. H, He). The plasma activated bonded pair is then

annealed causing the bond interface to strengthen while the implanted interface is

weakened. The result is that a thin film can be delaminated at the implanted interface

from the rest of the substrate, forming an SOI layer.

Ion cutting is arguably the most versatile and efficient technique for fabricating

SOI structures, compared to the other two techniques mentioned above. Ion cutting

allows the potential reuse of the substrate that the film originated from, unlike the

BESOI technique, nor is the film restricted to being the same material as the substrate

as in SIMOX method. However, compared to the SIMOX technique, the ion-cut films

(as do the BESOI films) do possess an inherent complication: ion-cut films are not

oriented in the same direction as the substrate (if they are both crystalline) due to

88
 89

slight offcuts of the two wafers. For layer characterization methods such as x-ray

diffraction, this orientation difference has to be accounted for.

The ion-cut films are typically implanted with a dose of ~1016 cm-2 with an

energy of 30-50 keV/atom (so for H2+, it would be twice that). The energy of the

implant is proportional to the depth of the ion distribution and, more importantly, the

damage distribution caused by the impinging particles.[1] SRIM/TRIM simulations

can be used to simulate the penetration depth of the ion species (e.g. H+, H2+, H3+,

etc.) into the Si wafer. This film exfoliation was done for two different kinds of

implantations : single ion implantation and plasma immersion ion implantation - and

on two different types of substrate : Corning 1737F glass and wet thermal silicon

dioxide. The electrical properties of these films are compared and discussed based on

their Hall effect and hot probe measurements, which is the focus of this chapter. The

following chapter will divert attention to the use of these films for the fabrication of

MOSFETs and the characterization of the MOSFETs.

Figure 3-1 shows the SRIM/TRIM simulated ion concentrations (left column)

and damage distribution (right column) for several implantation energies. These

distributions were created using a 20,000 ion Monte-Carlo calculation. The ion peaks

as a function of energy are shown under the heading “Ion range” which is the

projected ion range (net distance from the surface).

Implantation of hydrogen into silicon and annealing at temperatures at or

above 300 °C allows the hydrogen to be both more mobile and more reactive. The

effect of this is increased pressure in the subsurface cavities, which is the damage
 90

10 kV

20 kV

30 kV

50 kV

(a) (b)
Figure 3-1: SRIM/TRIM simulations (20,000 ions) of implanted H ion
concentrations and implantation induced vacancies in Si. Column (a) is the
implanted ion concentration profile of atomic hydrogen into silicon for various
implantation energies 10, 20 30 and 50 kV. Column (b) shows the damage
distributions for the respective implantation energies. The given “ion range” is
the projected range (depth of the implanted ion), the straggle (standard
deviation), skewness and kurtosis are the second, third and fourth moments of
the ion distribution. [2,3]
 91

Figure 3-2: (a) Optical micrograph of 1×1017 H+/cm2 after annealing to 475 °C
(Mag. 90×). (b) AFM image of a 15 µm×15 µm region of the same sample as in
(a). [4][After M. K. Weldon, et al., J. Vac. Sci. Technol. B 15(4), 1997]
 92

region caused by the impinging ions. Since the layer of silicon “above” the cavities is

thinner (than the rest of the substrate), it is easier for the expanding gas to push in that

direction. The result is the bubbles and blisters shown in figure 3-2. The effect of

bonding a capping wafer (also called a stiffener) on top of the implanted wafer is that

the capping wafer provides a “restoring” force to the surface of the implanted wafer. If

the surface is not bonded to a stiffener and the donor wafer is annealed to about 400 ºC

for 10-15 minutes, surface blistering occurs due to the expansion of hydrogen gas (see

figure 3-2). It can be seen that there are numerous small bubbles and a large number of

“popped” blisters (darker areas). In figure 3-2b, an atomic force microscope (AFM)

image provides a close-up of a 15 ×15 µm2 region. With the bonded wafer on top, the

gas cannot easily expand normal to the surface and instead expands laterally. This

propagates a ion damage induced crack parallel to the surface which is able to

delaminate a film of silicon. The general process is illustrated in figure 3-3 below.

The exfoliated film can also be delaminated using alternative methods. This

apparently modifies the electrical and structural properties of the film. The method

using only heat to self-delaminate the film, is termed thermal exfoliation (TE),

otherwise known as "hot cut", because the film is self-delaminated or cut at room

temperature after an anneal of ~400-450 ºC or so. The alternate method is termed

mechanical exfoliation (ME) or "cold cut". This involves annealing the bonded pair

for ~2 hours at temperatures up to 250-350 ºC to strengthen the wafer to wafer bond

(also done in TE sample), cooled to room temperature, and then using a razor blade

inserted into the gap between the bonded wafers to mechanically delaminate the
 93

Step 1: H+ implantation Step 3: Bonding

H+
SiO2

Implanted
p-Si layer

Step 2: Cleaning and Step 4: Annealing and

activation exfoliation

Stiffener (Si)

SiO2
SiO2
Bond surfaces Exfoliated Layer
n-region

p-Si n-region

p-Si
Figure 3-3: The Smart-CutTM process. Step 1: Hydrogen ions are implanted into
the surface of the (donor) silicon substrate (typically, prime grade silicon) at
energies of ~30-150 kV at a dose of ~1016 cm-2. They roughly end up at ~1000Å
per 10 kV per proton, which is where the damage region lies. Step2: The stiffener
(usually glass or oxidized silicon with a wet thermal oxide of 2000-5000Å) and the
implanted wafer are then cleaned and then have the surfaces activated with
plasma (oxygen, nitrogen or argon) for ~30 s at ~100W plus any appropriate post
plasma treatment. Step 3: The wafers are contacted and Step 4: they are
annealed in air first at 100 °C (to strengthen wafer-to-wafer bond strength to
prepare for dicing) then at temperatures of 200-400 °C to exfoliate the film.
 94

film. Because the impinging implanted atoms have left a particular damage profile, the

film/substrate interface is weakened. This allows the film to be separated from the

original substrate due to the fact that the wafer to wafer bond interface is stronger than

the substrate to film implantation interface. This is why it is critical to have a very

strong wafer-to-wafer bond at low temperatures.

In this chapter, the electrical properties of these films were measured using

Hall effect (Van der Pauw type measurements), and hot probe as a function of depth

into the film. Tetra-methyl Ammonium hydroxide (TMAH) was used to etch silicon in

between the electrical measurements. The samples measured included thermally

exfoliated Si on glass (Corning 1737F, an alumino-silicate glass) and thermally and

mechanically exfoliated silicon on wet thermal oxide (~3000-5000 Å thick) using

single ion and plasma immersion ion implantation (PIII, pronounced as "P-3"). These

measurements were done after exfoliation, and after annealing the films at

temperatures between 550 ºC and 1050 ºC. In addition, the strain in the films were

characterized using x-ray diffraction for the as-exfoliated films and also after

annealing at 1000 °C which is the maximum temperature reached in the fabrication of

the MOSFETs without all the intermediate temperature cycling (discussed in chapter

4). The effect of thermal and other shallow donors and their origins are discussed as

well as the effect of annealing in air, nitrogen and argon.

 95

3.2 Ion implantation

Ion implantation is a process commonly used for doping semiconductors with

tightly controlled doses in precisely designated areas. The implanted distributions are

typically laterally abrupt with a Gaussian[5] distribution along the direction of the

implant which makes it particularly useful in doping for self-aligned processes in

MOSFETs.

There were two types of ion implanters used for creating the exfoliated films used in

this study:

1. conventional (single) ion implantation which uses a mass separation

filter so that only one ion species is allowed to pass through into the
sample; the particle beam is scanned across the sample surface in
order to evenly cover the area, and

2. plasma immersion ion implantation (PIII, pronounced “P–three”).

With PIII, a plasma containing multiple ionic species is generated
and the ions are accelerated over a short distance and implanted into
the sample. Because the whole wafer is implanted at once (dose is
independent of wafer size), the implantation is inherently more
efficient. However, this comes at the cost of having to
indiscriminately implant several types of ions due to the difficulty in
separating them out of the plasma. This results in multiple
implantation depths (due to mass differences of the different
species) which can affect the surface quality of the exfoliated film.
Another draw back with this PIII method was that it did not yet have
ultra high vacuum capability (due to technological difficulties) and
so other contaminants which may have been in the chamber are also
implanted. The bias voltage (acceleration voltage) is limited by the
fact that at higher energies, the collisions of the ions with the
substrate create larger amounts of x-rays, require larger currents and
cause faster heating of the substrate. [6]
 96

3.2.1. Single ion implantation

Silicon samples which were hydrogen implanted, were obtained from Hong

Kong University of Science and Technology and VTT Electronics in Espoo, Finland.

The implantation energies were 100 KeV for H2+ implantation (VTT electronics), 50

KeV for H+ implantation, and the implantation dose was 5×1016 cm-2 making them

comparable. These implants were done at room temperature.

Another set of samples was obtained from Los Alamos National Laboratory

which had been H+ implanted at 40 KeV with a dose of 6×1016 cm-2 . This particular

set was, however, implanted at -135 ºC instead of the "usual" room temperature used.

This was done for two reasons: (1.) the surface became noticeably smoother which is

probably better for strong wafer to wafer bonding, and (2.) the ion damage induced

defects will migrate a shorter distance [7].

Hall effect (room temperature), hot probe and four point probe measurements

were performed on these two sets of samples. An interesting result was that the

samples implanted at low temperature (-135 ºC) became highly resistive compared to

the samples implanted at room temperature, even after annealing at temperatures in the

range of 650-1000 ºC in nitrogen, and the resulting exfoliated film was slightly

thinner. Possible reasons and similar observations will be discussed later in this

chapter.
 97

3.2.2. Plasma immersion ion implantation (PIII)

The use of PIII [8,9] as an alternate ion implantation source is worth a careful

examination for several reasons. Conventional implantation using a rastered ion beam

takes a significant amount of time and can increase the costs of implantation,

especially for larger wafers. [10] For a sophisticated circuit/device, several if not tens

of sequential implants may be required. For a fab to turn out a few hundred wafers an

hour, individual wafer processing time is critical. The main feature that makes PIII

very attractive is the fact that the implant dose is independent of the wafer size: large

area wafers take the same time to implant as small wafers.

Unlike the "conventional" method of using a single ion species for

implantation, the PIII method implanted several species at the same time. This is

because the implantation chamber does not allow mass separation of the ions. The

chamber is basically a plasma etcher. Hydrogen gas is introduced at low pressures

(base pressure of ~1 µTorr, working pressure of about 0.2 mTorr) and the plasma is

ignited. The plasma will be composed of several species of hydrogen: H+, H2+, H3+...

as well as electrons and neutral particles. Since there is a bias between the sample

stage and the chamber, the ions are accelerated towards the cathode and implanted in

the silicon sample. (This is, of course, a very simplified picture of what happens but it

will suffice for the purposes here.) The drawbacks with this method, are 1. sputtering

of the chamber material is inevitable and this causes the (typically) metallic ions to

also be implanted into the sample, 2. because the chambers are usually not designed

for UHV conditions, residual impurities such as nitrogen and oxygen as implanted
 98

Fig 3-4: Schematic set up of PIII. It can be seen that the implantation dose is
independent of wafer size. A typical dose rate is 1 ×1016 cm-2 s-1 [10][After P.K.
Chu et al., J. Vac. Sci. Tech. A 19(5) 2001]

in large quantities [10], and 3. that because the implanted ions have different masses,

they are implanted into the substrate with multiple different dose and damage

distributions. (See figure 3-1)

A question comes up with this introduction of impinging ions of different

masses: Does the more massive ion create more damage? If we examine this in terms

of the effective cross section of collision, we can perhaps gain more insight. Assuming

that the magnitude of the damage created by the collisions is proportional to the cross

section, we have [11]:

σ (θ) = (Z1Z2 e2/4E)2 [sin-4 (θ/2) - 2(M1/M2)2 + …]

 99

where the leftmost term in the parenthesis is the first order Coulombic repulsion term

and the terms in the brackets are the higher order corrections due to atomic recoil. σ is

the effective scattering cross sectional area that the incoming particle sees approaching

the target, θ is the deflection angle measured with respect to the direction of the

impinging particle, Z1 and Z2 are the atomic numbers of the incident particle

(hydrogen in our case) and the target particle (silicon in our case), e is the electronic

charge, E is the incident kinetic energy, and M1 and M2 are the masses of the incident

and target atoms. This expression comes from a two-body central force problem

accounting for recoil of the atoms and is an expansion of a power series from a more

concise expression. Assuming that M1 << M2, which is true in our case for hydrogen

(M1=1) and silicon (M2=28), the cross sectional dependence on mass is quite small,

∆σ ~ 2 (M1 / 28)2 is 0.25% for M1 = 1 (H+) and 2.3% for M1=3 (H3+). The difference

is about an order of magnitude and shows that there can be more damage from the

larger ions. Another easily remedied problem is that, at least in this chamber, the

vacuum was not particularly high (i.e. pressure was not as low as it could be) and so a

host of other contaminants may also have been implanted into the silicon (e.g. carbon).

This may introduce other effects which may not be easy to separate. The most obvious

one is a reduction of mobility which is observed for PIII vs. single ion implanted

silicon films on glass (see section 3.8.1.2).

Another feature examined using the PIII technique are the effects of the

implantation frequency (pulse width and frequency). The three implantation modes

used in this examination were DC (no voltage oscillation, just fixed anode and cathode
 100

potentials), long pulse (low frequency voltage oscillation) and short pulse (higher

frequency oscillation). The differences between the long pulse and short pulse is the

pulse width and the frequency (duty cycle). The short pulse and long pulse modes are

characterized by a 30 µs pulse width with a 300 Hz frequency and a 300 µs pulse

width with a 75 Hz frequency, respectively. The DC mode is a subset of these with an

infinite pulse width. The DC mode is characteristic for its mono-energetic implants.

The pulsed modes have low energy implantations included because of the finite rise

and fall times of the pulse. These low energies smoothly broaden the distribution of the

implanted ions and the damage profiles that result (see figure 3-6). This is on top of

the fact that there are several species of the ion that could be implanted, which by

itself will result in varying depths. The DC mode only had the single complication of

multiple ion (different masses) implantations. This would result in distinct damage

distributions which would result in a rougher cut. With the AC modes, the effect of

having the lower energy implants effectively introduces a continuum of implanted

distributions making the cut smoother in the small scale but potentially rougher over a

long range. The small scale RMS roughness of PIII silicon on glass as measured by

contact mode AFM is shown in Table 3-1. As seen under a Nomarski microscope (not

included here because features do not show up well in the photograph), the AC

implanted, exfoliated films are clearly more bumpy and patchy compared to the DC

implanted films (under 1000× magnification). For the DC mode implant, the electrical

characteristics seem to be more stable compared to the long pulse implantation which

was more stable than the short pulse implantation. To examine the potential effects of
 101

contamination, secondary ion mass spectroscopy (SIMS) analysis was done to see

what sort of impurities may have been introduced (figure 3-5).

DC
Si film glass
24
10
Concentration (atoms/cc) 23
1x10
O
22
10
21 H
10
20 C
10
N
19
10
0 500 1000 1500 2000
Depth (Å)

Long Pulse
Si film glass
24
10
Concentration (atoms/cc)

23
1x10
O
22
10
21
10
20 C H
10
N
19
10
0 500 1000 1500 2000
Depth (Å)

Fig 3-5: SIMS analysis done on PIII DC and Long Pulse Si on glass samples. The
thickness of the film is denoted by the dotted line(s) close to 1500Å. The glass was
Corning 1737F glass. Note the thickness of the silicon film is different for the DC
and AC mode implantations. This is the result of the broadened
implantation/damage profile produced by the low energy implants characteristic
of the AC mode.
 102

Bias
Max. implant energy/bias

(a)
time
Lower energy implant regions

Implant concentration/ Projected range from max.

implant energy
damage
AC Cleavage area
Integrated damage
mode distribution
(b)
depth
Low energy implants

Implant concentration/
damage
DC Integrated
mode damage
distribution
(c)
depth
Multiple ion implants

Figure 3-6: Differences between DC and AC mode PIII implantation. (a) The
finite rise/fall times for AC mode PIII implantation. (b) The low energy implants
effectively make a continuum of distributions, increasing the width of the
cleavage depth. (c) multiple ion implants introduce more discrete distributions
and therefore more discrete cut depths. The central peak of the integrated
damage distribution will tend to be larger due to more overlap. The effect of this
is that the implanted ions are spread out more smoothly (b), compared to the DC
mode which has more discrete cut depths (c). Because of this broader
distribution, the cut depth is not precisely defined. The effect is to give a much
larger range of possible cut depths. This will result in the cut depth varying over
the film giving a long range surface roughness (AC mode) and a short range
surface roughness (DC mode).
 103

Table 3-1: RMS roughness of PIII silicon on glass for the different implantation
modes as measured by AFM. Short pulse = 30 µs/300Hz, Long Pulse =
300µs/75Hz.

PIII Implantation mode RMS roughness (Rq) (nm)

DC 5.574

Long pulse 5.222

Short pulse 4.575

There were no obvious characteristics which stood out other than the fact that the AC

implanted films had a more non-uniform distribution compared to the DC implanted

films, and the AC implanted films were noticeably thinner than the DC films. The

thinner AC films is likely the result of the broadened damage distribution, which

creates a range of possible cut depths. The effect of this would be potentially smoother

films at the atomic scale but at the cost of larger long range roughness. This is similar

to what was observed with the low temperature implantation of hydrogen into silicon

(discussed earlier). It would not be unreasonable to think that the low temperature

implanted films were thinner than room temperature implanted films because the low

temperature implantation damage distribution was broader. This would result in

smoother (atomic scale ) films which is what was measured with the AFM (Table 3-1).

Cross sectional TEM (Figure 3-7) was performed on PIII (DC mode) silicon

glass samples at the Hong Kong University of Science and Technology (HKUST)
 104

[13]. Hall effect, hot probe and four point probe measurements were performed on

these exfoliated films and are discussed later. These are compared to single ion

implanted films on glass.

In this section, the ability to have a single crystal layer of silicon on an

amorphous layer (glass) was demonstrated using the ion cut technique with single ion

implantation and PIII. The glass limits the scope of the study because of its relatively

low strain point of 666 °C which means that all process temperatures used to study the

film characteristics must be kept below this temperature. To get a wider scope, the

study will progress with silicon on thermal oxide. This will allow electrical

characterization using process temperatures ~1000 °C and avoid additional

complications due to restrictions from the glass substrate such as strain point

temperature and chemical impurities from the glass.

 105

Defective Si

Cut depth
Si

Glass

(a) As-exfoliated Si/Glass cross section.

Si

Glass

(b) Si/Glass interface

Figure 3-7: Cross sectional TEM of DC mode PIII for silicon on Corning 1737F
glass. In (a), the layers of the glass, silicon and damaged silicon layer are clearly
seen. The damage layer is 500 Å thick and the total cut depth for the silicon film
is ~1500 Å for the 30 kV implantation. The diffraction pattern is for the middle
silicon layer and shows that it is still mono-crystalline. In (b), a close-up of the
silicon-glass interface is shown. (After F. Lu et al, J. Vac. Sci. and Tech B,
Sept/Oct 2003)
 106

3.3 Implantation induced damage profile

With mass separation (ion selectivity), a single type of ion with a well known

energy produces a well defined implantation profile in the target substrate. Using

Monte Carlo based simulations, the ion concentration and damage profile can

be calculated and simulated with SRIM/TRIM (by James F. Ziegler). The important

difference here is that the ion distributions and the damage distributions are in

general not the same [14], as seen in figure 3-1. The basic idea is that the hydrogen

not only creates a distribution of broken bonds but also chemically passivates the

dangling bonds, preventing them from easily reforming and thus creating a semi-

permanent network of hydrogen. As the implanted sample is annealed, the hydrogen

collocates to form H2 gas increasing the pressure in the cavity. This pressure is forced

laterally across and below the sample surface when there is a mechanical stiffener

(wafer bonded to surface). This will result in delamination of the film from the

substrate.

3.4 Electrical characterization of films

3.4.1 Hall effect

The Hall effect has been discussed in detail in many textbooks [15-20] so it

will not be repeated here. The Hall effect measures the voltage difference across two

surfaces which are perpendicular to the direction of current flow. This is a function of

temperature, magnetic field, sample type...among many other things [15-20]. This
 107

measurement can reveal the carrier density, mobility, and conductivity -- important

parameters in characterizing the electrical properties of these exfoliated films.

Indium was soldered onto oxide free surfaces at four points (Van der Pauw

technique) [19] to provide ohmic contacts to the Si film. The solder has to wet the

surface as shown in figure 3-8b and a quick resistance measurement using a Fluke 89

multi-meter was used to verify that the contacts have similar and symmetric

resistances. The Hall voltages were set by a Keithley 220 programmable current

source and measured with a Keithly 617 programmable electrometer. Note that

warming up these machines for several hours allows some stabilization to occur and

may optimize the measurement conditions.

Indium dots

3-5 mm
3-5 mm
(a)

Indium solder

Bare Si surface

(b) WET NOT WET

Figure 3-8: (a) 3-5 mm on a side sample with indium solder dots. (b) Illustration
of indium wetting and not wetting the surface for good ohmic contacts to silicon.
Essentially, the contact angle should be small.
 108

The films were electrically characterized as a function of depth into the film.

Tetramethyl-ammonium hydroxide (TMAH) was used to etch off layers of the Si film

in roughly 500 Å increments. TMAH is a popular Si etchant because it can etch off Si

layers while providing smooth surfaces with less toxicity than the usual KOH etchant.

It also has the additional benefit of not containing potassium (K) which can cause

contamination problems in devices (e.g. threshold shifts in MOSFETs). The solution

was nominally 25% concentration by weight in de-ionized water and was used at

temperatures of 60-85 ºC. The solution was reused (because it wasn’t cheap enough to

dispose of every time) resulting in the “active ingredients” becoming depleted --

forcing a higher temperature to be used in order to have similar etch rates (~100 Å /

sec) [21].

3.4.2 Hot probe

The hot probe (or thermoelectric probe) test is used as a quick confirmation of

the Hall effect type test. Most of the time, the two measurements agree with each

other. They most often disagree when the sample is highly resistive possibly by

surface depletion, excessive trapping (implantation induced usually), etc. This has

been discussed in Dieter Schroeder’s book [16]. Essentially, two sharp, metallic

probes are placed on the In contacts and a hot soldering iron is applied to one of the

probes near the sample (the indium contacts are not really necessary). A voltmeter is

attached to the metal probes. The way this works can be thought of as: the high

temperature probe drives away the majority carrier from the hot area (by diffusion).

The diffusing carriers create an electric field to counteract the diffusion and the
 109

potential difference across the electric field is measured. For example, if the sample is

n-type, applying a hot soldering iron to the probe attached to the positive side of the

voltmeter, causes the electrons to flow away and to the cold probe. This means that the

(hole) current goes from the cold probe to the hot probe. Since the voltmeter can be

thought of as a large resistance, the current will cause a positive voltage to be induced

on the positive voltage probe (display shows a positive voltage). If the display voltage

is negative, it means that the sample is p-type.

3.5 Thermal donors in Silicon

3.5.1 Phenomenological introduction

The starting material for this film exfoliation process was always p-type (001)

Czochralski (CZ) grown single crystal silicon wafers. What was noticed after the

exfoliation process was that the film became n-type as measured with hot probe, four

point probe and Hall effect measurements. Upon annealing at temperatures of 650-

~1000 °C in nitrogen, the (cold cut) films usually returned back to the native p-type

conductivity. This phenomena was attributed to what is called thermal donors – which

are newly introduced states which happen to have an extra electron or two (the number

of electrons will be discussed later in this section). These thermal donor states arise

from oxygen clusters that form within the silicon lattice. The mechanics of the

formation and thermal evolution of these will be discussed.

 110

3.5.2 Origin, formation and thermal evolution of thermal

donors

The formation of thermal donors in silicon has been intensely studied since the

1950’s but there is still debate over their physical and chemical structure [22-31]. This

is due to sometimes inconsistent data which is presumably the result of the sensitivity

of thermal donor formation to many factors. These factors include complex issues

such as thermal history, any number of substitutional and interstitial impurities,

defects, and strain. To top it off, these thermal donors geometrically and chemically

evolve during the heat treatments. What is known has been determined mainly through

Fourier transform infrared measurements (FTIR), TEM, deep level transient

spectroscopy (DLTS), and electron paramagnetic resonance (EPR or NMR) [27,29-

31].

Overall, thermal donors are formed in Czochralski (CZ) silicon from clustering

of oxygen [30], and/or precipitation of SiOx and/or silicon self-interstitial phases

[32]. The oxygen is present in Czochralski silicon due to the use of a silica crucible

from which the single crystal boule is pulled [27]. The amount of oxygen can be as

high as ~2×1018 cm-3, which is the solubility limit of oxygen in silicon at the melting

point of silicon [33]. Upon cooling, the oxygen becomes supersaturated in the silicon

lattice. At temperatures close to room temperature, the oxygen is frozen in and being

interstitial, has negligible electrical activity. When the silicon is annealed at

temperatures above 300 °C, the oxygen becomes mobile [28] and tends to form

clusters [32-34]. These clusters of oxygen range from four to as high as twenty-four,
 111

(and possibly even higher) with a mean size of roughly ten oxygen atoms [31,32] as

determined by four point probe, FTIR, ab-initio calculations and electronic transitions

from the ground state to the 2p0 excited state [32, 34]. The oxygen clusters were found

to have a C2V symmetry along the <001> axis [31] and have decreasing ionization

energies as the size of the cluster increased [32] – reminiscent of a kind of “macro-

atom”.

The addition of oxygen atoms to a cluster changes the electrical properties and

creates a new species of thermal donor. The thermal donors (TDs) that have been

discussed can be either shallow (single) thermal donors or what are termed “thermal

double donors” (TDDs) due to the fact that they carry two free electrons [35]. These

double donors are subdivided into 2 categories: neutral and positively charged [32].

The neutral category is further subdivided into 16 different defects: TDDx0, where x

ranges from 1-16 (ionization energy ranges from 69.2-41.9 meV). The positively

charged defects are subdivided into 9 cases: TDDx+, where x ranges from 1-9

(ionization energies range from 156.3-116.0 meV) [32]. These TDDs have a common

core [31] and the increase in x shifts the donor state closer to the conduction band

edge. The presented thermal donor picture so far seems busy, but relatively

straightforward. However, to illustrate the confusion in the literature dealing with this

issue, there have been reports that the addition of an oxygen atom to a pre-existing TD

can render it electrically inactive [28]. To complicate things even more, the

introduction of hydrogen, which is what was used to do the ion cutting of the films in

this thesis, acts as a catalyst to the formation of these thermal donors [29]. Also,
 112

hydrogen can bond strongly with the thermal double donor turning it into a shallow

single donor [35]. It is known that hydrogen is unique in this way from studies of

introducing helium, argon, argon/oxygen mixtures, and nitrogen by plasma and

observing no effects quite like those produced by hydrogen [36].

The formation of oxygen clusters and precipitates has been correlated with a

decrease in interstitial oxygen and vice-versa [28,31,32]. Without the introduction of

hydrogen, annealing times in excess of 20 hours at temperatures of 700 °C have been

observed to be be necessary to see significant change [32]. With hydrogen, it seems

that formation of these thermal donors require only minutes (based on thermal

exfoliation times). The formation of the type of thermal donors are also affected by the

anneal temperature as seen in table 3-2.

Table 3-2 : thermal donor type as a function of anneal temperature range. [after
Om Prakash, [28]]
Anneal Description
temperature
(°C)
300 – 850 Oxygen thermal donors in general

300 – 470 Thermal single and double donors

450 – 550 New thermal donors

(smaller generation rate and higher thermal stability)
New donors
600 – 700
(has an incubation period which can be reduced by pre-annealing
at ~450 °C)

As mentioned, the TDs formed at higher temperatures will have larger cluster sizes

and larger clusters have been reported to be more stable than smaller ones. This
 113

interesting fact comes about due to Ostwald ripening [28], where smaller than average

clusters are redissolved and taken up by the larger clusters. However, this presents a

dilemma. Because the clusters are in a lattice, a larger cluster would present more

localized strain to the lattice and thus be more likely to be energetically unfavorable.

It would seem that there would have to be a tradeoff between the driving force from

supersaturation of the oxygen atoms and the strain. The tradeoff is that the oxygen

clusters continue to grow but due to the volume expansion, the addition of two

interstitial oxygens means that one silicon self-interstitial is produced to alleviate the

strain [41,42]. It is not clear if the strain is completely relieved or if some residual

stress is accumulated. The build up of silicon self intersitials introduces a different

phase known as a silicon precipitate. These precipitates typically form ribbons of

hexagonal silicon which is associated with what are termed “new donors” (NDs) [33]

(these have to be differentiated from another class of thermal donors called “new

thermal donors”).

With the films used in this thesis, thermal donor effects are seen throughout the

process. As mentioned, the initial material is p-type; after exfoliation (300 °C for

mechanically exfoliated films, 400-450 °C for thermally exfoliated films) the films are

n-type. What should be expected for the as-exfoliated (not annealed) films is minimal

thermal donor effects in the mechanically exfoliated films and definite and possibly

substantial thermal donor influence in the thermally exfoliated films. After annealing

at 650 °C for 4 hours in nitrogen, the mechanically exfoliated film returns back to its

native p-type conductivity, however, the thermally exfoliated film does not. In fact,
 114

the thermally exfoliated film is highly resistive at anneal temperatures from 550-650

°C, and remains n-type even after annealing at 1050 °C for 1 hour in nitrogen. This

effect is likely due to the time at the maximum exfoliation temperature as noticed by a

Russian group [35]. The return to p-type conductivity is the expected result

presumably because the thermal donor states may effectively “dissociate” –

eliminating the donor level. However, as we have seen from the description above, the

real picture may not be that simple.

To summarize this section, with the material we used, oxygen thermal donors

will have at least some, if not substantial, influence on the properties of the silicon

film. This is compounded in complexity by the introduction of hydrogen and possibly

by the implantation induced damage layer on the film surface. The thermal evolution

of the thermal donors, new thermal donors and new donors (note to reader: “new

thermal donors” are not the same as “new donors”) are driven by (chemical)

supersaturation, and (physical) strain relief nucleated by some sort of defect such as

substitutional or interstitial carbon, dislocations, or under the right conditions, possibly

homogeneous nucleation. The strain relief introduces precipitates of SiOx (oxide

precipitates (OPs) ) and self interstitial silicon which can act as a nucleation point for

new donors [33]. What is clear is that the evolution of the thermal donors has to do

with the clusters/precipitates growing bigger with longer anneal times and higher

temperatures.

With all these complications with Czochralski Si, why isn't float zone Si used

more often? [27] It turns out that the occurrence of high concentrations of interstitial
 115

oxygen can be beneficial for the manufacture of electronic devices. The temperature

cycling encountered during device fabrication processing causes the interstitial oxygen

to form precipitates of SiO2. These precipitates act as intrinsic gettering sites for fast

diffusing transition metal impurities and also as "pins" for dislocations because they

can grow in the cores and inhibit glide and dislocation multiplication arising from

local stresses [26]. These features have the benefit of increasing device yields for CZ

Si.

3.6 Experimental considerations : annealing and measurement

details
After the films were exfoliated onto a handling substrate, they were cleaved

into square pieces roughly 3-5mm on a side for Van der Pauw and Hall effect

measurements. Since these measurements involved etching off ~500 Å (measured

using the Filmetrics F20 optical thin film thickness measurement system which has a

~50 Å effective resolution) of the silicon film using TMAH, etching off the native

oxide, soldering four indium dots, making the series of voltage measurements to get

the resistivity, Hall mobility, and sheet charge; each data point took a little time. It

required roughly 30 minutes per data point if there were no surprises or snags in the

process. To measure a series of 4-10 points took several hours at best, to the whole

afternoon or whole day (at worst). When this was first performed, the best use of time

was to just keep going, finish where you finish and continue the next day. However,

some large jumps in the measured parameters occurred and it was noticed that they

happened in between the points which were taken on consecutive days with a time gap
 116

of ~10-14 hours. Measuring the same point that was finished at the previous day

showed that the measurement was significantly different the next day. This is

speculated to be due to changes on the surface which are related to oxidation, but even

if the oxide was etched

Effect of annealing in air vs. nitrogen for PIII DC

silicon on glass

10
)
-2

5
Sheet charge (cm

-5 air
nitrogen

-10
0 5 10 15
Anneal time (hours)

Figure 3-9: PIII DC mode silicon on Corning 1737F glass measurements as a

function of annealing ambient. It is relatively clear that annealing in air has a
detrimental effect, making the sheet charge values jump erratically. Annealing in
nitrogen seems to solve this problem. The expected type of the silicon film is n-
type for the as-exfoliated film and p-type for the annealed samples. It is for this
reason that the sheet change at time zero is not included.

off and the indium contacts resoldered, the values were usually not close to the values

measured the day before. The bottom line is that the measurements should be done in
 117

one run with a time gap of less than about two hours if the measurements are to be

consistent. Another factor that can change the measured values is the annealing

ambient. In the early stages of this research, the samples were annealed in air.

However, the following graph shows that annealing in air seems to change the

measured values somewhat unpredictably.

The variations from annealing in air were solved by annealing in nitrogen. The

measurements were much more consistent (figure 3-9). The only drawback

Table 3-3: Hall effect and hot probe measurement data for DC mode PIII silicon
on glass. The sheet charge as a function of time was plotted in figure 3-10. Hot
probe measurements only give conductivity type.
Sheet charge Hot
Anneal time (hrs) Si thickness (Å) ρ (Ω.cm) n (x1015 cm-3) µ (cm2/V.s)
(x1010 cm-2) Probe
annealed in air
0 1550 5.2 -31 -40 -47.6 N
2 1550 391 -1.1 -15 -1.67 P
4 1550 223 4.96 5.6 7.7 P
6 1550 147 4.6 9.2 7.1 P
8 1550 127 -2.6 -19 -4 P
10 1550 123 1.3 3.9 2 P
12 1550 144 -2.1 -20 -3.3 P
14 1530 217 2.2 13.4 3.3 P

annealed in nitrogen
0 1550 3 -220 -10 -330 N
2 1550 H.R. --- --- ---
4 1530 248 1.2 21 1.9 P
6 1530 77 5 16 7.7 P
9 1530 78 3.8 21 5.9 P

with annealing in nitrogen was the fact [46] that nitrogen can create deep level traps in

Si. If they form, they can reduce the carrier mobility and sheet charge densities. An

alternative to this is to anneal in argon (see figure 3-10), which shows a marked
 118

improvement in the carrier sheet charge. It can be seen that the largest difference

between the samples where the damage layer is etched off before being annealed (EA)

and the samples where the damage layer is annealed before being etched layer by layer

(AE), is that of argon annealing. This lends credence to the fact that annealing in

nitrogen may introduce traps (solid and hollow circles on plot), which may explain

why the EA and AE profiles are relatively close together in figure 3-10. With oxygen

Thermally exfoliated Si/Oxide annealed

800 °C / 4 hours.
18

16 EA -Ar
AE - Ar
14
Electron Sheet charge

EA - O2
12 AE - O2
× 10 11 (cm -2 )

EA - N2
10 AE - N2

0
0 1000 2000 3000 4000 5000
Depth into Si (Å)

Figure 3-10: Thermally exfoliated (hot cut) silicon on wet thermal oxide sheet
charge depth profile as a function of annealing ambient and whether or not the
damage layer existed. In general, the presence of the damage layer reduced the
electron sheet charge and annealing in an argon ambient resulted in the highest
electronic sheet charge. “H.R.” is highly resistive, which means that the samples
could not be reliably measured.
 119

annealing, the variation is much greater which makes it undesirable since it is

then difficult to predict.

One interesting pattern observed in figure 3-10 is the clear rise and fall trend of

the carrier profiles. Even for the EA samples where the damage layers have been

etched off prior to annealing, the electron sheet charge continues to increase for ~1000

Å or so. This suggests that the defect layer extends slightly into the crystalline region

(from TEM, see figure 3-5) and upon annealing, diffuses deeper into the film.

Normally, it would be expected that the sheet charge only decreases as you etch away

the surface. The reasoning behind the increase is that a compensated layer is present

which is the byproduct of the traps from the damaged layer.

3.7 Silicon film characteristics

Even though the data from the previous section shows that annealing in argon

rather than nitrogen seems to give higher carrier densities (which is seen as a positive

attribute), using argon as the annealing ambient was not always convenient in different

annealing furnaces. To be consistent with previous material processes and studies,

annealing was always done using nitrogen unless otherwise specified.

The electrical characteristics of the exfoliated films using Hall effect and hot

probe measurements will be presented in the following section(s). From the Hall

effect measurements, resistivity and sheet charge are used to calculate volume carrier

concentration and carrier (Hall) mobility. To relate this material data to what is

needed for our intended application, recall from chapter 1 that, the channel mobility

desired for a reasonable value of current conduction was ~100 cm2/V.s. This was for
 120

the worst case of only using one MOSFET/pixel. For “stacked” TFTs, [see chapter 1

for TFT configurations] the mobility requirement would be less stringent.

Nevertheless, 100 cm2/V.s is a good reference point. Since the Hall mobility can be

calculated using the sheet charge and resistivity, [16] it can be seen that the mobility

is inversely proportional to the carrier density, which is expected since a higher

concentration of free carriers increases scattering. A large value of mobility, therefore

implies that the carrier concentration is low. A low carrier concentration can be

interpreted as being the result of traps which can increase leakage currents in the

MOSFET channel. Traps are essentially disturbances in the periodicity of the lattice

which create a state in the band gap which act as carrier recombination/generation

sites. We would like to minimize the presence of traps to maintain material quality.

On the other hand, a large carrier concentration does not necessarily mean that the

material is good. The formation of donor states (e.g. oxygen related thermal donors,

new donors) will increase the carrier density and reduce the resistivity and will also

introduce states in the material bandgap. A balance will have to be made to balance

out mobility and carrier concentration for this application. From the measured Hall

effect data, a sheet resistance, Rs, can be extracted. [16, p. 202] Knowing the film

thickness allows the calculation of the film resistivity ( ρ = Rsd ). Likewise a sheet

charge, Qi, can be calculated from the Hall effect measurement, and with the value of

the film thickness, a volume carrier concentration is obtainable ( nvolume = nsheet / dfilm ).

[50] From the general definition of conductivity, σ = neµ, we can

get µ = 1/ (ensheetRs) = 1/ (e n ρ ). If we set the desired value of mobility as a minimum

 121

of ~100 cm2/V.s, we get a relation between the film resistivity and the carrier

concentration:

ρ n = ( e µmin )-1

Tradeoff between exfoliated film resistivity

and volume carrier concentration

1.E+03
2
mobility = 100 cm /V.s
film resistivity ( Ω .cm)

2
mobility = 200 cm /V.s
1.E+02 2
mobility = 300 cm /V.s
2
mobility = 400 cm /V.s
1.E+01

1.E+00

1.E-01

1.E-02
1.E+14 1.E+15 1.E+16 1.E+17 1.E+18
-3
volume carrier concentration (cm )

Figure 3-11 : Plot of required film resistivity so that mobility is at least 100
cm2/V·s as a function of carrier concentration.

Since the values of ρ are taken for thin films (SOI), the relation should be valid for

films in general. Values of n are in the range of ~1014 – 1017 cm-3. This allows us to

plot the desired values of film resistivity to get a reasonable mobility. So for a carrier

concentration of ~1×1016 cm-3, we would like a resistivity of less than or about 10

 122

Ω.cm. Cross checking these values with actual measured values (listed in the

appendix) show a good correlation. This can be used as a guide during the Hall effect

measurement as an additional check to the validity of the data.

3.8 Electrical measurements

3.8.1 Silicon on insulator structures

From the applications perspective, the goal is an understanding of the behavior

of silicon films exfoliated on glass. However, using glass as the mechanical support

substrate introduces the constraint that processing temperatures cannot go much above

650 ºC due to the strain point of the 1737F glass (666 °C). Fabrication of MOSFETs

on glass would then entail making use of many low temperature processes which

would add numerous new variables to the study; this would make it more difficult to

focus on the film properties by themselves. Therefore, this approach was not taken and

the use of thermal oxides as the gate dielectric was used.

Using the traditional silicon on (wet) thermal oxide SOI structure allows us to

concentrate on the film and its behavior under varying thermal histories. In particular,

carrier distributions, thermal donors and possibly trap or defect diffusion. The anneal

temperatures can go up to 900-950 ºC so we can see how these parameters vary as a

function of the anneal temperature. Above ~950 ºC, however, the type changes from

the recovered p-type conductivity to n-type conductivity. This was not expected. For

Si films on oxide, however, this does not matter since we can merely make a p-

channel MOSFET, assuming that no significant differences are introduced.

 123

The follow sections will first show silicon on glass electrical results, then move

on to silicon on wet thermal oxide studies.

3.8.1.1 Silicon on glass experiment

The materials used were Corning 1737F glass and prime grade, Czochralski

grown, p-type (~4.5×1014 cm-3), (001) oriented, 2 inch silicon wafers. The glass was

degreased in DeContam®, and both the glass and silicon were cleaned in organic

solvents using trichloroethylene (TCE), acetone and isopropal alcohol (IPA) and

rinsed in running deionized water for 1 hour before being spun dry. Following that,

both substrates were activated in an oxygen plasma (100 Watts, 200-500 mTorr) for

30 secs, dipped into RCA-1 (75 °C) for 45 secs, rinsed in deionized water and blow

dried with nitrogen before contacting the two surfaces. The bonded pair was then

annealed at 300 °C for 2-16 hours before increasing the temperature to ~400-450 °C

for thermal exfoliation. (All silicon on glass samples were only thermally exfoliated)

There are two sets of silicon on glass samples. One set was implanted with

plasma immersion ion implantation scheme and the other with the more conventional

single ion beam. The electrical properties of these films are presented for as-exfoliated

and annealed (at 650 °C typically for 4 hours at a time) as a function of depth into the

film using layer by layer etching and Hall effect/hot probe measurements. Four hours

seemed to be the minimum anneal time that would usually give consistent results. The

etchant used was 25% (by wt.) tetramethylammonium hydroxide. The intended etch

interval was 500 Å steps, which was usually followed. The film thickness was
 124

determined using a Filmetrics model F20 reflectometer which has an effective film

resolution of ~ ±50Å.

Electrical data was taken using a Van Der Pauw / Hall effect measurement set

up as described previously. Square sample pieces roughly 3-5 mm on a side were used

with indium solder for ohmic contacts making sure the indium had actually wet the

surface of the silicon film. A 1-2% hydrofluoric acid solution was used before

applying the contacts for each measurement to make sure there was no native oxide

present (hydrophobic surface). From the measurement, resistivity, carrier

concentration, carrier type, mobility and sheet charge were obtained as a function of

depth into the film, in ~500 Å increments. Each point was measured after using

TMAH (25% nominal concentration by weight, 55-85 ºC, with stirring [whatever was

necessary to maintain about 100 Å/sec etch rate] as the Si etchant, an HF dip and a

quick film thickness measurement using the Filmetrics F20 optical thin film

measurement system.1

3.8.1.2 Silicon on glass results

Figure 3-12 shows the measured silicon on glass carrier concentration as a

function of depth for separate as-exfoliated and annealed films. There are two sets of

data for the annealed films. One has the damage layer (1500 Å thick from TEM) intact

1
To use the Filmetrics F20 system effectively, there are several things that can be done. Turn off robust thickness check box
(it’s unclear what exactly this does but seems to use a simpler calculation to get the film thickness(es). Narrow the search range
(under “constraints”). I usually try to keep the search range in the 10-20% (of the rough film thickness estimate) and < 1% for
layers such as oxides that are well known. The third point is that sometimes you will saturate the detector and the reflectance
spectrum will have noticeable notches in the peaks. You can re-establish a new baseline by choosing “Setup/Data Acquisition”,
deselect “Autoscale integration”, reduce the integration time and retake the reference. Redo the standard baseline with a standard
silicon wafer and it should be calibrated to handle the new reflectivity without saturating the detector. [51]
 125

as the film was annealed (anneal then etch), while the other was annealed after etching

off the damage layer (using TMAH). For all three sets of data, the average carrier

concentration increases as a function of depth. The reasoning given for this is either

that the carriers are compensated or close to being compensated near the film surface

or that implantation induced damage is maximum near the film surface (more traps)

and decreases with depth (less traps). For the as-exfoliated film (no anneal), the

increase in average electron concentration increases more than an order of magnitude

PIII DC SOG average carrier

concentration depth profile
[anneals done for 4 hrs@650C in nitrogen face down, etches done with TMAH]

1.E+19 as exfoliated [electrons]

anneal then etch [holes]
-3
)

etch then anneal [holes]

1.E+18
concentration (cm
average carrier

1.E+17

1.E+16

1.E+15

0 500 1000 1500

depth into silicon (Å)

Figure 3-12: Average carrier concentration depth profile for plasma immersion
ion implanted (PIII) silicon on corning 1737F alumino-silicate glass. The donor
wafer (implanted wafer) was implanted with H+ at 30 kV giving a cut depth of
roughly 1500 Å with a 500 Å damage layer at the surface. The as-exfoliated data
is n-type and increases throughout the damaged region before dropping off. The
data for all three sets stops short of the final hundreds of Angstroms because the
film becomes highly resistive and is not measurable using Hall effect.
 126

before falling off, presumably due to surface depletion from the opposite side. After

annealing, the increase is only about half an order of magnitude. This is consistent

with the trap density following the damage distribution. The etch then anneal case

(EA) (▲) was done to see if there was any substantial contribution from the damage

layer. From figure 3-12, it looks like there isn’t much difference but there is a

noticeable increase in hole concentration.

To compare PIII implanted films with single ion implanted films, the same

layer by layer etching is done for single ion implanted silicon films exfoliated onto

glass as shown in figure 3-13. The same procedure applies, except after bonding, one

Average electron concentration depth profile

for single ion implanted SOG as exfoliated
[25% TMAH etched]

1000
Electron concentration
x10 [cm ]

100
14 -3

14 hrs.@300C [n-Si]
10 2 hrs.@300C[n-Si]

1
0 1000 2000 3000 4000
Depth into silicon layer (Å)

Figure 3-13: Single ion (as opposed to PIII), as-exfoliated implanted silicon on
glass films. The different anneal times are for the wafer bonded pair (before the
film was exfoliated.).
 127

bonded pair is annealed for 14 hours at 300 °C in air (■), and another annealed only 2

hours at 300 °C in air (▲). One difference is readily apparent to the astute reader: the

PIII films are inherently thinner than the single ion implanted samples. This is due to

the experimental difficulties associated with PIII (increased X-rays, etc.). PIII can go

to higher energies for deeper implants but the operators chose not to at the time. This

was not a problem for single ion implanted samples which used energies of 50

keV/ion. From figure 3-13, it can be seen that after annealing for 14 hours, the

implanted depth is slightly increased (~2500 Å). Finally, a side by side comparison of

the cases for annealed then etched (AE) and etched then annealed to see the effect the

damage layer may have on the electronic properties of the film. From figure 3-14, the

AE and EA curves meet up at about 2300 Å. This suggests that the effect of the

damage layer, which is determined to be very close to 1500 Å from a TEM photo,

extends further. This can be attributed to thermally induced diffusion of vacancies

further into the film or possibly the tail of the damage distribution. The latter is more

likely since a calculation of the former for silicon self diffusion at 650 °C (for 4 hours)

gives a negligible value [52, p.206].

 128

Single ion implanted silicon on glass

[im planted at HKUST]
bonded pair annealed at 300C for 2 hours, exfoliated film
annealed at 650C for 4 hours
7
6
Hole sheet charge

AE
( ×10 11 cm -2 )

5
EA
4
3
2
1
0
0 1000 2000 3000 4000 5000

Depth into Si film (Å)

Figure 3-14: Comparison between thermally exfoliated AE and EA samples
annealed in nitrogen. From the way the graphs line up at about a depth of 2000-
2500 Å, one can speculate that the annealing may cause the defect migration to
that depth for the case where the damage layer is left intact. [diffusion of ~1000 Å
for 4 hours at 650 °C.]

3.8.1.3 Discussion of silicon on glass results

In general, comparing the PIII implanted vs single ion beam implantation, the

mobilities were significantly higher (about one order of magnitude) for the single ion

beam case. This is due to at least two factors: single ion implantation is done at a

higher vacuum and is therefore cleaner. The reduced impurity content is clearly a
 129

factor when the electrical properties are considered: data are more stable and it’s more

consistent. However, there is another factor which is coupled in which make the two

cases a little more difficult to compare. Since the PIII implantation was only done at

30 kV (it can apparently go up to 100 kV but for reasons such as higher X-rays,

samples heating, etc. it was not done) the ion-cut film was only ~1500 Å thick. This

thinner film inherently reduces the carrier mobility (see appendix for values) due to

increased surface scattering as well as the host of impurities that were implanted due

to non-ideal vacuum conditions. The effect of the damage layer has been shown to

reduce the carrier concentration, presumably due to the presence of traps. The traps

extend further than the visible damage layer most likely because the implantation

induced damage distribution has a tail. Even though thermal donors were not

mentioned in the results, there was a subtle introduction here by the fact that the as-

exfoliated films were n-type and the annealed films were p-type. This will be

discussed in more detail later on. Nevertheless, it has been demonstrated here that

silicon can be exfoliated onto glass with reasonable electrical properties suitable for

making flat panel displays.

3.8.2 Silicon on wet thermal oxide

Wet thermal oxide was used in order to keep the variables consistent with what

was done in chapter 2. The wafer bonding study was done using wet oxide (3300-5000

Å). Dry oxide was also used in the wafer bonding study but its role in the quality of

bonding is not conclusive due to limited data. However, based on the very limited
 130

data, there does not seem to be any difference between the wet and dry oxides with

regard to wafer to wafer bond strength.

These electrical measurements were performed using the same method

mentioned in the silicon on glass section (see §3.1 and §3.8.1.1) and done for

mechanically and thermally exfoliated films (mechanically exfoliated anneal

conditions: ~300 ºC for 2 hours in air on hot plate, no weight on top; thermally

exfoliated: 250-300 ºC hot plate and annealed for 2 hours in air, then temperature

increased to 400-500 ºC in 50 ºC increments for 30 minutes at a time until the wafers

separate with a soft 'pop'). Under these two categories, were the etched and annealed

(EA), and annealed and etched (AE) films. The “etch” referring to the ~1500 Å

damage layer etched off (using TMAH). Before any etching or annealing, however

was the as-exfoliated case. The annealing was done in a tube furnace in nitrogen at

temperatures in the range of 550-950 ºC for 4 hours and 1000-1050 ºC for 1 hour.

3.8.2.1 Thermally exfoliated films (hot cut)

These films were single ion implanted (as opposed to PIII ) on wet oxidized

silicon substrates (3300-5000 Å). They were annealed at 300 °C for 1-2 hours in air as

a bonded pair before raising the temperature to 400-500 °C until the film delaminated

(also in air). The data starts with the films being annealed (in nitrogen) at 900 °C,

instead of 650 °C. This is because the hot cut films were highly resistive after

annealing at temperatures from 550-650 °C in nitrogen for 4 hours. To further

complicate things, these hot cut films never returned back to the original p-type

doping, even after 1050 °C anneals.

 131

Hot cut Si/wet thermal oxide

annealed 900 °C / 4 hrs in N 2
12
Annealed before
10 etching
Electron sheet Charge

Etched before
8 annealling
x10 11 (cm -2)

0
0 1000 2000 3000 4000 5000
Depth into Si (Å)

Figure 3-15: Thermally exfoliated silicon on wet thermal oxide. The difference
between this data and the data for the 650 °C anneal in figure 3-14 is significant.
The AE data jumps all over the place compared to the EA data. This may suggest
that the diffusion of the defects from the damage layer has gone all the way
through the film.

In figure 3-15, the AE plot shows the usual increasing electron sheet charge in

the damage layer (left of the vertical dotted line) but then drops off with a more

complicated up and down fluctuation in a region about 1000 Å thick. The EA plot is a

smoother plot but still shows an increasing trend until about 2500 Å from the original

surface (which includes the damaged layer), which is consistent with the “extension”

of the damage layer mentioned earlier (section 3.8.1.2). The behavior of the AE plot
 132

(also figure 3-15) seems to suggest that the fluctuations (between 2800 Å and 3800 Å)

may be due to a damage layer migrating as a whole to a deeper part of the film and

Hot cut Si/w et thermal oxide

1050 °C /1 hr / N 2
20
etched before annealing
Electron sheet charge

15 Annealed before etching

x10 11 (cm -2)

10

0
0 1000 2000 3000 4000 5000
Depth into Si (Å)
Figure 3-16: Thermally exfoliated silicon on wet thermal oxide annealed at 1050
°C for 1 hour in nitrogen. This was done to see if the thermally exfoliated samples
could be turned back to its original p-type doping. Higher temperatures were not
attempted because the temperatures approached the softening temperature of the
quartz tube.

preferentially nucleating donor rich regions (if increasing sheet charge with depth

actually does indicate a damaged region.). To see if the hot cut films could be turned

back to it’s native p-type, annealing at 1050 °C was tried (see figure 3-16). Higher

temperatures were not attempted due to equipment limitations. At this point the AE
 133

electron sheet charge decreased monotonically as a function of depth (except for a

small part near the surface) indicating that the ion induced damage was annealed out.

However, the EA electron sheet charge fluctuated up and down and

VTT hot cut Si on wet thermal

oxide
100
charge x10 (cm )
-2

10
electron sheet
11

1
VTT hot cut as-exfoliated
VTT hot cut 950C / 4 hrs N2
0.1 VTT hot cut 900C /4 hrs N2

VTT hot cut 800C / 4hrs / N2

0.01
0 1000 2000 3000 4000 5000
Depth into Si layer (A)

Figure 3-17: Thermally exfoliated silicon films on oxide depth distribution. The
as-exfoliated data is superimposed as a reference. The annealed samples have had
the damage layers etched off before annealing. The main difference between the
annealed samples and the as-exfoliated sample is the drop off point. The higher
the anneal, the more sloped the profile becomes. This is an indication of a more
uniform distribution of carriers since this is a plot of the (average) electron sheet
charge.

then the sample became highly resistive, preventing further measurement. At 1050 °C,

points defects should be annealed out as shown in the AE plot and there should be
 134

very few vacancies left. Figure 3-17 shows the overplots of the electron sheet charge

depth distributions for the as-exfoliated and 800 °C, 900 °C, 950 °C anneals for 4

hours in nitrogen. This shows that the carrier concentrations of the annealed samples

do not fall off as quickly as the as-exfoliated sample but instead, remains within the

same order of magnitude. A further observation for the thermally exfoliated films is

that the higher the anneal temperature, the higher the maximum carrier concentration

(not counting the as-exfoliated data).

3.8.2.3 Discussion of hot cut results

These thermally exfoliated films on wet thermal oxide were exfoliated at temperatures

between 400-500 °C in air on a hot plate. After an initial 300 °C bond strengthening

anneal (wafer to wafer) the temperature was ramped up to 400 °C for 30 minutes, 450

°C for 3 minutes, and finally 500 °C or until the wafers separated. The unexpected

characteristics about these films was that they never returned to the native p-type

doping as was expected. When this was first encountered, it was not clear whether this

was due to some sort of contamination (VTT films were exfoliated at VTT electronics,

Finland), the nature of the exfoliation or something in the silicon wafers which was

activated by this process. However, contamination by n-type dopants after annealing at

UCSD was not likely since a low doped p-type BESOI Si wafer was measured before

and after annealing and it was found that there was little or no change in the carrier

concentration (doping was on the order of 1012 cm-3 as measured by Hall effect).

Since the cold cut films (next section) were also exfoliated at VTT electronics (albeit,

at a different time) and did not show these characteristics, it can probably be assumed
 135

that it was not due to some unknown contaminant. SIMS was performed on these

samples to see if the reason for the continual n-type conductivity was due to carbon,

nitrogen, oxygen, boron, or phosphorus. No obvious patterns or features were seen.

This anomalous behavior was also reported by a Russian group [40] where the

difference in conductivity type was attributed to exposure time to the thermal

exfoliation temperature. A reference by E.B. Yakimov et al. [61], showed that this

phenomena could be explained by the action of new donors. Apparently, pre-annealing

Czochralski Si around 450 °C (the thermal exfoliation temperature) enhances the

formation of nucleation sites for these new donors, which form in the temperature

range of 700-900 °C [28,33,61]. These new donors are essentially oxide precipitates

(OPs) which form from the reaction of interstitial oxygen with the surrounding silicon

lattice. These OPs have positive surface state charges, Qss, which is likely due to

localized excesses of Si atoms. The Qss is able to invert the conductivity type of the

region immediately around the OP. If the density of the OPs is sufficiently high, these

inverted regions can form a continuous inverted region. The conditions for the

formation of these new donors / oxide precipitates is consistent with the conditions

involved with thermal exfoliation.

3.8.3.1 Mechanically exfoliated (cold cut) films

The cold cut films are also single ion implanted and bonded to wet oxidized

silicon substrates (3300-5000 Å). After annealing at 250-300 °C for 2 hours in air, a

100 µm razor blade was inserted between the bonded wafers. Due to the strong wafer
 136

to wafer bonding and the weakened implanted interface, the film delaminated to form

the cold cut film. Comparison of the electron sheet charge depth distributions of the

As-exfoliated cold cut and hot cut films

100
electron sheet charge

cold cut
x10 (cm )

10
-2

hot cut

1
11

0.1

0.01
0 1000 2000 3000 4000 5000
Depth into Si film (Å)

Figure 3-18: comparison of as-exfoliated data for cold cut and hot cut films. The
vertical dotted line denotes the visible extent of the damage layer (through TEM).

as-exfoliated hot cut and cold cut films are shown in figure 3-18. Note that the hot

cut film changes only a very small amount up to the edge of the damage layer before

falling off very quickly. The cold cut film drops off linearly at a faster rate up to the

damage layer edge also before rapidly falling off. The unchanging average sheet

charge of the hot cut film in the damage layer means that there are few carriers there.

Figure 3-19 shows the AE and EA plots of the hole sheet charge for various anneal
 137

temperatures. All the AE cases are solid shapes while the EA cases are hollow shapes.

In general, the EA cases had a larger hole sheet charge compared to the AE cases.

Cold cut Si/wet thermal oxide

20
AE 650C [VTT]
EA 650C [VTT]
16 AE 800C [VTT]
hole sheet charge

EA 800C [VTT]
[ x10 11 cm -2 ]

AE 650C [HKUST]
12 EA 650C [HKUST]
EA 900C [VTT]
AE 900C [VTT]
8

0
0 1000 2000 3000 4000
depth into Si layer (Å)

Figure 3-19: The effect of etching before annealing and vice versa for cold cut
films as well as the effect of differing anneal temperatures. The basic trend is that
annealing at higher temperatures raises the carrier concentration and etching off
the damage layer before annealing, increases it even more. VTT indicates that the
samples were implanted and exfoliated at VTT electronics, Espoo, Finland; and
HKUST indicates that the sample was implanted and exfoliated at the Hong
Kong University of Science and Technology.

Annealing cold cut films to 650 °C (4 h, N2) produced a recovery of the p-type

conductivity. However, annealing above ~920 °C turned the film n-type again! Figure

3-20 shows the electron sheet charge depth profile for the Ea and AE cases. The EA

monotonically decreased, however, the AE case fluctuated after ~2000 Å.

 138

Cold cut Si on wet thermal oxide

annealed 1000 °C / 1 hr N2
12
damage layer Etched then Annealed
10
Electron sheet

Annealed then Etched

[ x10 11 cm -2 ]

8
charge

6
4
2
0
0 1000 2000 3000 4000 5000
Depth into Si layer (A)

Figure 3-20: Comparison of EA and AE samples for cold cut silicon on wet
thermal oxide annealed at 1000 °C for 1 hour in nitrogen.

3.8.3.2 Discussion of cold cut results

There are three distinct slopes seen in the hot cut data. This suggests that there

are more carriers just below the damage region in a thickness of about 1000 Å and

even more carriers below that. This is seen from the increasing slope. As a layer is

etched away, a large change in the sheet charge takes place. With the cold cut film,

there are not enough data points to see if the same trend follows. What is seen though

is that there is a relatively uniform concentration of carriers in the damage region and

quite a few carriers in the damage/”undamaged” interface (along the dotted line).
 139

Figure 3-19 shows the behavior of the cold cut films under various anneal

temperatures, all for 4 hour intervals in UHP nitrogen. The trend here is relatively

clear: higher anneal temperatures produce higher carrier sheet charges and etching the

damage layer before annealing increases the carrier sheet charge by about a factor of

two. For the most part, the removal of the damage region leaves carriers spread out

over the rest of the film rather uniformly, as is evident from the linearly decreasing

sheet charge. A similar trend is seen in the cold cut film annealed at 1000 °C for 1

hour in nitrogen as seen in figure 3-20. The removal of the damage layer results in the

resulting carrier distribution matching the same pattern of approximately parallel

sloped lines (♦). This is contrasted to the fluctuating behavior of the AE case (■).

The cold cut films differed most significantly from the hot cut films by the fact

that they returned to the native p-type doping after being annealed at temperatures in

the range of 650-900 °C in nitrogen. From figure 3-18, there are two main

differences between the hot cut and cold cut films. The first is that in the damage

layer, the electron sheet charge for the hot cut films barely change indicating that there

are few free carriers. For the cold cut films, there is a shallow but clear slope

indicating that, while there are not a lot of carriers, they are uniformly distributed

(linear slope). This is consistent with the fact that due to the low exfoliation

temperature, there are fewer thermal donors (see section 3.10 for more details) and

possibly fewer traps, though there is no easy way to distinguish between the two with

the data here. From figure 3-19, it is clear that etching off the damage layer before

annealing has a significant effect on the carrier sheet charge. The difference between
 140

the EA and AE curves (for each respective anneal temperature) is also proportional to

the anneal temperature, i.e. higher anneal temperatures lead to a bigger separation

between the AE and EA curves. This can be rationalized by defect diffusion from

inside the surface damage layer into the “bulk” of the film.

At anneal temperatures greater than ~920 °C, the cold cut films turn n-type

again. This is likely due to the formation of new donors which, through oxide

precipitates and surface state charges, can invert the material conductivity as it did

with the thermally exfoliated films in section 3.8.2.3. However, with the mechanically

exfoliated films, the films were not subject to the “requisite” pre-anneal temperature of

~450 °C [61] since they were delaminated from the substrate after an anneal of 300 °C

or less. This lower pre-anneal temperature allows the formation of fewer nucleation

sites for the oxide precipitates and a sufficiently high density of new donors do not

form until a temperature of ~920 °C is attained.

3.9 Strain characterization of hot and cold cut films on wet

thermal oxide
To a first approximation, strain in an epitaxial layer is easily measured using x-

ray diffraction. By measuring the angular separation of the substrate (zero order) and

the film (first order) peaks, and calculating the lattice strain using a differential form

of Bragg’s law [53], it seems straight forward. However, there are several assumptions

that are inherently made in order to use this relation unconditionally. The material is

assumed to be single crystal, lattice matched and is typically 2 layers including the

substrate (though it can be extended to multiple layers). The wafers are also assumed
 141

to be relatively flat so that any stress in the film can be measured and directly

correlated with the strain induced curvature [52]. In an SOI substrate, there are 3

layers, one of which is amorphous and depending on how the SOI substrate was

fabricated, the lattice orientation of the (100) plane may be different from the

substrate due to the fact that the film originated from a completely different wafer and

may possess a different tilt or offcut. The amorphous oxide layer being bonded to the

donor silicon wafer (implanted with hydrogen) introduces some degree of uncertainty

at the interface – there is no long range lattice, no lattice matching and there exists the

possibility that the interface can slip depending on the thermal history of the sample.

To further complicate the issue at hand, it is not clear whether any initial curvature in

the virgin wafer(s) can significantly affect the final strain state. This initial curvature

in the wafer means that only the change in curvature in the substrate will have any

meaning. The traditional way of determining whether the film has a compressive or

tensile stress by examining the curvature of the structure (e.g. for film on top: concave

≡ tensile and convex ≡ compressive) may not always be applied as will be explained

below.

For a 2 layered system with an epitaxial film on top of a crystalline substrate

with a flat substrate, a smaller lateral (in the plane of the wafer surface) lattice

constant in the freestanding film compared to the substrate will result in a concave

curvature of the substrate or a tensile strain of the film. Likewise, a film with a

freestanding lateral lattice constant larger than the substrate lattice constant will result

in a convex curvature of the substrate or a compressive strain of the film. The

 142

compressive strain refers to the biaxial (in the plane of the film) force from the

substrate pressing the film from the sides. Because the materials that are typically used

have positive Poisson ratios, the lateral force(s) cause the planes parallel to the surface

(in our case: (100) planes) to increase their interplanar distance (increasing the out-of-

plane strain).

The method of creating a single crystal SOI layer can currently take two paths:

wafer bonding and ion implantation. With oxygen ion implantation, a SIMOX

(Separation by Implantation of Oxygen) type SOI structure is created. With this

technique, the orientation of the film is still the same as that of the substrate since they

were one and the same only now separated by a layer of implant induced oxide. With

the wafer bonding approach, two different wafers are used for the substrate and the

film and this leads to complications since the donor wafer (for the film) and the

substrate will, in general, not have the same tilt/offcut orientation.

Wafer normal
Wafer normal
SOI
SiO2

Azimuthal direction

Substrate

Figure 3-21: (Leftmost figure) Cross section of the nominally oriented (001) SOI
substrate indicating the relative orientation of the (001) planes in the film and the
substrate by the direction of the diagonal lines (exaggerated). (Rightmost figure)
the azimuthal direction of rotation with respect to the wafer normal (which may
not coincide with the [001] normal of the film.
 143

Rotation of the SOI piece in the azimuthal direction with respect to the x-ray

beam will show a variety of strains from very compressive to very tensile, which

proved to be quite puzzling at first. To correct for this, the correct azimuthal and off-

normal angle must be determined (see appendix and ref. 58). To do this, a triple axis

diffractometer was used for more careful control of the sample orientation, and the

offcut for the film and the substrate are each independently corrected for. The correct

azimuthal angle was the average of two measured Bragg angles taken 180 ° apart in

the azimuthal direction, or essentially, the angle which resulted in the Bragg angle not

shifting after the sample was rotated 180 °. The respective, corrected Bragg angles for

the substrate and the film are then used to calculate the strain in the film.

The results in Table 3-4 show that the in-plane strain of the as-exfoliated

films exfoliated at 400 °C is in compression, i.e. the out-of-plane lattice spacing is

longer than that of the substrate.. After annealing the films at 1000 °C for 1 hr. in

nitrogen (the conditions used in the fabrication of the MOSFETs), the strain in films

relaxes to ~0, which is what is expected.

Table 3-4 : measured strain values of the film after correcting for the substrate
and film offcuts using a triple axis X-ray diffractometer.

As-exfoliated Annealed 1000 °C

(unannealed) 1 hr. / nitrogen
Cold cut (4.3 ± 1.0) × 10-4
~0
(250 °C) compression
Hot Cut (5.6 ± 1.0) × 10-4
~0
(450 °C) compression
 144

A triple axis x-ray diffractometer was used to measure the strain in the films. Since the

buried oxide was somewhat thick, there was the question of whether or not the zero

order peak was actually due to the handling (Si) substrate or due to the body of the

film. To be sure we were actually measuring the actual film and substrate and not just

the body of the film, it had to be confirmed that the x-rays could penetrate the 5000 Å

oxide layer. To get a better feel for this, the penetration depth of Cu-Kα x-rays

(1.540562 Å) [53, p.509] in Si can be calculated. Unfortunately, it is not a simple

matter of giving a number since the x-rays decay exponentially in the material. Rather,

it is given as a certain depth which gives a percentage of the reflection [53, p.292-5].

For silicon and Cu-Kα1 a depth of ~5000 Å will reflect 95% of the x-rays back to the

detector. From this calculation, it can be safely assumed that the entire exfoliated film

is included in the output intensity. To be sure that the handling (Si) substrate is also

seen by the x-rays (as the reference, zero order peak), a rocking curve from an

oxidized (5000 Å wet SiO2) Si wafer was obtained. The substrate peak counts were

about an order of magnitude lower than typical but the peak was still clearly seen.

From these observations, it is clear that the zero order peak is the (relaxed) Si substrate

and the first order peak is due to the film.

To calculate the strain in the film, the relation [53, p. 350-4]

(∆d/d) = - ∆θ cot (θΒ)

is used, which is derived from the differentiated form of the Bragg law, with respect to

θ. “d” is the out of plane spacing, ∆d/d is the strain (unitless), ∆θ is the angular
 145

difference between the zero and first order peaks in radians, and θB is the Bragg angle

of the substrate.

Discussion of x-ray diffraction results

Strain has been associated with thermal donor formation [54,55]. It is

important to note that the references do mention observing compressive strain in

annealed (~450 °C) H-implanted CZ Si. To explore this possibility a little further,

examination of the possible sources of this strain is necessary. From Ohring’s book

“The materials science of thin films” [56,57], a list for possible sources of strain is

presented:

1. thermal expansion mismatch

2. incorporation of atoms or chemical reactions
3. lattice spacing differences in mono-crystalline substrates and the film
during epitaxial growth
4. variation with interatomic spacing with the crystal size
5. Recrystallization processes
6. microscopic voids and special arrangements of dislocations
7. phase transformations

With thermal expansion mismatch, there are several possibilities since there are three

layers in an SOI structure and the three layers are not necessarily bonded together the

same way. The complication lies with the oxide-film interface. Since our SOI

substrates were fabricated using ion-cutting and wafer bonding, the full wafer-to wafer

bond strength is not attained until the bonded pair has been annealed at 200-300 °C.

That means the possibility exists that the interface between the bonded wafers could

slip during annealing due to the expansion of the silicon (we’ll assume the oxide does

not expand enough to make a difference as a worst case). If this was the case, then the
 146

silicon would be bonded to the oxide at a larger lattice constant (because it expanded

during the anneal) whereas the opposite surface of the silicon film would shrink back

down to the room temperature value (as the sample cooled). There would then be a

lattice constant gradient across the film and this would show up as asymmetric skew in

the first order (film) peak because the lattice constant could only be larger than the

room temperature lattice constant. Calculation shows that this skew would be around

0.05° wide and thus clearly visible using our rocking curve scan parameters. However,

there was no observed skewing of the film peak and so it is concluded that the

interface does not slip during annealing. Another way that is traditionally used to

measure strain in a film is by measuring the change in curvature of the substrate

before and after the film is bonded or deposited. Unfortunately, the initial curvatures

of the substrates were not measured before processing so no further progress was

made along this approach. In addition, having three layers (film, oxide, and substrate)

means that the traditional way of thinking of the curvature is not directly related to the

film strain. The traditional way of thinking assumed that the film was lattice matched

with the substrate and that the change in curvature of the substrate was a direct

indication of the sign of the stress in the film, e.g. with a film on top of the substrate: a

concave curvature for tensile stress and a convex curvature for compressive stress.

With a three layer structure though, it can turn out that the film is in tension even

though the substrate is curved in a convex shape. The way to reason this out is to start

from the beginning: assuming a flat Si wafer, thermal oxidation causes the wafer bow

into a convex shape due to the volume expansion of the oxide. This means that the
 147

oxide is under compressive stress and this is a well known fact. Bonding this to a flat

or slightly convex silicon wafer (which presumably has been implanted with hydrogen

so that we can exfoliate a film) [1] means that the bonded pair now becomes more flat

H implanted Si

Thermal oxide

Oxidized handle wafer

Handle wafer

(b)

(a)

Si film

oxide
(c)

Figure 3-22: (a) the hydrogen implanted wafer has a convex curvature [1], which
is bonded to a thermally oxidized silicon wafer which also has a convex curvature
due to the volume expansion of the oxide. (b) because both wafers are convex and
facing each other, the balance each other out (figure not to scale) and the wafers
are bonded in a flat state. (c) as the film is delaminated, the much thicker
oxidized substrate reverts back to it’s convex curvature stretching the film and
putting it in a state of tension even though the overall curvature is convex.
 148

again due to the compensating curvature (see fig. 3-22). The film is bonded in the

condition where the whole structure is flat. After annealing and delamination , the

oxidized wafer (to which the film is now bonded to) reverts to its convex shape and

stretches the film. So now, the film is actually in tension, even though the substrate

shows a convex shape. [58] It is clear from the results in Table 3-4 that the films,

being in compression, are not consistent with this line of reasoning. The second point

in the list is of particular interest since it is known that thermal donors form and that

they originate from the clustering of oxygen. The question is whether the growth of

these oxygen clusters catalyzed by hydrogen, ranging in size from ~3-20 oxygen

atoms, could act as inclusions and introduce strain into the silicon lattice. However, it

is also known that the formation of these oxygen clusters and platelets spawn the

formation of other defects such as silicon ribbons and other related silicon interstitials.

What makes this scenario tricky to analyze is that, while oxide precipitates and

platelets haven been directly observed via TEM to have dimensions in the range of

several nanometers thick (along the (100) plane) and up to 500 nm on a side of a

square, [59] the formation of these structures and their volume expansion also creates

silicon interstitials to relieve the strain. [1,32,33,46,47,60] The formation of the oxide

precipitates/platelets are known to nucleate from oxygen and carbon related defects

and the density of these defects are a function of what is termed “pre-annealing”. [61]

Specifically, the reported annealing cycle consisted of 2 cases: a pre-anneal at 470 °C,

a subsequent anneal at ~1000 °C, and a control case where the pre-anneal was not

performed. This annealing sequence is similar to the anneal sequence used here at
 149

UCSD for the film exfoliation and post exfoliation anneal at 1000 °C. The electron

sheet charge of the as-exfoliated films , which are 7.4 × 1011 cm-2 for the mechanically

exfoliated film (at ~250 °C) and 1.2 × 1012 cm-2 for the thermally exfoliated film (at

~450 °C), suggests that the formation of donor states was enhanced for the case with

the pre-anneal. The consequences of this will be discussed in chapter 4. Points 3, 4

and 7 refer to epitaxy, crystal size (assuming polycrystalline Si), and phase

transformations all of which either do not really apply here. However, points 5 and 6

refer to recrystallization and special arrangements of dislocations to relieve strain

which have been documented [1,32,33] and briefly discussed previously.

Höchbauer et al. [1], observed compressive stress in thermally exfoliated

silicon films as a function of H implantation dose and pointed out that the implanted

hydrogen and it’s related complexes does not contribute to the accumulated stain in

the material. Instead, it was assumed that, due to the high mobility of single vacancies

and isolated silicon self interstitials at room temperature, it was likely that these were

responsible for the buildup of the observed compressive stress in the film. There is

mutual agreement in that the silicon self interstitials, which can form as a result of

oxygen clustering of thermal donors, may play a role [46,47]. Another point which is

consistent with the idea that thermal donors are involved is the observation that the

recovered p-type conductivity (exfoliated and after annealing at 650 °C for 4 hours in

hours in nitrogen) for the cold cut films is lower than the starting concentration of the

virgin wafers. The initial concentration of holes in a p-type wafer is in the range of

1014 - 3×1015 cm-3 (5×1012 – 1.5×1014 cm-2 for a 500 µm thick Si wafer). Hydrogen
 150

implantation creates an n-type layer at the surface and the recovered concentration is

in the low 1011 cm-2 after annealing at 800 °C (4 hours in nitrogen) and mid to high

1011 cm-2 after annealing at 900 °C (4 hours in nitrogen) (see figure 3-18 and Tables of

sheet charge in the Appendix). The reduction in the hole sheet charge corresponds to a

reduced p-type conductivity. The reduced p-type conductivity is likely a result of

unquenched donor states or deep level traps from the new donors.

3.10 Discussion
The mechanically exfoliated silicon films (a.k.a. "cold cut films") from VTT

electronics (Espoo, Finland) came to UCSD as as-exfoliated films on an oxidized

silicon substrate (they used 4 inch (100) OkmeticTM wafers) diced into strips 1 cm

wide. Our collaborators at VTT electronics exfoliated these films by annealing at 250-

300 ºC for 2 hours and then inserting a razor blade (GilletteTM #5, double edged blade

(100 ± 1 µm thick)) into the gap between the bonded wafers. The cold cut films

exfoliated at VTT electronics had smoother RMS surface roughness compared to the

hot cut films (also exfoliated at VTT electronics) as shown in figure 3-24. Later in the

study, donor wafers which had been H+ implanted at Los Alamos National Laboratory

(LANL) by Dr. Jung-Kun Lee were also used. The samples from LANL required

annealing at 400 ºC for 2 hours before the film would delaminate. This was

presumably because that the wafer to wafer bond strength (bonded at UCSD) was not

as strong as that obtained in the samples from VTT Electronics in Finland. The

required bond strength should be greater than the bond strength at the implanted layer

interface. This can be seen in the figure 3-24.

 151

Cold cut, Rq ~ 4 nm Hot cut, Rq ~ 8 nm

Figure 3-23 : AFM topograph of cold cut and hot cut films. (After Henttinen et
al., Appl. Phys. Lett. (2000) ) [62]

The reason for the smaller bond strength could be due to a variety of factors but

differences in the plasma reactors (also see chapter 2) are likely to blame for the

reason that even reactors of the same type made by different manufacturers have many

variables and differences such as chamber geometry, input power and possible modes

of the plasma, chamber cleanliness, etc. The thermally exfoliated films (also known as

"hot cut films") used in this thesis were all bonded and exfoliated at VTT electronics,

Finland. From the Hall measurement data, the carrier sheet charge is plotted as a

function of depth into the films. Keep in mind that the surface of the film was

originally in the bulk of the implanted wafer and the hydrogen ions were incident from

the film side closest to the buried oxide (see figure 3-25 for schematic diagram). For

the cold cut samples, it is evident that the "etched then annealed" (EA) samples have

higher sheet charge concentrations overall compared to the "annealed then etched"

(AE) samples. To recap: the etch was done using TMAH on the ~1500 Å damaged

layer (as seen by TEM). The reason for this difference between the EA and AE is
 152

probably due to defect (trap) diffusion in the body of the film in the AE case, thereby

reducing the available carriers. At temperatures ~650 °C, the defects cannot be

Figure 3-24: Plot of effective wafer bonded surface energy as a function of anneal
temperature. The surface is the “effective” energy because the implanted
hydrogen interface is weakened and becomes weaker upon annealing. This plot
shows that the bond strength holding the film to the rest of the wafer actually
depends on the carrier concentration (Fermi level) and not the doping
concentration. (after K. Henttinen, et al, [64])

annealed out but are mobile and diffuse deeper into the film (see figure 3-13). Figure

3-27 shows a plot of the electron sheet charge for the hot cut and cold cut films. The

films were annealed at 950 °C to make them both n-type (actually to make the cold cut

film n-type, since the hot cut film never turns p-type). It is seen that the cold cut films
 153

damag
damage implantation
H+

depth
Damage region

Bonding
interface

Figure 3-25 : The implantation is done through the wafer bonded interface. The
cut depth is the region of maximum damage. There is a characteristic region of
highly damaged material is seen from TEM which is distinct from the H+
concentration profile.

have a much lower, and more non-uniform sheet charge compared to the hot cut films

(figure 3-27). This difference is only due to the difference in the exfoliation

processes. At 950 °C, one might think the point defects are being annealed out.

However, if that were the case, the cold cut film should have a similar sheet

distribution as the hot cut film. Because of this, the difference in sheet charge is not

likely to be due to the defects being annealed out but rather with new donors states

being formed from the nucleation of oxide precipitates. With that in mind, the oxide

precipitates for the hot cut film form due to a higher density of nucleation sites which

are from the higher “pre-anneal” temperature from the exfoliation temperature of ~450

°C (compared to the cold cut exfoliation temperature of ~ 250-300 °C). Oxygen is not
 154

particularly mobile until about 300 °C and so the cold cut films have much fewer

oxygen clusters (which act as the nucleation sites for the oxide precipitates) compared

to the hot cut films.

Cold cut vs. Hot cut

VTT silicon on wet thermal oxide, 950C / 4 hrs in N2
18
16
Electron sheet charge

Cold cut
14 Hot cut

12
(cm )
-2

10
11

8
x10

6
4
2
0
0 1000 2000 3000 4000 5000
Depth into Si layer (A)

Figure 3-26: Comparison of cold cut and hot cut films. They can really only be
compared in this thesis at temperatures above ~950 °C since they are opposite
conductivity types below that.

This is seen in the slopes in the damage region of the as-exfoliated films in figure 3-

18. The non-changing slope of the hot cut film indicates that there are few carriers,

presumably due to traps. The cold cut film has a larger linear slope which indicates a

uniformly doped region with fewer traps which is consistent with the lower mobility

of oxygen at the cold cut temperature (250-300 °C) forming fewer oxygen thermal
 155

donors. Another point that should not be ignored is the amount of hydrogen in and

around the damage area. This excess hydrogen (which is substantially reduced in hot

p-BESOI and n-SIMOX

carrier distribution
8

6 BESOI hole sheet charge

x 10 (cm )
carrier sheet

SIMOX elec. sheet charge

-2

4
charge

2
11

-2

-4
0 1 2 3 4
Depth into top film ( µ m)

Figure 3-27 : To see if the implantation/exfoliation damage could be singled out,

some electrical measurements were done on p-type BESOI and n-SIMOX wafers.
The resulting behavior is what was expected for implanted and non-implanted
films.

cut films since most of it probably turns into H2 gas…) can either form electron traps

[26] or diffuse out (more likely once the film has been delaminated. Another

possible, but not probable, reason would include contamination from the stainless steel

razor blades used to delaminate the cold cut films. However, the hot cut films are n-

type and they did not touch the blade at all. To dig a little further and see if

implantation or delamination damage, electrical depth profiles of BESOI and

 156

SIMOX wafers were done. BESOI stands for Bonded and Etch back, SOI. The wafers

are not implanted, but are bonded with a thermal oxide layer between them and one

wafer is lapped and chemically etched almost all the way down. With SIMOX

(Separation by IMplantation of OXygen), a wafer is implanted with a high dose of

oxygen and annealed at high temperatures to form a buried oxide layer. Unfortunately,

these wafers are expensive and I was only able to obtain a p-type BESOI and n-type

SIMOX wafer for testing. The BESOI wafer characteristics were as expected, a linear

sheet charge profile showing uniform doping throughout the wafer. With SIMOX, the

the sheet charge profile increases with increasing depth into the film. The profiles are

smooth, unlike some of the profiles measured for the exfoliated films shown earlier. It

was not known whether the film layer of the BESOI was from CZ Si or not. However,

the results suggest that due to the lack of hydrogen in the material, there are no

extraneous donor states (no upward trend or carrier sheet charge with increasing

depth) where SIMOX wafers are annealed at high temperature for many hours to

repair the ion implant induced damage. This extended high temperature anneal is

consistent with the formation of donor states in the literature.

3.11 Summary and conclusions:

The electrical depth characterization of the BESOI and SIMOX wafers behave

as expected and are consistent with the general behavior of the exfoliated films. This

gives us confidence that the processes and measurement techniques used are valid and

consistent. The quartz annealing tube was also measured using an undoped piece of
 157

silicon to see if there was contamination in the tube that was causing the results to

skew. No significant dopants were detected using Hall effect measurements of the

undoped samples before and after annealing. What these measurements do tell us is

that there is a difference in the electrical properties between the cold cut and hot cut

films. Physical evidence that could explain these differences are hard to come by, and

the focus turns mainly to chemical differences that are “activated” by the difference in

process temperatures between the hot cut (~450 °C) and cold cut (~250 °C) films.

Oxygen thermal donors enhanced by the implanted hydrogen, are the likely culprit for

these differences after annealing at 650 °C. Silicon films on glass samples have been

demonstrated and electrically characterized using PIII and the usual single ion

implantation. To extend our studies to higher temperatures, glass could not be used

due to its relatively low strain point and so thermally oxidized silicon substrates were

used. What is found is that the cold cut films have a lower sheet charge compared to

the hot cut films when they are compared after annealing at 950 °C (so they are both

n-type). This is presumably due to the fact that there are fewer thermal donor states

formed due to lack of oxygen mobility since the films are cut after annealing at only

250-300 °C. At lower anneal temperatures, the films are not directly comparable due

to differing conductivity types. These studies will for the basis for the differences

encountered in the MOSFETs fabricated from these SOI films in the next chapter.
 158

3.12 References

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[6] Paul Chu, City University of Hong Kong, Dept. of Physics and Materials
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[8] Chu PK, Cheung NW. Microcavity engineering by plasma immersion ion
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[9] Chu PK, Chung Chan, Cheung NW. Recent applications of plasma immersion
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[10] P. K. Chu, S. Qin, C. Chan, N. W. Cheung, and L. A. Larson, Plasma

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 161

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Chapter 4: Fabrication and characterization of
MOSFETS.

4.1 Background

The Metal-Oxide-Semiconductor Field Effect transistor (MOSFET) is the most

important semiconductor device to date. Its relatively simple structure allows it to be

both practically and analytically understood and scaled down to dimensions

approaching "physical limits", or so as one might have been led to believe over the last

decade. The "M-O-S" describes the cross sectional structure of the device, metal (for

the contact pads) on top of the gate oxide layer (which serves as passivating as well as

an insulating layer), and the semiconductor, which more often than not is silicon. The

"F-E-T" describes the method of operation of this transistor: it operates on the ability

of the metal contact to apply a bias voltage across the insulating oxide, pulling up

mobile carriers which then form a conducting layer between the source and drain

regions. This control of the conductance of the channel between the source and drain

is what allows the transistor to turn "on" and "off". The “source” and “drain” are the

regions doped opposite to that of the substrate and form the connecting ends of the

channel. When the channel is present, current is allowed to flow from the drain to the

source (named “source” because it is typically grounded and thus is a source of

electrons – which move opposite to the hole (conventional) current).

The physics involved in the formation of the channel basically determine how

the MOSFET will behave and function. Factors such as ions in the oxide, substrate

163
 164

bias and geometry all affect the electrical properties. These will not be discussed in

detail since they can be found in numerous other texts.

metal
SiO2
++++++
------
p p

n-Si
(a)

metal
SiO2
------
++++++
p p

n-Si
(b)

Figure 4-1: (a) p-channel MOSFET with a positive gate bias produces no channel
between the source and drain (dark gray regions). (b) negative gate bias produces
a conducting channel between the source and drain. If a bias is now applied
between the source and drain, a current can flow.

4.1.1 Electrical characterization

MOSFETs are commonly characterized by their current-voltage (I-V) and

capacitance-voltage (C-V) properties. However, with the introduction of the buried

 165

oxide layer of the SOI structure, C-V measurements would require a more

sophisticated analysis. Therefore, only I-V measurements are taken in this thesis.

I-V curves

Current-Voltage curves are typically what are used to characterize MOSFETs

(not to mention just about all other semiconductor devices). There are two types that

will be used here: ID-Vds and ID-Vgs plots. The former is geared more towards

examination of the higher current and associated properties whereas the latter is

geared towards examination of low currents such as leakage, on-off ratios, and

subthreshold properties. The general trend is shown in the figures below:

1
Vg = 2v
0.8 Vg = 4v
Vg = 6v
Ids (mA)

0.6 Vg = 8v
Vg = 10v

0.4

0.2

0
0 2 4 6 8 10
Vds (V)

Figure 4-2 : example MOSFET drain to source current as a function of drain to

source potential bias and gate to source bias. The sloped region is referred to as
the linear region, and the flat (horizontal) part is referred to as the saturation
region.
 166

Log (Ids) Subthreshold slope

Leakage current level

Vgs

Figure 4-3 : MOSFET drain to source current as a function of gate to source

potential bias for a fixed drain to source potential bias. Note that the y-axis is a
log scale. The level at which the current settles is the base leakage current (off
state current). The subthreshold slope determines how quickly the device can
turn on or off and is measured as a certain number of millivolts per decade of
current.

The subthreshold slope indicates the sharpness of the on-off current transition. The

subthreshold swing, S ≡ 1/(subthreshold slope) is defined as the swing in the gate

voltage needed to reduce the current by one decade and has a minimum value of 60

mV/decade of current at room temperature. [1]

Square law description

The square law description (“square” because it has a quadratic dependence)

provides an easy and accurate way to quantify the MOSFET Id-Vds characteristics. For

the linear region:

 167

ID = ( WµCox / 2L ) [ 2( Vgs – VT ) Vds – Vds2 ]

and for the saturation region:

ID = ( WµCox / 2L ) ( Vgs – VT )2
where ID = IDS (subscripts are case insensitive) is the current flowing from the drain to

the source, W is the channel width, µ is the carrier mobility, Cox is the oxide

capacitance, L is the channel length, Vgs is the gate to source bias, and VT is the

threshold voltage. These equations give a useful description in terms of simplicity and

accuracy. There are higher order terms for additional precision which come into play

under the appropriate conditions and requirements, but these will not be discussed

here.

4.1.2 Mobility

Qualitatively, mobility is a measure of how easy it is for a carrier to move in a

lattice environment. A lattice with defects can reduce the mobility due to various

scattering effects. More quantitatively, mobility is the proportionality constant

between the velocity of the particle and the applied electric field. It is typically given

in units of cm2/V.s and in bulk silicon, where electrons have values in the range of

1500 cm2/V.s and holes in the range of 450 cm2/V.s. [2] In a MOSFET channel, the

dimensions of the narrow channel increase surface scattering and under strong

inversion, the large number of carriers can reduce the mobility. Mobility can be

extracted from the Hall effect measurements as

 168

µH = |RH| / ρ
[3], where RH is the Hall coefficient and ρ is the resistivity. The Hall mobility is not

the same as the conductivity mobility which is given as :

µp = 1/(q·p·ρ)

for p-type semiconductors [4], where q is the electronic charge and p is the doping

concentration. The difference between the two mobilities are usually ignored because

it is small. The relation between the Hall mobility and the conductivity mobility is a

scattering coefficient:

µH = r · µp

where ' r ' is a scattering factor that lies between 1 and 2 depending on the scattering

mechanism [5]. For lattice scattering, r = 3π/8=1.18, for ionized impurity scattering r

= 315π/512=1.93 and for neutral impurity scattering, r =1.00. [5-7]

Mobility Extraction

By plotting channel conductance or transconductance vs. Gate bias (Vgs), a

linear equation from the respective expressions can be fit to the experimental data and

a mobility extracted from the slope of the fitted line. There are three main types of

mobility for the MOSFET. There is “effective mobility” (µeff), which is calculated

from the channel conductance at low drain voltages and fixed gate bias; “field effect

mobility” (µFE), which is calculated from the transconductance in the linear region
 169

with a fixed drain-source voltage; and “saturation mobility” (µsat), which can be

calculated from the saturation drain current. [8] The field effect mobility is easier to

calculate and has less variation with common parameters and so it is the most popular

one to use and the one used here.

Overall, the end product is that the TFT drivers should have a sufficiently large

mobility so that large currents can be available to charge up and discharge the holding

capacitors that will sustain the light emitting element for the desired duration. It was

shown in chapters 1 and 3 that ~100 cm2/V·s is more than sufficient, and that the

measured Hall mobilities are greater than ~100 cm2/V·s, so it is expected that the

effective mobility will also be sufficiently large.

4.1.3 Leakage current measurement

The drain-source leakage is directly proportional to the gate width. This is true

because the larger the width, the more "parallel" channels are potentially available.

Therefore, to get a good measurement, a large area MOSFET (gate width = 128 µm) is

used. This magnifies the leakage current and avoids the problem of running into the

limits of the HP 4155B semiconductor parameter analyzer used for this measurement.

To make sure that the leakage currents measured are actually currents passing from

source to drain and not some artifact of noise or the measurement setup, certain

guidelines have to be followed [9] : The measurement limits are dictated mainly by the

connections used. The general set up is the HP4155B connected via tri-axial cable to a
 170

probe station box made of metal, is grounded and shielded from light as much as

possible (see figure 4-4).

Figure 4-4 : diagram showing preferred setup for low current probing. The box
should be light tight and grounded, effectively serving as a radiation shield. (after
HP 4155B/4156B Semiconductor Parameter Analyzer, Product Note-3 Prober
Connection Guide, Hewlett-Packard)

The triaxial cables are usually converted to coaxial cables via a connection panel on

the side of the probe station box. The coaxial cables are then directly connected the

probes which then contact the MOSFET pads. The connection between the tri-axial

and coaxial cables are extremely important. The triaxial cables have an extra shield
 171

between the sensing probe ( the signal wire) and the outer most (grounded) shield.

This extra, intermediate shield is called the "guard". The guard is biased to the same

potential as the sense cable by a unity gain amplifier in the 4155B. Since the guard and

the sense are at the same potential, no current can flow between them and current

leakage is minimized. It is important that when connecting the tri-axial probe to the

Figure 4-5: example of how to connect triaxial cable to probe box interlock
connection to coaxial cable inside the probe box. This provides maximum
sensitivity for low current measurements. (after HP 4155B/4156B Semiconductor
Parameter Analyzer, Product Note-3 Prober Connection Guide, Hewlett-
Packard)
 172

Open circuit leakage as measured by

4155B in ITL using triaxial-coaxial-probe
connection with floating ground
1E-10
short integration time (640us)
"measured" current

1E-11 medium integration time (20.0 ms)

long integration time (320 ms)
1E-12
(A)

1E-13

1E-14

1E-15
-5 0 5 10
Bias (V)

Figure 4-6: Noise floor for the HP4155B semiconductor parameter analyzer. The
connector configuration used was tri-axial guard connect to the co-axial shield.
The short integration time was the setting used in the measurements. It has the
largest spread but fastest measurement time. As it turned out, it doesn’t matter
which setting was used for the measurements here since the currents were all
greater than 1 pA.

coaxial probe, the guard is connected to the outer shield of the coaxial cable (inside

the probe station box). With this configuration, the resolution of the measurement is

about 10 fA (10-15 amps) in the best case. Connecting the ground of the triaxial to the

ground of the coaxial limits the resolution to about 1 nA and using other types of non-

shielded cables worsens the resolution.

 173

4.2 Silicon on insulator (SOI) structures for devices

The semiconductor on insulator structure has been carefully examined and

studied for a number of years and there are at least several texts worth mentioning.

[10] For the silicon on glass or the silicon on oxidized silicon substrate structures, the

top layer of silicon is on top of an insulating substrate, as the name implies. This has

important consequences for the electronic properties. For a device fabricated from an

SOI structure or wafer, the insulating layer can be used to isolate the devices from

each other effective providing shielding from cross-talk. This is commonly used for

space electronics and is called "radiation hardening" or “radiation resistant”. In bulk

Si, the substrate constitutes the dominant volume of the semiconductor material the

device sit on. With energetic particles flying around (the “radiation”), they impact the

semiconductor and leave a trail of electrons and holes in the path. These extra carriers

can then diffuse all throughout the substrate (since it is semiconducting) and create

havoc with the devices causing shorts, errors, etc. With SOI, the semiconducting

material thickness is kept to a minimum, just enough for operation of the device, and

so energetic particles that enter the region can only create a minimal number of extra

carriers. This is what makes the SOI structures "radiation resistant". However, there

are other complications to deal with which are centered around the main feature of the

SOI structure. The isolation provided by the buried oxide also creates a free floating

film (with no fixed electrical reference, i.e. no sourcing/sinking of carriers). This leads

to charging of the film under certain conditions which is seen as the kink effect – part

of the floating body effect family in TFTs. The oxide on the bottom can also act as a
 174

second gate depending on how the substrate is biased or charged (possibly by

impurities which are close to the interface, such as sodium).

The kink effect is seen as a step or kink in the ID – Vds characteristics (see

figure 4-7). This is explained by a sudden shift in the threshold voltage which is

caused by a bias change to the film.

Ids
kink

Vg3
Vg2
Vg1

Vds
Figure 4-7 : Illustration of the kink effect.

The bias change is the result of a build up of charge due to impact ionization (from

large drain-source bias) in the film. Since the charge has no place to go (because the

film is floating), it changes the potential of the film. The coefficient of pair generation

by energetic holes is much lower than that of pair generation by energetic electrons.

Because of this, p-channel SOI MOSFETs are usually free of the kink effect. [10, p.

159] The kink effect is not observed in bulk Si because the carriers generated by

impact ionization can escape into the substrate or well contact. The biasing of the film
 175

can also cause an anomalous sub-threshold shift which can reduce the slope from it’s

theoretical minimum value of 60 mV/decade at room temperature. [10, p.159] Further

discussion of these and other artifacts associated with the SOI structure can be found

in Jean-Pierre Colinge’s book, Silicon-on-insulator Technology: Materials to VLSI.

[10]

4.2.1 Effect of film thickness

The thickness of the silicon layer determines the properties of the layer to a

large degree. The reason why the thickness makes a difference is basically due to the

effect of the surface potential(s) on the band edges. The gate oxide induces band

A B C
Ec Ec
Ec

Ef Ef Ef

Ev Ev Ev

Gate oxide Front Back Back

Front
gate gate gate
gate
oxide oxide oxide
oxide

Figure 4-8 : Band diagram in bulk (A), a thick-film SOI (B), and a thin-film SOI
device (C). All devices are represented at threshold (front gate voltage =
threshold voltage). The shaded areas represent the depleted zones. SOI devices
are represented for a condition of weak inversion (below threshold) at the back
interface. [After ref. 10, pp. 126]
 176

bending at the front surface and the buried oxide layer that the silicon sits atop of

induces band bending from the "bottom". If the film is very thin, the bending effects

will reach each other and fully deplete the film. This is not unlike what happens at

punch-through conditions. The maximum depletion width is reached at strong

inversion or the threshold condition and the expression is given by [2, page 373; and

10, 1st Ed., page 109]:

xdmax = [( 4 εSi . ΦF ) / (q . Na) ]½

where ΦF is the Fermi potential which is

ΦF = (kT/q) . ln(Na/ni)

and εSi is the permittivity of silicon, k is Boltzman’s constant, q is the electronic

charge, Na is the doping concentration and ni is the intrinsic carrier concentration.

Note that some texts will write the xdmax as [(2 εSi . ΦF) / (q.Na) ]½ and the ΦF as

2(kT/q).ln(Na/ni) to remain consistent with previous notation.

 177

Partially depleted → fully depleted film

transition for silicon
1.E+01
-100 °C
Room Temp.
depletion width (µm)

100 °C
1.E+00 300 °C

0.20 µm
0.14 µm
1.E-01

1.E-02
1.E+14 1.E+15 1.E+16 1.E+17
doping concentration (cm-3)
Figure 4-9: Calculation of depletion width due to the doping level. After
annealing to ~1000 °C the electron concentration is in mid 1016 cm-3. This gives a
range of 0.14-0.20 µm for the space charge region under the front gate. The
depletion width is only a slow function of temperature.

4.2.2 Partially vs Fully depleted TFTs

If the depletion regions do not completely enclose the body of the FET (leaves

a neutral region), the FET is considered to be partially depleted. However, if the film

is thin enough, the whole layer is enclosed in the space charge region and the FET is

considered fully depleted. The implications of fully depleted and partially depleted

MOSFETs are essentially operational simplicity vs. enhanced performance. The fully
 178

depleted MOSFET allows larger current densities, sharper subthreshold slopes and

have immunity to the kink effect but at the cost of being more sensitive to front and

back gate coupling.

4.3 Background summary

MOSFETs and its basic mechanics have been presented. The basic operational

modes have been quantified by the first order square law description which is

sufficient for extracting transistor parameters such as mobility and transconductance.

Other parameters such as drain-source leakage and subthreshold swing are not so

easily calculated and have to be measured. The optimal conditions for the

measurements have been described using the HP4155B semiconductor parameter

analyzer along with the requisite connections for low current measurements. Finally, a

brief introduction to the properties of thin film MOSFETs has been described and the

pros and cons reviewed. The following sections will cover the fabrication details and

the results of the electrical measurements.

4.4 Experimental details

To isolate the properties of the films and not have them convoluted with

properties of low temperature oxides, process conditions, or possible unknown

contaminants from glass, the MOSFETs will be fabricated using the exfoliated films

on wet thermal oxidized silicon substrates, a dry thermal oxide as the gate oxide and

boron diffused wells for the source and drain regions. This means that the films will be

annealed at temperatures in the range of 900-1000 ºC which will anneal out physical
 179

defects associated with damage from the ion implantation. This basically leaves

chemically oriented defects such as the thermal donors.

4.4.1 SOI MOSFETs (hot cut and cold cut samples)

The as-exfoliated silicon films started as 5000 Å thick films. After etching off

the damage layer, and thermally growing the field and gate oxide (which consumes

another 1500 Å of silicon), the final thickness was ~2000 Å. The final structure had a

500 Å (dry) gate oxide, and a ~2000 Å exfoliated silicon film, on top of a substrate

which consisted of 5000 Å wet thermal oxide on a silicon substrate (figure 4-10).

MOSFETs with 38 µm gate lengths and 128 µm gate widths (figure 4-11) were

processed using thermally grown wet and dry oxides at temperatures as high as 1000

°C for diffusion masking and gate oxides. The source-drain doping was done with a

boron

1000 Å Al
source

500 Å gate oxide

drain
gate

2000-2500 Å
5000 Å Wet thermal oxide

400-500 µm
Si handle wafer

Figure 4-10 : Final structure of the p-MOSFET.

 180

Figure 4-11a: Optical micrograph of the final MOSFET. Shown are the
aluminum contact pads for the source, drain and gate. The smaller squares are
the windows through the gate oxide through which the metal contacts the doped
silicon.

38 microns
microns
128

Figure 4-11b: Optical micrograph of the channel area of the MOSFET. The gate
length is 38 µm and the gate width is 128 µm.

nitride source from PDS products® (Saint-Gobain advanced ceramics). A 5 minute

predep and 5 minute drive-in process (both at 1000 °C) was utilized so as to minimize

diffusion into the buried oxide. Finally, aluminum contacts were evaporated onto the

source, drain and gate areas and annealed at 450 °C in nitrogen.

 181

4.4.2 Conductivity conversion

Recall that the starting wafers were p-type CZ (100) prime grade wafers. After

hydrogen implantation, the presence of hydrogen was able to catalyze the formation of

oxygen thermal donors, new thermal donors and new donors as well as the

complementary oxide precipitates and silicon interstitial related defects. The donor

states turned the sample n-type due to the overwhelming number of oxygen intersitials

present. It was roughly calculated that even with oxygen cluster sizes of up to 20

oxygen atoms/cluster, the n-type doping concentration was at least 1016 cm-3 compared

to the starting p-type concentration of ~1×1015 cm-3. After annealing at 650 °C (this

temperature was used because a lot of silicon on glass samples were annealed at this

temperature also) for 4 hours in nitrogen, the cold cut films turned back to being p-

type but the hot cut films did not. The hot cut films were highly resistive after

annealing at temperatures from ~500 – 650 °C, and were n-type from 650 – 1050 °C.

Higher temperatures were not used due to equipment limitations (quartz tube starts to

soften at higher temperatures). It is believed that this n-type doping was due to new

thermal donors or new donors since they become active at high temperatures. It also

turned out that the cold cut film turned n-type at anneal temperatures above about 920

°C. This coincidence made the comparison between hot cut and cold cut more direct.

So instead of the initial expectation that n-MOSFETs were going to be fabricated and

compared, it turned out that p-MOSFETs were what would be created.

 182

4.4.3 Process conditions

The fabrication was similar to the fabrication of a MOSFET on bulk silicon,

however there were a few issues which had to be noted. Perhaps the foremost

problem was to carefully keep track of how much silicon was being used in the film to

create the diffusion mask oxide and the gate oxide. With bulk silicon, this is not a

problem due to the very thick substrate. The parameters involved were essentially the

depth of the source and drain p-wells and the thickness of the masking oxide grown at

a particular temperature. There was also the difficulty of determining if the doping

profile was uniform. Because the quartz wafer holder was designed to hold 300 µm, 2”

wafers, the 1 cm × 1 cm × 500 µm piece could not be placed in the recommended

position about 1-2 mm next to the boron nitride (BN) source wafers for doping.

Instead, small pieces were laid flat or at an angle facing the BN wafers but about 1 cm

away.

4.5 Results and discussion

The Ids-Vds curves for the hot cut, cold cut and bulk Si p-MOSFETs are shown

below in figures 4-12a-c. The curves look like the standard I-V curves expected for a

MOSFET and are all similar. The current reaches ~1 mA at a drain bias of 5-6 volts

and a gate bias of 10, 11 and 14 volts for the cold cut, hot cut and bulk Si devices

respectively. From these curves, the field effect mobility, the transconductance and the

threshold voltage are extracted and summarized in Table 4-1. Figures 4-13 a-c depict

the Ids-Vgs curves which give information on the off-state drain-source leakage current
 183

p-MOSFET on hot cut silicon film

1.2
Vg=12v
Drain-source current
0.8
(mA) Vg=10

0.4 Vg=8v

Vg=6v
0 Vg=4v

0 2 4 6 8 10
Drain-source bias (V)

Figure 4-12a : ID-Vds plots for p-MOSFET fabricated on hot cut Si.

p-MOSFET on cold cut silicon

1.2 Vg=11
Drain-source

Vg=10
current (mA)

0.8
Vg=9
Vg=8v
0.4 Vg=7v
Vg=6v
Vg=5
0
0 2 4 6 8 10
Drain-source bias (V)

Figure 4-12b : ID-Vds plots for p-MOSFET fabricated on cold cut Si.
 184

p-MOSFET on bulk n-Si

1.5
Vg=14v
Drain-source current (mA)

Vg=12v
1.0

Vg=10v
0.5
Vg=8v
Vg=6v
0.0 Vg=4v
0 2 4 6 8 10
Drain-source bias (V)

Figure 4-12c : ID-Vds plots for p-MOSFET fabricated on bulk Si.

and subthreshold swing. There are several plots for each of the film types indicating

the sensitivity of the device to differing biasing conditions of the film body. The main

differences are whether the film body was floating, grounded or biased. For all cases,

the turn on voltages were very close to each other indicating that the fabrication

process was consistent and no obvious problems were at hand. Also note that the

current at turn-on rises up to just shy of ~0.1 mA which is higher than similar

polysilicon TFTs (figure 4-14). [11]

The FET fabricated on the hot cut film shown in figure 4-13a shows that the

lowest leakage current is obtained for drain and body biased at –2.5 volts and the

source grounded. The leakage current profile, however, was noisy resulting in what

almost seems like two separate plots.

 185

P-FET Hot cut film from VTT

1.E-04
Vds=-2.5v, Vbs=-2.5v
1.E-05 Vds=-5v, Vbs=-5v
Vds=-5v, Vbs=float
1.E-06
Vds=-5v, Vbs=-5v
drain current (A)

1.E-07

1.E-08

1.E-09

1.E-10

1.E-11

1.E-12
-5 -3 -1 1 3 5 7 9
Gate bias (V)

Figure 4-13a : p-MOSFET fabricated on hot cut silicon. The different biasing
conditions all gave similar curves as shown.

In figure 4-13b, the FET on the cold cut film characteristics show a wide range of

variation for the various biasing conditions. This device had the lowest yield of about

20% and was the most sensitive to any change in the film body potential. However,

the bias which gave the optimum conditions were again the body and drain biased at –

2.5 volts. This condition also resulted in the sharpest on-off transition and the largest

current magnitude. For the bulk Si p-MOSFET, the I-V displayed no noticeable

change for the varying bias conditions.

The transistor parameters extracted from these I-V plots are also summarized

in Table 4-1. The leakage current is given per unit width (128 µm gate width) to make

it easy to compare to other FETs. The cold cut device had the lowest drain to source

leakage current with ~0.6 pA/µm. This was even lower than the bulk Si device and is
 186

P-FET Cold cut film from VTT

1.E-04 Vds=-5v, Vbs=-5v

1.E-05 Vds=-2.5v, Vbs=-2.5v

Vds=-2.5v, Vbs=0
1.E-06 Vds=-5v, Vbs=0
drain current (A)

1.E-07 Vds=-2.5v, Vbs=float

1.E-08

1.E-09

1.E-10

1.E-11

1.E-12
-5 -3 -1 1 3 5 7 9
gate bias (V)

Figure 4-13b : p-MOSFET fabricated on cold cut silicon ID-Vgs characteristics.

The different biasing conditions resulted in the widest variation of
characteristics.

likely due to the smaller leakage through the thin film. However, this also means that

the hot cut film, due to it’s relatively large leakage current of 10 pA/µm, after it was

processed, possesses a very large number of defects that act as carrier generation sites.

This leads us back to the idea that the differences in the films are caused by defects

which are thermally activated and depend on the thermal history – new donors.

The transconductance is the change in (drain-source) current with a change in

the gate bias. It is a conductance because it follows the traditional definition of ∆I/∆V,

but because the gate bias acts indirectly on the amount of current, it is a “trans”-

conductance. It is essentially a measure of how readily the channel under

 187

P-FET bulk Si
1.E-04

1.E-05 Vds=-2.5v, Vbs=-2.5v

Vds=-1v, Vbs=0
1.E-06
Vds=-2.5v, Vbs=0
drain current (A)

1.E-07 Vds=-5v, Vbs=0

1.E-08

1.E-09

1.E-10

1.E-11

1.E-12
-5 -3 -1 1 3 5 7 9
gate bias (V)

Figure 4-13c : p-MOSFET fabricated on bulk Si. The gate oxide was 1000 Å
thick. The biasing conditions didn’t affect the I-V characteristics much if any.

the gate oxide can be formed. For both films, the transconductances are very close but

the bulk Si FET has the highest value whereas the cold cut FET has the lowest value.

This can be interpreted as defects or damage due to the implantation/exfoliation

process slightly hindering the formation of the channel.

Overall, the cold cut FET has the lowest leakage current, transconductance,

mobility and subthreshold swing. Out of these four parameters, low leakage and low

subthreshold swing are highly desirable characteristics while the other parameters are

sufficiently close to the hot cut and bulk Si or are sufficiently high for the intended

application.
 188

-6
1x10
-7 TE device
1x10
ME device
per gate width (A/µm)

-8 Bulk Device
Drain-Source current

1x10
-9 TE
1x10
-10
1x10
-11
10
ME
-12
10
-13 BULK
10
-4 -2 0 2 4 6 8 10 12
Gate-Source bias (V)

Figure 4-13d: Plot of Ids-Vgs in the off and turn-on states for TE, ME and bulk p-
MOSFETs with Vds = 2.5 volts. The bulk p-MOSFET had the same lateral
geometry as the SOI MOSFETs but differed in oxide thickness (~500 Å for SOI
MOSFET vs. ~1000 Å for bulk MOSFET) and starting p-type doping
concentration (~1015 cm-3 for bulk MOSFET and ~1016 cm-3 for SOI MOSFETs)
so they may not be directly comparable.
 189

Figure 4-14: Plot of n-channel polysilicon TFT off-state leakage and turn-on
characteristics for conventional (conv.) polySi and increased grain size (new)
polySi films. The inset shows the effective electron mobility as a function of gate
bias. [after J-H Jeon et al., (2001), 11]
 190

Table 4-1: Summary of MOSFET characteristics for hot cut, cold cut and bulk
Si. The mobility listed is the field effect mobility. (W/L = 128/38)

TE ME Bulk
SOI SOI Si

Leakage ( pA/ µ m) 10 0.6 0.6

Transconductance
54 52 55
µ S @ -4.8 v
2 .
Mobility (cm /V s) 100 91 190

Subthreshold swing
150 120 120
( mV/decade) @ -3 v

Threshold Voltage (V) -3.2 -2.9 -2.5

I on / I off ratio
5 6 6
~10 ~10 ~10
@V d =0 v

I on / I off ratio
4 6 6
~10 ~10 ~10
@V d =-5 v
 191

4.6 Discussion

4.6.1 Hot cut devices vs cold cut devices

To examine the off-state, drain-source leakage current without all the different

biasing conditions, one case will be examined in figure 4-13d. The measurement

conditions here are Vds = 2.5 v, and the vertical axis is already normalized to the gate

width. It is clear that the TE (hot cut) device has a substantially large leakage current

which increases quickly with increasing positive gate bias. In contrast, the ME (cold

cut) device close resembles that of the bulk Si device which should have the fewest

defects and contaminants (most notably hydrogen). This case shows that by keeping

the exfoliation temperature low (< ~300 °C), even with the introduction of hydrogen

which enhances the formation rate of the donor states and the high temperature

processing at 1000 °C, the quality of the material can be maintained, similar to that of

bulk Si. This is corroborated by a report by E.B. Yakimov [14] who connects the

dependence of the formation of new thermal donors on a “pre-anneal” at ~470 °C.

This temperature is very close to the exfoliation temperature of the hot cut films used

in this thesis.
 192

Figure 4-15 : I-V characteristic for amorphous silicon TFT (after MIT 6.976:
Special topics in flat panel display devices, lecture 16, Spring 2001)

4.7 Summary and conclusions

For flat panel display applications, as noted in chapter 1, it was determined that

~100 cm2/V.s channel mobility was more than sufficient to obtain the required current

for controlling the light emitting element to meet a threshold brightness. With values

of 100 and 91 cm2/V.s for the hot and cold cut devices, this requirement is readily met.

MOSFETs fabricated on amorphous silicon films have mobilities less than or about 1-
 193

10 cm2/V.s. The best values for hole mobility for poly-silicon TFTs reported in the

literature are in the range of 120-180 cm2/V.s, [12, 13] While this may seem

significant, drawbacks to the devices are also significant – the leakage current for the

TFT with the high mobility had a leakage current of roughly 2 × 10-8 A, which is

roughly an order of magnitude higher than the leakage current from the hot cut devices

measured. Effectively, the cold cut MOSFET seems to have the best tradeoff

between the critical parameters while still basically meeting and sometimes exceeding

the required attributes. The closest contenders are apparently devices fabricated on

amorphous silicon. Just by glancing at the plot in figure 4-15 the off state leakage

current is astonishingly low, but the corresponding mobility for amorphous Si is also

exceedingly low!

SOI p-MOSFETs fabricated on thermally and mechanically exfoliated films

were characterized using the standard current voltage technique and the results

compared to similarly fabricated polysilicon and amorphous silicon MOSFETs. It was

shown that using mechanically exfoliated single crystal silicon films instead of

thermally exfoliated single crystal silicon, polysilicon or amorphous films allowed the

best tradeoff between hole mobility, off state leakage current and maximum current

swing while still meeting required “specifications” for high performance TFT flat

panel displays as given in chapter 1. The difference between the devices fabricated on

the thermally and mechanically exfoliated films is apparent and discussed in terms of

oxygen related thermal donors, new thermal donors and new donors and how these are

nucleated as a function of the thermal history of the film. Based on these reports, the
 194

difference between the devices stems from the “additional” anneal necessary to

exfoliated the hot cut film.

 195

4.8 References:

[1] Sorin Cristoloveanu, Sheng S. Li, Electrical characterization of silicon-on-

insulator materials and devices, Kluwer 1995, pp. 250.

[2] S.M. Sze, Physics of semiconductor devices, 2nd ed., Wiley, New York, 1981,
pp.851.

[3] D. Schroeder, Semiconductor Material and device characterization, Wiley

1990, p. 200.

[4] ibid, p. 195.

[5] ibid, p. 73.

[6] S.M. Sze, Physics of semiconductor devices, 2nd ed., Wiley, New York, 1981,
pp.256-63.

[7] Y.P. Song, R.L. Van Meirhaeghe, W.H. Laflere, and F. Cardon, Solid-State
Electron. 29, 633-38, June 1986.

[8] D. Schroeder, Semiconductor Material and device characterization, Wiley

1990, pp. 226-31.

[9] Personal communication: Alson Wong, Agilent, Colorado, May, 2003

[10] Jean-Pierre Colinge, Silicon-on-insulator technology: Materials to VLSI, 2nd

Ed., Kluwer Academic publishers, 1997; Sorin Cristoloveanu, Sheng S. Li;
Electrical characterization of silicon-on-insulator materials and devices;
Kluwer academic publishers, 1995.

[11] Jae-Hong Jeon, Min-Cheol Lee, Kee-Chan Park, and Min-Koo Han, A New
Polycrystalline Silicon TFT With a Single Grain Boundary in the Channel,
IEEE Electron Device Letters, Vol. 22, No. 9, 2001, pp.429-31

[12] Ucjikoga, S. Low-temperature polycrystalline silicon thin-film transistor

technologies for system-on-glass displays. MRS Bull. 27, 881-886 (2002)

[13] Mizuno, T., Sugiyama, N., Kurobe, A. & Takagi, S. IEEE Trans. Electron
Devices 48, 1612-1618 (2001).

[14] E.B. Yakimov, O.V. Feklisova, M. Acciarri, A. Cavallini, S. Pizzini, Solid

State Phenomena Vols. 69-70 (1999), pp.327-332.
Chapter 5: Summary, conclusions and suggestions for
continued research
Chapter 1 defined the somewhat arbitrary requirements for high end flat panel

displays using organic LEDs. The requirements were based on current top of the line

models and then extended some within reason. The end goal is to have a bright, high

resolution screen which has the capability to clearly display full motion video. While

the geometry of this screen this can be scaled up or down, the main application the

requirements were designed for were portable notebook type computers. Active matrix

addressing was targeted even though it was more costly and complex to design and

manufacture because of its inherent advantages and flexibility. The transistor drivers

will more than likely be staggered (more than 1 TFT per pixel) for superior control of

the injected current profile, thus relaxing the mobility requirement. Nevertheless, a

high but still reasonable value of 100 cm2/V.s was the target mobility to design for.

Because the display is among the largest consumers of power in a portable computing

system, OLEDs were chosen because of its inherent and apparent power efficiency

compared to liquid crystal light valve type displays. On top of this, the off-state

leakage currents in the transistor drivers must be minimized to extend the battery life.

By using nominally single crystal films instead of polycrystalline films, this feature is

inherently implemented. To be able to lay down a single crystal silicon layer on an

amorphous substrate requires the use of wafer bonding techniques which is the topic

of discussion in chapter 2.

Wafer bonding is a necessary but not sufficient condition for creating a high

quality SOI structure for FPD applications. This is because FPD applications require

196
 197

the use of glass as a backplane substrate. The glass can be one of several boro-

aluminosilicates designed with thermal expansion coefficients close to that of silicon.

The current technology only allows temperatures of up to 666 °C before the glass

begins to soften and so traditional wafer bonding techniques which require

temperatures of up to 1000 °C, have to be improved. This bonding enhancement is

possible through the use of plasma activation of the to-be-bonded surfaces which

allows bonds approaching the fracture strength of Si at relatively low temperatures of

200-400 °C. The exact mechanism for the plasma activation is not known but through

a variety of experiments and observations, a plausible model has been proposed. The

model is centered around the action of the plasma(s) and the idea that wafer bonding is

essentially an oxidation of the interface. Certainly, more work can be done in this area

to elicit the mechanisms responsible for this interesting phenomena, including a more

comprehensive study of roughness as a function of plasma species, power, exposure

time, driving frequency, and reactor type. Now that it is known what sort of conditions

results in an effective surface activation for high bond strengths (chapter 2), the study

can be centered around these parameters. Without these specific conditions, this study

would be an exercise in frustration. The basic surface chemistry presented in books on

wafer bonding was never quite satisfying to me. I had picked up the idea of looking at

the isolated and associated silanols after reading that the associated silanols apparently

attract water more strongly than the isolated silanols in Tong and Gosele’s book.

These can only be detected using multiple internal transmission FTIR measurements

to strength the absorption of IR light from the resonances of these molecular species.
 198

Thinking about this will eventually lead to wondering how the plasma activation

affects these silanol groups. This can be further explored using plasma activated and

annealed bonded pieces to look for isolated and associated silanol groups, using

different types of oxides (e.g. various chemical oxides, wet and dry oxides), and

different plasma reactors to explore whether the activation is dominated by physical

mechanisms or chemical mechanisms (using the ICP vs RIE type reactors). There are

many potential problems that will be briefly described in hopes of helping the reader

who chooses to attempt these types of experiments. First of all, aligning the IR beam

from scratch/spare parabolic and elliptical mirrors and micro-positioners is no easy

feat, even with a IR phosphor detection card. I did get the system aligned and the

signal was read using a mercury cadmium telluride (MCT) detector with help from

Lucio Flores (of Professor John Crowell’s group in the chemistry dept. of UCSD) but

the next problem was to enclose the system in a dry nitrogen box to avoid partial

absorption of the spectra from water in the atmosphere (the silanol group peaks largely

lie in the middle of the water spectrum), and that was never completely done. Another

point worth exploring is confirming the impact of UV light in the activation process

and carefully quantifying its contribution. I’ve seen at least one thesis on this topic

but it was unconvincing because there was no tangible model to explain the results.

What might be a useful approach is to temporarily bond a piece of double polished

sapphire (because it allows the UV to pass through) to a silicon wafer and put that

piece in the plasma reactor. This allows UV to interact with the surface but does not

allow the ions to come into contact with the surface. Afterwards, unbond the sapphire
 199

and bond the silicon wafers together. It would be better if one or the other or both

wafers could be tested in this manner similar to what Tommi Suni did in this Masters

thesis (VTT Electronics, 2001). Another, easy in principle, experiment is to try and

measure the UV spectrum of the different plasmas through the port window of the

plasma chamber and correlate the photon energies with bond strengths present at the

Si-SiO2 interface. Of course, the transmission spectrum of the window would have to

be known for this information to be useful. Ideally, the complete characterization of

the plasma would be ideal but due to the number of variables which are often coupled

to other variables, this has proven to be next to impossible. The foundation for

investigating the physics of how to exfoliate a film lies in the ability to consistently

control the bond strength of the two wafers. This is because the wafer-to-wafer bond

strength must exceed that of the implanted interfacial bond strength. The capability to

achieve a strong bond at low processing temperatures minimizes problems in material

due to such things as thermal donors as was seen in chapters 3 and 4. The properties of

the glass used as the backplane in the FPD are not as thoroughly explored as that of Si.

Keeping the process temperatures low also minimizes any diffusion of impurities from

the glass into the Si used for the TFTs.

The physics behind the film exfoliation is being vigorously investigated. For

this thesis, only hydrogen implantation was used. At least part of the complication

came from the fact that depending on how the film was exfoliated, different electrical

properties (as measured by Hall effect) were found. The main indicator of this was a

difference in the depth distribution of the carrier concentration (or sheet charge). In
 200

general, mechanically exfoliated films displayed lower carrier concentrations

compared to thermally exfoliated films at the same depth into the film. Whether or not

the damage layer was etched off prior to annealing also made a significant difference.

The damage layer also seemed to extend further than the “standard” 1500 Å as seen

from TEM because the meeting point of the EA and AE sheet charge distributions

was observed to “meet up” maybe 100-200 Å deeper than where the damage layer was

supposed to end. Perhaps, etching off a little more would result in improved electrical

characteristics due to a more complete elimination of defects that could diffuse around

the film? The issue of anneal ambient was not explored due to the time issue of this

thesis. Due to safeguards for securing extra gas cylinders and the like, it was never

convenient to use argon as the annealing ambient during the fabrication of the

MOSFETs. It would be interesting to see how the transistor characteristics change

with argon instead of nitrogen.

The majority carriers in the film followed the standard behavior of what are

known as thermal donors. These can evolve into “new thermal donors” and “new

donors” upon annealing at higher temperatures, the respective distribution of which

depend strongly on the thermal history at lower anneal temperatures. Essentially, the

complexity of these donor states determines the properties of the film since these

donor states lead to the precipitation of oxide phases in the silicon which, because of

their volume expansion which leads to a lack of a complete lattice match, turn into

dangling bonds which then behave as deep level traps. These oxide precipitates as they

are termed, contain positive surface state charges that are present in any oxide. These
 201

positive charges originate from sodium or potassium contamination or local excesses

of unreacted Si. The positive charge results in layer inversion near the oxide

precipitates and due to their mismatch with the lattice, form dangling bonds which

cause states to open up in the band gap due to the disruption in the lattice. If the

density of these oxide precipitates is sufficiently high, the inversion layers connect

with each other eventually inverting a large portion of the material. This is a

complicated scenario to analyze especially with MOSFETs since the channel region is

formed by inverting the new donor inverted region. Nevertheless, with all these

interesting properties, devices were fabricated and tested.

p-type MOSFETs were fabricated because the films ended up n-type after

annealing above 920 °C. This was presumably due to the effect of new donors in the

silicon. Standard, large area MOSFETs were made for several reasons: to avoid

scaling problems or device artifacts associated with geometry, to get a good average

over a large part of the film, and to effectively amplify the leakage current so that low

current (<100 fA) measurement difficulties are avoided. With that given, the partially

depleted MOSFETs were fabricated using the standard process that goes up to 1000

°C (for oxidation and boron diffusion). What the results show are that the cold cut film

has the lowest leakage current and comparable transconductance, mobility,

subthreshold slope and threshold voltage. The small leakage current is thought to be

due to a smaller number of new donor states and/or oxide precipitates which are also

associated with deep level generation states which is consistent with the respective

formation densities of the new donors associated with the films.

 202

Samples obtained much later showed that p-type conductivity was recovered

after annealing at 1000 °C. To get a more complete picture, n-channel MOSFETs

could be fabricated and the results compared to the Hall effect measurements more

directly. To do this meaningfully though, would mean doing the Hall effect and

MOSFET characterization within a short time period. It was noticed that the Hall

effect measurements of the same sample taken after about 1.5 years did not show the

same characteristics. This is consistent with the observation that the layer by layer

etching and Hall effect measurements and to be done in the same run (the same day).

The result of starting one measurement one day and finishing the next day was that

there was always a large discontinuous change in the film properties, e.g. the sheet

charge distribution (see chapter 3). This time delayed measurement was only done for

a small number of samples so I can’t conclude that the sample characteristics always

change over time but it is certainly a point worth watching.

Overall, in this thesis, plasma activated hydrophilic silicon wafer bonding was

examined and reasonable control of the bond strength as a function of plasma and wet

chemical process parameters was obtained. This was necessary for the film exfoliation

process. The films were electrically characterized as a function of depth into the film

and at several different anneal temperatures. Clear differences were observed for the

mechanically and thermally exfoliated films which manifested as differences in the p-

channel MOSFETs fabricated on these films. The device fabricated on the

mechanically exfoliated film exhibited the desired characteristics for low power

consumption, and high performance flat panel displays.

 Appendix

Thermally exfoliated [Hot cut] (single ion)

Silicon on wet thermal oxide
Annealed 4 hours at 800 °C in argon

Table 3-10-1: Hall effect and hot probe measurement data for argon annealed
thermally exfoliated silicon on wet thermal oxide for EA (etched, then
annealed: damage layer etched off before annealing at 800 °C) and AE
(annealed, then etched: damage layer left intact during annealing). Qi denotes
the sheet charge. The samples were consistently n-type between the Hall effect
and hot probe measurements.

10/22/2002 Hot cut Argon annealed 4 hours at 800C

EA
Depth Qi
Si thickness electron conc. Hot
into Si ρ (Ω.cm) -3 µ (cm /V.s)
2
-2
(Å) (cm ) x1e16 (cm ) x1e11 Probe
(Å)
3400 1400 1.53 1.38 296 4.7 N
2750 2050 0.66 2.96 323 8.1 N
2200 2600 0.53 4.1 290 9.01 N
1700 3100 0.5 4.1 311 6.9 N
1200 3600 0.47 6.8 193 8.2 N
750 4050 0.43 4.04 356 3.03 N
400 4400 H.R.

AE
Depth Qi
Si thickness electron conc. Hot
into Si ρ (Ω.cm) -3 µ (cm /V.s)
2
-2
(Å) (cm ) x1e16 (cm ) x1e11 Probe
(Å)
4900 0 47 0.16 86 0.76 N
4300 600 26 0.11 208 0.49 N
3800 1100 13 0.225 214 0.86 N
3400 1500 2.9 0.49 433 1.67 N
3200 1700 1.9 0.71 467 2.3 N
2400 2500 2.2 0.72 394 1.72 N
1700 3200 1.7 1.2 294 2.1 N
950 3950 5.9 3.5 30 3.3 N

203
 204

Thermally exfoliated [Hot cut] (single ion)

Silicon on wet thermal oxide
Annealed 4 hours at 800 °C in oxygen

Table 3-10-2: Hall effect and hot probe measurement data for oxygen
annealed thermally exfoliated silicon on wet thermal oxide for EA (etched,
then annealed: damage layer etched off before annealing at 800 °C) and AE
(annealed, then etched: damage layer left intact during annealing). Qi denotes
the sheet charge. The samples were consistently n-type between the Hall effect
and hot probe measurements.

10/22/2002 Hot cut oxygen (dry) annealed 4 hours at 800C

AE
Depth
Si thickness electron conc. Qi Hot
into Si ρ (Ω.cm) -3 µ (cm /V.s)
2
-2
(A) (cm ) x1e16 (cm ) x 1e11 Probe
(A)
4700 0 6.8 0.41 223 1.9 N
4350 350 6.2 0.39 257 1.7 N
3700 1000 2.8 0.63 361 2.33 N
3250 1450 1.2 1.5 352 4.8 N
2150 2550 1.38 1.6 292 3.3 N
1500 3200 0.83 2.9 259 4.4 N
850 3850 1.5 19.6 22 17 N

EA
Depth
Si thickness electron conc. Qi Hot
into Si ρ (Ω.cm) -3 µ (cm /V.s)
2
-2
(A) (cm ) x1e16 (cm ) x 1e11 Probe
(A)
3000 1800 2.4 1 259 3.3 N
2400 2400 0.93 2.2 304 5.3 N
2000 2800 0.71 3.1 284 6.2 N
1500 3300 0.5 3.4 364 5.2 N
900 3900 0.33 5.8 332 5.21 N
700 4100 H.R.
 205

Thermally exfoliated [Hot cut] (single ion)

Silicon on wet thermal oxide
Annealed to 800 °C in nitrogen

Table 3-10-3: Hall effect and hot probe measurement data for (UHP) nitrogen
annealed thermally exfoliated silicon on wet thermal oxide for AE (annealed,
then etched: damage layer left intact during annealing). Qi denotes the sheet
charge. The samples were consistently n-type between the Hall effect and hot
probe measurements. The EA samples are shown later in this chapter.

Hot cut, nitrogen annealed at 800C

AE
Depth
Si thickness electron conc. Qi Hot
into Si ρ (Ω.cm) -3 µ (cm /V.s)
2
-2
(A) (cm ) x1e16 (cm ) x 1e11 Probe
(A)
4700 0 20.7 0.137 220 0.645 N
4300 400 19.7 0.191 166 0.82 N
3700 1000 3.7 0.63 270 2.3 N
3100 1600 1.32 1.08 440 3.33 N
2600 2100 1.08 1.3 436 3.45 N
2150 2550 1.26 1.66 297 3.6 N
1500 3200 1.45 1.67 259 2.5 N
1050 3650 unstable N
 206

Thermally exfoliated [Hot cut] (PIII)

Silicon on glass
Annealed 4 hours at 650 °C in N2

Table 3-12-1: Hall effect and hot probe data for PIII thermally exfoliated
silicon on 1737F glass. The mobilities are characteristically small presumably
due to the implantation of large numbers of impurities such as carbon,
nitrogen and oxygen. This is typical of PIII due to the non-UHV conditions.

PIII as-exfoliated silicon on glass

electron
mobility sheet charge Hot Probe
Si thickness(Å) depth(Å) ρ (Ω.cm) concentration
(cm2/V s) (cm-2) typing
(cm-3)
1620 0 2.3 1.50E+17 18 2.40E+12 N
1310 310 2 2.00E+17 16 2.60E+12 N
1000 620 2 4.50E+17 8 4.50E+12 N
870 750 1.6 2.90E+18 1.4 2.50E+13 N
450 1170 3 5.00E+16 42 2.30E+11 N

PIII annealed, then etched (with TMAH) silicon on glass

carrier
mobility sheet charge Hot Probe
ρ (Ω.cm) concentration
-3 (cm2/V s) (cm-2) typing
Si thickness(A) depth(A) (cm )
1620 0 459 -1.10E+15 -12 1.80E+10 P
1250 370 365 -9.40E+14 -18 -1.20E+10 P
940 680 279 7.10E+14 31 6.70E+09 P
LOST

1630 0 170 4.10E+15 9 6.50E+10 P

1380 250 154 3.90E+15 10.5 5.40E+10 P
1240 390 146 4.60E+15 9.4 5.70E+10 P
1030 600 139 5.20E+15 8.6 5.40E+10 P
810 820 140 7.40E+15 6 6.00E+10 P
600 1030 H.R.
350 1280 H.R.

PIII etched (with TMAH), then annealed silicon on glass

carrier
mobility sheet charge Hot Probe
ρ (Ω.cm) concentration 2 -2
-3 (cm /V s) (cm ) typing
Si thickness(A) depth(A) (cm )
940 100 1.00E+16 6 9.80E+10 P
650 115 1.80E+16 3 1.20E+11 P
560 H.R.
 207

Thermally exfoliated [Hot cut] (PIII)

Silicon on glass
Annealed 4 hours at 650 °C in air

Table 3-12-2: Note: these samples annealed in air, not nitrogen. Even after
multiple measurements, the data flip-flop between n and p type material as
shown by the Hall data and in some cases the hot probe data.
PIII SOG (samples annealed at 650C in air)
Pulse anneal time(total)
DC 0 hrs 1581 4.2 -1.00E+17 -14.1 -1.67E+12 N sample 7A unetched,unannealed
4 hrs 1581 100 4.30E+15 14.3 6.90E+10 P
1000 62 7.63E+15 13.2 7.63E+10 P TMAH etched
0 hrs. 1590 7.3 -3.90E+16 -22 -6.20E+11 N unetched, unannealed
4 hrs 1590 310 4.22E+14 48 6.71E+09 P 650C anneal in air only
1424 307 2.80E+15 7.3 4.00E+10 P TMAH etched
1155 250 1.70E+16 1.5 2.00E+11 P TMAH etched
990 267 1.63E+14 143 1.61E+09 P
975 253 1.00E+15 24 9.90E+09 P
4 hrs 1484 246 2.10E+14 122 3.10E+09 P
1014 224 -3.30E+15 -8.5 -3.30E+10 P ????????
701 144 5.62E+15 7.7 4.00E+10 P
24 hrs 1484 HIGHLY RESISTIVE
1179 HIGHLY RESISTIVE
1150 HIGHLY RESISTIVE

Short pulse 0 hrs 1464 38.8 -1.22E+16 -13.2 -1.80E+11 N sample 8B unetched,unannealed
1 hr 1464 65.4 3.84E+15 25 5.62E+10 P
4 hrs 1464 17 2.36E+00 15.5 3.45E+11 P
1157 39 -1.73E+15 -93 -2.00E+10 P TMAH etched
850 HIGHLY RESISTIVE TMAH etched

Long pulse 0 hrs 1390 56.5 4.28E+15 25.8 5.95E+10 N sample 9C unetched,unannealed
4 hrs 1390 HIGHLY RESISTIVE P?
8 hrs 1390 HIGHLY RESISTIVE P?
1131 HIGHLY RESISTIVE P? TMAH etched
1080 HIGHLY RESISTIVE P? TMAH etched
 208

Thermally exfoliated [Hot cut] (single ion)

Silicon on glass
Annealed varying times in air

Table 3-13-1: Top half data is as-exfoliated depth data measured by Hall
effect, hot probe and layer by layer etching with TMAH. Lower half data is
the electrical data measured the same way but the film has been annealed
(leftmost column) in air. The “14 hrs” and “2 hrs” signify the annealing time
of the bonded Si to glass pair before the film was exfoliated.
Post exfoliation Silicon carrier Hot
300C anneal time ρ mobility sheet charge
anneal time thickness concentration 2 Probe
before exfoliation (Ω.cm) (cm /V s) (cm-2)
@650C (Α) (cm-3) typing
0 hrs 14 hrs 4660 1.32 -1.60E+16 -292 -7.60E+11 N
4660 0.93 -3.50E+16 -193 -1.62E+12 N
4078 0.62 -4.70E+16 -211 -1.90E+12 N
3416 0.74 -3.30E+16 -240 -1.12E+12 N
3157 0.96 -2.86E+16 -242 -8.50E+11 N
2670 1.45 -1.20E+16 -357 -3.23E+11 N
2260 1.47 -2.40E+16 -175 -5.50E+11 N
1930 3.64 -1.40E+16 -119 -2.80E+11 N
1580 50 -4.65E+14 -270 -7.40E+09 N
1126 82 -5.35E+14 -143 -6.00E+09 N

0 hrs 2 hrs 4660 0.51 -3.60E+16 -341 -1.67E+12 N

4680 0.72 -7.60E+16 -114 -3.60E+12 N
3858 0.64 -3.30E+16 -295 -1.30E+12 N
3509 0.79 -2.20E+16 -364 -7.63E+11 N
3142 1.02 -1.78E+16 -343 -5.60E+11 N
2710 1.68 -1.13E+16 -330 -3.10E+11 N
2230 4.5 -8.00E+15 -170 -1.80E+11 N
2030 7.7 -2.10E+15 -378 -4.35E+10 N
1600 140 -2.10E+14 -213 -3.30E+09 N

Post exfoliation Silicon carrier Hot

300C anneal time ρ mobility sheet charge
anneal time thickness concentration Probe
before exfoliation (Ω.cm) -3 (cm2/V s) (cm-2)
@650C (Α) (cm ) typing
1 hr. 14 hrs. 4660 HIGHLY RESISTIVE
2.5 hrs. 14 hrs. 3460 22 -2.22E+15 -130 -7.70E+10 P
2.5 hrs. 14 hrs. 3164 75 2.00E+15 40 6.67E+10 P

1 hr. 2 hrs 4670 24 4.70E+15 56 2.20E+11 P

2.5 hrs. 2 hrs 4670 3.7 1.10E+16 159 5.00E+11 P
2.5 hrs. 2 hrs 3790 37 5.85E+14 287 2.22E+10 P
2.5 hrs. 2 hrs 3200 HIGHLY RESISTIVE

2 hrs 2 hrs 4630 51 1.90E+15 65 8.80E+10 P

4090 51 1.30E+15 94 5.30E+10 P
3470 131 4.30E+14 111 1.50E+10 P
2950 HIGHLY RESISTIVE
2590 HIGHLY RESISTIVE
1980 46 -5.30E+14 -258 -1.00E+10 N
1550 57 -4.60E+14 -237 -7.10E+09 N

4 hrs 2 hrs 4630 14 3.70E+15 122 1.70E+11 P

4090 18 2.20E+15 158 9.10E+10 P
3560 500 7.00E+14 18 2.50E+10 P
3050 213 -1.60E+14 -187 -4.80E+09 N
3050 122 -2.50E+14 -207 -3.80E+09 N
2580 15 -1.60E+15 -256 -4.20E+10 N
2170 14 -1.80E+15 -237 -4.00E+10 N
1500 4.4 8.30E+15 171 1.25E+11 N
 209

Thermally exfoliated [Hot cut] (single ion)

Silicon on glass
Annealed 4 hours at 650 °C in air

Table 3-14-1: Hall effect and hot probe data for AE (top half) and EA (bottom
half) silicon on glass samples. The bonded pair was annealed at 300 °C for 2
hours, and the exfoliated film was annealed at 650 °C for 4 hours in nitrogen.
Qi denotes the sheet charge.

-2
Si thickness Depth into electron Qi (cm )
ρ (Ω.cm) -3 µ (cm /V.s)
2
11
Hot Probe
(Å) Si (Å) conc.(cm ) [x 10 ]
4640 0 6.6 8.50E+15 112 3.90E+00 P
4115 525 5.8 9.90E+15 110 4.10E+00 P
3600 1040 2.1 1.20E+16 100 4.40E+00 P
3200 1440 4.90E+00 1.30E+16 101 4.10E+00 P
2700 1940 4.9 1.38E+16 92 3.70E+00 P
2250 2390 5.5 1.40E+16 81 3.10E+00 P
1980 2660 6.7 1.20E+16 78 2.40E+00 P
1820 2820 8.4 1.10E+16 66 2.00E+00 P
1630 3010 9.6 8.80E+15 74 1.40E+00 P
1430 3210 15.8 9.90E+15 40 1.40E+00 P
800 3840 H.R.

Si thickness Depth into electron Qi (cm-2)

ρ (Ω.cm) µ (cm /V.s)
2
Hot Probe
(Å) Si (Å) conc.(cm-3) [x 1011]
3200 1440 3.3 2.10E+16 92 6.6 P
2760 1880 3.5 1.90E+16 96 5.2 P
2500 2140 3.5 1.80E+16 100 4.4 P
2400 2240 3.7 1.70E+16 102 4 P
1450 3190 12.6 1.30E+16 39 1.9 P
 210

Thermally exfoliated [Hot cut] (single ion)

Silicon on wet thermal oxide
Annealed 4 hours at 900 °C in nitrogen

Table 3-15-1: Hall effect data for thermally exfoliated Si on wet thermal
oxide, annealed at 900 °C for 4 hours in nitrogen. The upper half of the table
shows the EA case (damaged layer etched off before annealing) and the lower
half shows the AE case (damage layer annealed with film). Qi denotes the sheet
charge.
Depth
Si thickness electron conc. Qi (cm-2) Hot
into Si ρ (Ω.cm) µ (cm /V.s)
2
(Å) (cm-3) x-1016 x -1011 Probe
(Å)
3220 1580 0.98 1.5 427 4.8 N
2800 2000 0.88 1.9 371 5.3 N
2450 2350 0.72 2.2 396 5.4 N
2200 2600 0.68 1.9 490 4.2 ?
2000 2800 0.7 2.1 423 4.2 N
1600 3200 0.79 2.3 345 3.65 ?
1150 3650 0.79 1.5 527 1.7 N
650 4150 H.R. P?

Depth -2
Si thickness electron conc. Qi (cm ) Hot
into Si ρ (Ω.cm) -3 µ (cm /V.s)
2
(Å) (cm ) x1e16 x 1e11 Probe
(Å)
4700 0 1.1 1.4 396 6.8 N
4000 700 0.79 2.1 386 8.2 N
3600 1100 0.68 2.3 398 8.3 N
3000 1700 0.51 3.3 377 9.8 N
2400 2300 0.52 2.4 455 6.3 N
1850 2850 0.43 6.1 234 1.1 N
1350 3350 0.43 5.2 280 7 N
900 3800 0.69 3.4 270 3.03 N
100 4600 unstable N
 211

Thermally exfoliated [Hot cut] (single ion)

Silicon on wet thermal oxide
Annealed 1 hour at 1050 °C in nitrogen

Table 3-16-1: Hall effect and hot probe data for thermally exfoliated silicon on
wet thermal oxide annealed at 1050 °C for 1 hour in nitrogen. The negative
values represent n-type carriers. Qi denotes the sheet charge.
Depth -2
Si thickness carrier conc. Qi (cm ) Hot
into Si ρ (Ω.cm) -3 µ (cm2/V.s)
(Å) (cm ) x1e16 x 1e11 Probe
(Å)
3120 1680 1.9 1.90E+16 175 -5.80E+11 N
2600 2200 1.4 3.85E+16 -117 -1.00E+12 N
2200 2600 1.6 -2.80E+16 -137 -6.30E+11 N
1100 3700 5 5.60E+15 218 6.30E+10 P
700 4100 unstable

Depth -2
Si thickness carrier conc. Qi (cm ) Hot
into Si ρ (Ω.cm) -3 µ (cm2/V.s)
(Å) (cm ) x1e16 x 1e11 Probe
(Å)
4600 200 0.34 -3.60E+16 -505 -1.70E+12 N
3900 900 0.29 -4.50E+16 -480 -1.74E+12 N
3150 1650 0.3 -4.20E+16 -492 -1.30E+12 N
2400 2400 0.4 -3.20E+16 -492 -7.60E+11 N
1100 3700 5.9 -3.40E+15 -313 -3.70E+10 N
 212

Mechanically exfoliated [Cold cut] (single ion)

Silicon on wet thermal oxide
Annealed 4 hours at 650 °C in nitrogen

Table 3-19-1: Cold cut films exfoliated at VTT electronics (Finland). In the AE
case (top set of data), the surface became rather non-uniform with the result
being that the thickness was not measurable using the Filmetrics F20. With the
EA case (bottom set), the film material became highly resistive (H.R.) after
etching off ~600 Å.

Annealed 650 °C for 4 hours in nitrogen

VTT Cold cut - annealed(650C for 4 hrs in N2) then etched
Si Depth
electron µ Qi Hot
thickness into Si ρ (Ω.cm) -3
conc.(cm ) (cm2/V.s) -2
(cm ) x1e11 Probe
(A) (A)
4850 0 4.1 8.00E+15 189 3.90 P
4215 635 3.5 5.70E+15 315 2.40 P
2540 2310 3.4 8.60E+15 216 2.20 P
1900 2950 5.2 2.60E+16 46 5.00 P
sample surface too nonuniform to measure using F20.

VTT Cold cut - etched(~1500A) then annealed(650C for 4 hrs in N2)

Si Depth
electron µ Qi Hot
thickness into Si ρ (Ω.cm) -3 2 -2
conc.(cm ) (cm /V.s) (cm ) x1e11 Probe
(A) (A)
3400 1450 3.3 1.00E+16 186 3.50 P
3150 1700 7.2 5.80E+15 151 1.80 P
2760 2090 120 1.50E+15 34 0.42 P
2510 H.R.
2300 H.R.
2000 H.R.
 213

Mechanically exfoliated [Cold cut] (single ion)

Silicon on wet thermal oxide
Annealed 4 hours at 800 °C in nitrogen

Table 3-19-2: Cold cut film exfoliated at VTT electronics (Finland). Annealed
at 800 °C for 4 hours in nitrogen.

6/11/2002
Etched (away damage layer), then anneal 800C for 4 hrs in nitrogen face down

Si Depth
µ Qi Hot
thickness into Si ρ (Ω.cm) -3
c.c. (cm ) 2 -2
(cm /V.s) (cm ) x1e11 Probe
(A) (A)
3230 1650 1.1 3.2E+16 172 10.00 P
2780 2100 1.8 2.8E+16 126 7.80 P
1780 3100 3.6 1.9E+16 89 3.50 P
800 4080 811 -1.4E+15 -5.5 -2.50 N

6/12/2002
Anneal, then etch 800C for 4 hrs in nitrogen face down

Si Depth
µ Qi Hot
thickness into Si ρ (Ω.cm) -3
c.c. (cm ) 2 -2
(cm /V.s) (cm ) x1e11 Probe
(A) (A)
4860 0 3.5 1.10E+16 166 5.20 P
4150 710 3.1 1.50E+16 141 6.00 P
3730 1130 3.1 1.30E+16 153 5.00 P
3380 1480 3.3 1.50E+16 126 5.00 P
2750 2110 4.34 1.30E+16 113 3.50 P
1690 3170 12.6 3.30E+15 151 5.56 P
1270 3590 19.5 -6.50E+15 -49 -8.30 P
500 4360 H.R.
 214

Mechanically exfoliated [Cold cut] (single ion)

Silicon on wet thermal oxide
Annealed 4 hours at 900 °C in nitrogen

Table 3-19-3: Cold cut film exfoliated at VTT electronics (Finland). Annealed
at 900 °C for 4 hours in nitrogen. The NÆP signifies that the hot probe
reading switched type (voltage polarity) over the course of the measurement.

Annealed 900 °C for 4 hours in nitrogen

Annealed then etched

Si Depth
hole conc. µ Qi Hot
thickness into Si ρ (Ω.cm) -3 2 -2
(cm ) x1e16 (cm /V.s) (cm ) x1e11 Probe
(A) (A)
4700 100 2 2 158 9.4 P
4350 450 2.1 2 150 8.6 P
4120 680 2.2 2 140 8.2 P
3500 1300 3.4 1.5 123 5.2 P
3200 1600 8.3 0.77 98 2.5 P
2800 2000 9.5 2.8 24 7.7 P
2400 2400 25 -1.4 -185 -0.33 N
2000 2800 33 0.26 71 0.53 P
1800 3000 31 -0.16 -125 -0.29 P

Etched then annealed

3350 1450 1.1 6.1 91 20 P
3100 1700 2.3 4.5 60 14 P
2900 1900 1.6 0.6 106 10 P
2300 2500 4.3 1.9 75 4.4 P
2050 2750 2.7 3.1 77 6.3 P
1700 3100 3.1 3.5 59 5.9 N -> P
1400 3400 11 0.11 537 0.15 P
 215

Mechanically exfoliated [Cold cut] (single ion)

Silicon on wet thermal oxide
Annealed 1 hour at 1000 °C in nitrogen

Table 3-20-1: Cold cut film exfoliated at VTT electronics (Finland). Annealed
at 1000 °C for 1 hour in nitrogen.

7/16/2002 VTT cold cut annealed 1000C for 1 hr in nitrogen.

Annealed then etched

Si Depth
electron µ Qi Hot
thickness into Si ρ (Ω.cm) -3 2 -2
conc.(cm ) (cm /V.s) (cm ) Probe
(A) (A)
4790 0 4.1 -3.20E+15 -472 -1.60E+11 N
4230 560 2.3 -1.10E+15 -251 -4.60E+10 N
3730 1060 1.12 -9.80E+15 -570 -3.60E+11 N
3250 1540 0.81 -1.30E+16 -585 -4.30E+11 N
2640 2150 -2.00E+16 -615 -5.20E+11 N
2100 2690 2.6 -5.90E+15 -410 -1.20E+11 N
1500 3290 0.69 -1.70E+16 -529 -2.60E+11 N

Etched then annealed

3340 1450 0.29 -3.40E+16 -635 -1.10E+12 N
2450 2340 0.28 -3.30E+16 -672 -8.10E+11 N
2140 2650 0.3 -2.90E+16 -706 -6.20E+11 N
1920 2870 0.52 -1.90E+16 -624 -3.70E+11 N
1650 3140 0.86 -1.40E+16 -534 -2.20E+11 N
1450 3340 0.77 -1.40E+16 -578 -2.00E+11 N