International Conference on Computation of Power, Energy, Information and Communication (ICCPEIC-2013), 17th & 18th , April 2013

Harmonics reduction using Multilevel inverter with SMES by OHPDPWM Technique

K.Parventhan. V. Raja

AbstractThe Static synchronous compensator is a shunt compensation device based on the principle of power electronics. Recent development of FACTS devices provides the reliable solution to potential problems. A cascaded multilevel inverter with Super Conducting Magnetic Energy Storage (SMES) is proposed for reduction of harmonics content. Multilevel inverter based FACTS offers improved voltage quality, decreased switching frequency. Here OHPDPWM technique is applied to the Multilevel Inverter (MLI) to obtain better performance. The performances of different PWM techniques applied to the Multilevel Inverter (MLI) are studied and the simulation result was carried out. Index TermsA STATCOM, SMES, Multilevel inverter, OHPDPWM

The multilevel VSC is the integral part of the STATCOM FACTS device, which supplies or absorbs the reactive power in transmission line to control the voltage of bus to which it is connected. The various multilevel VSCs are Diode Clamped Multilevel Inverter (DCMLI), Flying Capacitor Multilevel Inverter (FCMLI) and Cascaded Multilevel Inverter (CMLI). The Cascaded Multilevel Inverter (CMLI) is best suitable for the FACTS compensation device [2]. The Cascaded MLI has the series connection of two single phase full bridge inverters. In comparison of other multilevel inverters, Cascaded MLI has some advantages. The CMLI eliminates the large number of bulky transformers, clamping diodes and flying capacitors [2, 3]. The H-Bridge Cascade VSC can operate at lower switching frequency. There are various types of modulation techniques available in MLI, but each modulation technique aims to the stepped switching waveform resulting in reduced harmonics. The modulation schemes are based on the multiple carrier arrangements with pulse width modulation. The carriers are arranged with vertical shifts (Phase Disposition, Phase opposition disposition and Alternate phase opposition disposition), or with horizontal shifts (Phase shifted carrier PWM). The hybrid modulation scheme improves the performance of the Multilevel Inverter (MLI) [6]. In the STATCOM, the capacitor banks, pumped storage hydroelectric system and Battery Energy Storage System (BESS) are used to maintain a constant DC voltage for the Voltage Source Converter (VSC) operation. The drawbacks in BESS includes in a limited life cycle, voltage and current limitations and potential environmental hazards [11]. So here it is proposed to implement the SMES device. SMES is a large super conducting coil capable of storing electric energy in the magnetic field generated by DC current flowing through it. As per system requirements, the real and reactive power are absorbed and released from SMES coil. The one major advantage of the SMES coil [13] is that it can discharge large amount of power in a small period of time.

I. INTRODUCTION Most of the power systems are affected by the power quality issues. The power quality problem means any power problem manifested voltage, current and frequency deviation. Harmonics, voltage flicker, voltage regulation, unbalance, voltage sag and swell usually characterized the quality of electric power. The problem of eliminating harmonics in switching inverters has been the focus of research for many years [1]. The current trends of modulation control for multilevel inverters are to produce high quality of power output with high efficiency.

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K,Parventhan., Power Electronics and Drives, Department of EEE Dr.Pauls Engineering College Villupuram, Tamilnadu, India, raja_7372@yahoo.com, V. Raja. Power Electronics and Drives, Department of EEE Dr.Pauls Engineering College, Villupuram, Tamilnadu, India, rajasur22@gmail.com

ISBN: 978-1-4673-6406-5/13/$31.002013IEEE

International Conference on Computation of Power, Energy, Information and Communication (ICCPEIC-2013), 17th & 18th , April 2013
Fig.2. Schematic diagram of the inverter topology used to Verify the proposed five level (line to neutral) HPDPWM Method.

Fig.1. Overview of the block diagram. Fig.1. shows an overview of the block diagram for the multilevel VSI connected to the 14 bus AC system. In the proposed system, STATCOM consists of a cascaded multilevel inverter, SMES and the PID controller. The cascaded multilevel inverter is modulated by the Optimized Hybrid Phase Disposition PWM (OHPDPWM). The controller controls the input of the DC-DC converter and output of the CMLI. The reactive power exchange between the CMLI and the 14 bus AC power system can be controlled by varying the output voltage of the CMLI. When the load is connected to the 14 bus system, the voltages at some buses experiences voltage drop. This dropping voltage compensates by using Multilevel Inverter (MLI) based STATCOM. In this paper, the problem of harmonics and switching losses are considered. The various modulation technique schemes are applied to the MLI of STATCOM and the performance of different PWM schemes are compared and summarised in this paper. The simulation results of the above were carried out by using MATLAB/SIMULINK.

The carrier-based modulation schemes for multilevel inverters can be generally classified into two categories: phaseshifted and level-shifted modulations. Both modulation schemes can be applied to the CMLI inverters. THD of phase-shifted modulation is much higher than level-shifted modulation [4]. Therefore we have considered level-shifted modulation. An mlevel CMLI inverter using level-shifted multicarrier modulation scheme requires (m-1) triangular carriers, all having the same frequency and amplitude. The (m-1) triangular carriers are vertically disposed such that the bands they occupy are contiguous. There are three alternative PWM strategies with different phase relationships for the level-shifted multicarrier modulation: (i) In-phase disposition (IPD), where all carrier waveforms are in phase. It is generally accepted that the PD strategy gives rise to the lowest harmonic distortion for the line to line voltage. (ii) Phase opposition disposition (POD), where all carrier waveforms above zero reference are in phase and are 180 degree out of phase with those below zero. (iii) Alternate phase disposition (APOD), where every carrier waveform is in out of phase with its neighbor carrier by 180 degree. The cascaded inverter offers extra degree of freedom and greater possibilities in terms of device utilization, state redundancies, and effective switching frequency. In this paper, hybrid PWM scheme is presented which take advantage of the special properties available in conventional PWM methods and to minimize switching losses with better harmonic performance [6].

III. PROPOSED HYBRID PWM CONTROL METHOD II. CONVENTIONAL CARRIER BASED MODULATION SCHEMES The proposed hybrid PWM is the combination of low frequency PWM and high frequency SPWM. In each cell of cascaded inverter, the four power devices are operated two different frequencies, two being commutated at low frequency, i.e., the fundamental frequency of the output, and while the other two power devices are pulse width modulated at high frequency [9]. This arrangement causes the problem of differential switching losses among the switches.

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International Conference on Computation of Power, Energy, Information and Communication (ICCPEIC-2013), 17th & 18th , April 2013

IV. REACTIVE POWER AND HARMONICS CONTROL USING MULTILEVEL INVERTER STATCOM Compared to the two level voltage source inverters, the stepwise output voltage is the main advantage of the multilevel inverters. This advantage results in higher power quality, lower switching losses and THD minimization. The H-Bridge cascade multilevel inverter consists of two full bridge inverters connected in cascade manner. Each full bridge inverter requires the separate dc sources and it does not have the clamping diodes and flying capacitors. It consists of four switches per leg. Each of the switches consists of a power semiconductor device and an anti-parallel diode. The single PWM approach is used to generate the gating pulses for the switches Sal, Sa2, Sa3 and Sa4. Five level-inverter can produce voltage levels of +2V, +V, 0, -2V and - V. These voltage levels can be obtained using two separate dc sources. The proposed five-level STATCOM with SMES is simulated by using MATLAB/SIMULINK software. V. SIMULATION RESULTS A. H-bridge cascaded Multilevel Inverter

Fig.3. Reference and Carrier Signals for a five level Inverter. An optimized sequential signal added to the hybrid PWM pulses overcomes this problem. The low and high frequency PWM signal are shown in Fig.3. An optimized hybrid PDPWM method commutates the power switches at high frequency and low frequency sequentially. A common sequential signal and low frequency PWM signals are used for all cells in cascaded inverter. A high frequency SPWM for each cell is obtained by the comparison of the rectified modulation waveform with corresponding phase disposition carrier signal [9]. The low frequency PWM signal should be synchronized with the modulation waveform. Fig.4. shows the generation of gate pulses by a hybrid PWM controller. This controller is designed to mix the sequential signal, low frequency PWM and high frequency phase disposition sinusoidal PWM and to generate the appropriate gate pulses for cascaded inverter.

Fig.5. Cascaded multilevel inverter SIMULINK arrangement . H-bridge cascaded Multilevel Inverter SIMULINK arrangement is shown in Fig.5. The two single phase full bridge inverters are connected in series with separate dc sources and it is connected to the SMES device.

Fig.4. Low and High frequency PDPWM pulses. ISBN: 978-1-4673-6406-5/13/$31.002013IEEE

International Conference on Computation of Power, Energy, Information and Communication (ICCPEIC-2013), 17th & 18th , April 2013
B. SMES circuit D. Output Summary

Fig.6. SMES coil with DC-DC converter SIMULINK arrangement. The SMES coil with DC-DC converter SIMULINK arrangement is shown in Fig.6. The SMES coil stores the electrical energy that discharges through the DC-DC converter. This dc-dc converter connects the input of the H-bridge cascaded Multilevel Inverter. C. 14 Bus System

Table.1. Output summaries of 14 bus voltages in different conditions. The output summaries of 14 bus system is shown in Table.1. CMLI based STATCOM is connected to bus 3 and the voltage at the bus 3 observed by different PWM techniques to the controller. The results are same as tabulated in Table.2.

Compensation Load
Inverter
Triggering Technique

Voltage

P MW

Energy

device

(KV )

Q
MVAR

THD

(%)

With out load

With out compensation Single PWM

Multiple

4679 3419 3470 3837

0.85 0.61 0.20 0.25

.209 .206 .693 .864

7.62 2.26 0.60 0.60

With RL load

Multi Level
Inverter

Fig.7. IEEE 14 bus system SIMULINK arrangement. The standard IEEE 14 bus system SIMULINK arrangement is shown in Fig.7.

PWM OHPD PWM OHPD PWM

Controller

SMES 3840

Table.2. Comparison of P, Q and THD output values.

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International Conference on Computation of Power, Energy, Information and Communication (ICCPEIC-2013), 17th & 18th , April 2013
E. Load voltages with STATCOM

Fig.9 (b).P and Q output values with STATCOM. Simulation output of the Real power (P) and Reactive power (Q) With STATCOM operation is shown in the Fig.9 (b). G. Multilevel VSC Output voltage

Fig.8. Load voltages with STATCOM . Fig.8. shows the variation and the load voltages for different loading condition aloso the improvement in voltage after conecting the STATCOM is shown in Fig.8. F. Output of the P and Q values Fig.10 (a). 5 level single PWM. Simulation output of the 5 level Multilevel VSC, using single PWM output is shown in the Fig.10 (a).

Fig.9 (a).P and Q output values without STATCOM. Simulation output of the Real power (P) and Reactive power (Q) Without STATCOM shown in the Fig.9 (a).

Fig.10 (b). 5 level Multiple PWM. ISBN: 978-1-4673-6406-5/13/$31.002013IEEE

International Conference on Computation of Power, Energy, Information and Communication (ICCPEIC-2013), 17th & 18th , April 2013
Simulation output of the 5 level Multilevel VSC, when applying Multiple PWM output shown in the Fig.10 (b).

Fig.12 (b) . FFT analysis of OHPD PWM technique. I. Harmonics order table

Fig.10 (c). 5 level OHPD PWM. Simulation output of the 5 level Multilevel VSC, when applying OHPD PWM output is shown in the Fig.10. (c). H. THD Output

Fig.12 (a). FFT analysis in single PWM technique.

Table.3. Harmonics order table at different conditions.

.

VI. CONCLUSION In this paper, a Cascaded MLI based STATCOM is proposed for harmonic reduction. Here OHPDPWM technique is applied to the MLI to obtain better performance. The performances of different PWM techniques applied to the MLI are studied and the simulation results of the same are obtained using MATLAB/SIMULINK platform. The simulation results shows considerable decrease in harmonics and switching losses for the proposed OHPDPWM technique based Cascaded Multilevel Inverter.

Fig.12 (b) . FFT analysis in multiple PWM technique.

ISBN: 978-1-4673-6406-5/13/$31.002013IEEE

International Conference on Computation of Power, Energy, Information and Communication (ICCPEIC-2013), 17th & 18th , April 2013

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ISBN: 978-1-4673-6406-5/13/$31.002013IEEE