KEEE2276 D1: Adder and Counter (Digital Lab)

AHMAD FAHMI BIN AHMAD SAZALI (KEE110001) Name of demonstrators: Mr Islam

Abstract The digital circuit of a half adder, full adder, 4-bit adder and a synchronous 3-bit counter was designed and simulated utilizing MAX+PLUS II software. The simulation consists of applying a chosen input waveform to the circuit. The resulting output of each of the four circuits was analysed and verified to be true.

1.

Introduction Half Adder A half adder has two inputs and two outputs. The half adder adds two different binary values and then produces the sum bit and carry bit. The carry bit is generated if both inputs are logic high (1). The logical function for the carry bit is AND. The sum bit yields a 1 only when one of the inputs is a logical high. Else a logical low is produced. The logical function for the sum operation is XOR.

The logical circuit implementation is as shown below:

Figure 1: Half Adder Circuit

Table 1: Truth table for Half Adder A 0 0 1 1 B 0 1 0 1 SUM 0 1 1 0 CARRY 0 0 0 1

Full Adder A full adder circuit is similar to the half adder but has an extra input for incoming carry bit. Thus the full adders advantage over the half adder is that it can be cascaded to add multiple N bits. An N bit adder requires N full adders.

Figure 2: Full Adder Circuit

Table 2: Truth table for Full Adder (solution to exercise) A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 CARRY IN 0 1 0 1 0 1 0 1 SUM 0 1 1 0 1 0 0 1 CARRY OUT 0 0 0 1 0 1 1 1

4 Bit Adder A 4 bit adder is simply four full adders cascaded together. Consider Figure 3 and Figure 4.

Figure 3: Simplified Four bit Adder

Figure 4: Four bit Adder (solution to exercise)

3 Bit Synchronous Counter A 3 bit synchronous counter consists of 3 JK flip flops cascaded together. The least significant bit inverts for every clock pulse, the second significant bit inverts only when this bit and the previous bit are the same at the next clock pulse. Similarly, the third MSB inverts only when all the previous bits are the same including the MSB at the next clock pulse. From the description the logical implementation may be formed without constructing a state analysis for synthesis

Figure 5: 3 Bit Synchronous Counter

2.

Results and Discussion

a.

Half Adder A half adder was drawn and simulated in MAX PLUS+II. The output waveform yielded

Figure 6: Graph of input waveform (A,B) on half adder with output waveform (S,C)

b.

Full Adder

Figure 7: Graph of input waveform (A,B, Carry in) on Full Adder with output waveform (Sum, Carry out)

c.

4 Bit Adder

Figure 8: Waveform input/output for 4 bit adder

d.

3 Bit Synchronous Counter

Figure 9: Waveform input/output for 3 Bit Synchronous Counter

3.

Exercises Question: Design 3 bit synchronous counter using JKFF. Sequence is: 000->001->011-

>101->000. Values not stated in the sequence will go to 000;

Solution:
Table 3: Next State table

y3, x y1,y2 00 01 11 10

00

01

11

10

000 000 000 000

001 000 000 000

011 101 000 000

001 011 000 101

Table 4: Next State table for y1

y3, x y1,y2 00 01 11 10

00

01

11

10

0 0 0 0

0 0 0 0

0 1 0 0

0 0 0 1

Table 5: J1K1 Inputs

y3, x y1,y2 00 01 11 10

00

01

11

10

0d 0d d1 d1

0d 0d d1 d1

0d 1d d1 d1

0d 0d d1 d0

Table 6: Next State table for y2

y3, x y1,y2 00 01 11 10

00

01

11

10

0 0 0 0

0 0 0 0

1 0 0 0

0 1 0 0

Table 7: J2K2 Inputs

y3, x y1,y2 00 01 11 10

00

01

11

10

0d d1 d1 0d

0d d1 d1 0d

1d d1 d1 0d

0d d0 d1 0d

Table 8: Next State table for y3

y3, x y1,y2 00 01 11 10

00

01

11

10

0 0 0 0

1 0 0 0

1 1 0 0

1 1 0 1

Table 9: J3K3 Inputs

y3, x y1,y2 00 01 11 10

00

01

11

10

0d 0d 0d 0d

1d 0d 0d 0d

d0 d0 d1 d1

d0 d0 d1 d0

Figure 10: Circuit for counter in exercise

4.

Conclusions The design of an adder and a counter can be conveniently simulated in a computer. Thus

the verification process ( logic test) of a circuit can be quickly performed.

5.

References
1. 2. [online] http://hyperphysics.phy-astr.gsu.edu/hbase/electronic/fulladd.html [online] http://www.allaboutcircuits.com/vol_4/chpt_11/3.html