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1. Overview of 8051 Architecture, Timing, On-chip Resources, Instruction Set etc. Derivative products
A Microcontroller because you can make a one-chip system with the one chip containing:
- Easy interfacing.
- 32 I/O lines.
P0.7
XTAL1 P0.6 P
P0.5 O ADDRESS
P0.4 R AND
XTAL2 P0.3 T DATA BUS
P0.2
P0.1 0
P0.0
EA
PSEN P1.7
P1.6 P
ALE P1.5 O
P1.4 R
P1.3 T
P1.2 1
P1.1
P1.0
CPU
TXD RXD
P0 P2 P1 P3
(Address/Data)
ALE
_____
PSEN
8051
A15 - A8
PORT2 ROM(S)
ALE ADDRESS
AD7 - AD0 ADDRESS
LATCH INPUTS
PORT0
A7 - A0 DATA
D7 - D0 OUTPUTS
PSEN OE
+5V +5V
8051 80C51
10uF 2.2uF
RST RST
8.2K
F8
F0 B
E8
E0 ACC
D8
D0 PSW
C8
C0
B8 IP
B0 P3
A8 IE
A0 P2
98 SCON SBUF
90 P1
88 TCON TMOD TL0 TL1 TH0 TH1
80 P0 SP DPH DPL PCON
Interrupt control:
-IE : Interrupt Enable.
-IP : Interrupt Priority.
I/O Ports:
- P0 : Port 0.
- P1 : Port 1.
- P2 : Port 2.
- P3 : Port 3.
Serial I/O:
- SCON : Serial port control.
- SBUF : Serial data registers.
Other:
- PCON : Power control & misc.
- CY : Carry Flag.
- AC : Auxiliary Carry Flag.
- F0 : Flag 0 (available for user).
- RS1 : Register Select 1.
- RS0 : Register Select 0.
- OV : Arithmetic Overflow Flag.
-P : Accumulator Parity Flag.
- Quasi-bidirectional:
P1 P2 P3
PORT
PIN
Q N
FROM
PORT
LATCH INPUT
DATA
READ
PORT
PIN
NM OS
2 OSC.
PERIODS
PORT
PIN
Q
FROM
PORT
LATCH
As an I/O port:
Standard quasi-bidirectional.
- Alternate functions:
Only on some derivatives.
- As an I/O port:
Standard quasi-bidirectional.
- Alternate functions:
High byte of address bus for external
program and data memory accesses.
- Alternate functions:
Serial I/O - TXD, RXD
Timer clocks - T0, T1
Interrupts - INT0, INT1
Data memory - RD, WR
- Counts:
CPU cycles (crystal/12).
External input (max. half CPU rate).
- Timer Mode 1 :
Simple 16-bit counter.
- Timer Mode 2 :
8-bit auto-reload.
Counter in TL0 or TL1.
Reload value in TH0 or TH1.
Provides a periodic flag or interrupt.
Osc. ÷ 12
Int errupt
TL1 TH1 TF1
8- bits 8- bits
T1 (Pi n)
Cont rol
TR1
Gat e
INT1 (Pi n)
The Gate input controls whether the Counter runs while gated by the interrupt signal or not.
Timer 1 Timer 0
- TR1, TR0 : Run control bits for Timer 1 and Timer 0. Set to
run, reset to hold.
TXD and RXD are the serial output and input pins (Port 3, bits 1 and 0).
Mode 0: Shift Register Mode. Serial data is transmitted/received on RXD. TXD outputs shift clock. Baud
Rate is 1/12 of clock frequency.
Mode 1: 10-bits transmitted or received. Start (0), 8 data bits (LSB first), and a stop bit (1). Baud Rate
Clock is variable using Timer 1 overflow or external count input. Can go up to 104.2KHz (20MHz
osc.).
Mode 2: 11-bits transmitted or received. Start (0), 8 data bits (LSB first), programmable 9th bit, and stop bit
(1). Baud Rate programmable to either 1/32 or 1/64 oscillator frequency (625KHz for 20MHz
osc.).
Mode 3: 11-bit mode. Baud Rate variable using Timer 1 overflow or external input. 104.2 KHz max. (20
MHz osc.).
Serial Communication Modes 2 and 3 allow one "Master" 8051 to control several "Slaves":
The serial port can be programmed to generate an interrupt if the 9th data bit = 1.
The TXD outputs of the slaves are tied together and to the RXD input of the master. The RXD inputs of the
slaves are tied together and to the TXD ouput of the master.
Each slave is assigned an address. Address bytes transmitted by the master have the 9th bit = 1.
When the master transmits an address byte, all the slaves are interrupted. The slaves then check to see if
they are being addressed or not.
The Addressed slave can then carry out the master's commands.
- 0 = Disabled.
- 1 = Enabled.
Source Address
IE0 03H
TF0 0BH
IE1 13H
TF1 1BH
RI&TI 23H
- PS : Serial interface.
- PT1 : Timer 1.
- PX1 : External interrupt 1.
- PT0 : Timer 0.
- PX0 : External interrupt 0.
- 0 = Low priority.
- 1 = High priority.
2. Immediate operands:
The # sign is the designator. These are 8-bits except for DPTR contents (16-bits).
3. Register operands:
Designated as Rn, where n is 0..7. One of the four Register Banks is used (PSW selected).
4. Direct Operands:
From 00 to FF Hex, specifies one of the internal data addresses.
5. Indirect Address:
Designated as @Ri, where i is 0 or 1, uses the contents of R0 or R1 in the selected Register
Bank to specify the address. Other form is @A, using Accumulator contents.
ADD A, Rn 1/1
ADDC A, direct 2/1
SUBB A, @Ri 1/1
A, #data 2/1
INC A 1/1
DEC Rn 1/1
direct 2/1
@Ri 1/1
ANL A, Rn 1/1
ORL A, direct 2/1
XRL A, @Ri 1/1
A, #data 2/1
direct, A 2/1
direct, #data 3/2
C, bit 2/2
C, /bit 2/2
CLR A 1/1
CPL C 1/1
bit 2/1
RL A 1/1
RLC A 1/1
RR A 1/1
RRC A 1/1
SWAP A 1/1
SETB C 1/1
CLR bit
CPL
2/1
MOV A, Rn 1/1
A, direct 2/1
A, @Ri 1/1
A, #data 2/1
Rn, A 1/1
Rn , direct 2/2
Rn, #data 2/1
direct, A 2/1
direct, Rn 2/2
direct, direct 3/2
direct, @Ri 2/2
direct, #data 3/2
C, bit 2/1
bit, C 2/2
XCH A, Rn 1/1
A, direct 2/1
A, @Ri 1/1
NOP - 1/1
JC rel 2/2
JNC rel 2/2
JB bit, rel 3/2
JNB bit, rel 3/2
JBC bit, rel 3/2
· Clock synchronization.
· Arbitration procedure.
· Transmission speed up to 100Khz
· Maximum bus length of 4 meters.
· Maximum drive capacity of 400pF.
· Allows series resistor for IC protection.
· Compatible with most IC technologies (TTL, CMOS,Etc.).
MASTER:
· Initiates a transfer by generating start
and stop conditions.
· Generates the clock.
· Transmits the slave address.
· Determines data transfer direction.
SLAVE:
· Responds only when addressed.
· Timing is controlled by the clock line.
· The device must also be able to sense the logic level on these
pins.
· The serial clock and data lines are connected to VCC through
pull up resistors.
+VDD
Pull-up
Rp Rp
Resistors
SDA Serial data line
SCL Serial clock line
DEVICE 1 DEVICE 2
SDA SDA
SCL S P SCL
Start Stop
Condition Condition
SDA
SCL
Data line
Change
stable:
of data
Data valid
allowed
R/W
7-bit slave address
R/W :
0 - Slave will be written by master.
1 - Slave will be read by master.
SDA
MSB
SCL S 1 2 7 8 9 1 2 3-8 9 P
START ACK ACK STOP
CONDITION CONDITION
· Master Write:
· Master Read:
Start counting
Wait State high period
CLK 1
CLK 2
Start counting
low period
SCL
ARBITRATION:
· Arbitration is the procedure by which competing masters decide final control of
the bus.
· I2C arbitration does not corrupt the data transmitted by the prevailing master.
Arbitration is performed bit by bit until it is uniquely resolved.
· Arbitration is lost by a master when it attempts to assert a high on the data line
and fails..
DATA1
DATA2
SDA
SCL 1 2 3 4 5
· Microcontrollers
· Microprocessors
· Keyboards
· Mouses
· Trackballs
· Tablets
· Low speed printers
· Modems
This interconnect method, known as ACCESS.bus, is based on the I2C serial protocol
invented by Philips.
ACCESS.bus features:
· Up to 14 devices
· Serial, daisy-chained 4-pin cable (2 pins are power and ground). Only ONE device
port needed on computer.
ACCESS.Bus features:
· DEC and Signetics will provide Developer's Kit with all information required to to
develop applications.
ADB ACCESS.bus
Hot-Plugging not recommended fully supported
Extended Memory
I/O 80C51 2 to 32 K
Product Name Process ROM RAM Pins 8-bit Ports Serial I/O Timers Special
8031/51 NMOS 4K 128 40 4 UART 2 Industry Standard
8032/52 NMOS 8K 256 40 4 UART 3 Industry Standard
8XC751 CEPROM 2K 64 24 2+3/8 I2C 1 24 Pin Skinny DIP
8XC752 CEPROM 2K 64 28 2+5/8 I2C 1 8-bit A/D,PWM
8XC31/51 CEPROM 4K 128 40 4 UART 2 20,24, 30MHz
8XCL410 SACMOS 4K 128 40 4 I2C 2 LowVolt/Power (1.8 volts)
80/3C851 EEPROM 4K 128 40 4 UART 2 256 EEPROM
8XC550 CEPROM 4K 128 40 4 UART 2 8-bit A/D, WD
8XC451 CEPROM 4K 128 68 7 UART 2 7 I/O Ports
8XC652 CEPROM 8K 256 40 4 UART,I2C 2 8K ROM, I2C Serial Bus
8XC52 CEPROM 8K 256 40 4 UART 3 Industry Standard
8XC053/054 CEPROM 8K/16k 192 42 4 -- 2 TV Display (OSD), D/A
8XC562 CEPROM 8K 256 68 6 UART 4 8-bit A/D, PWM, WD, T2
8XC552 CEPROM 8K 256 68 6 UART,I2C 4 10-bit A/D, PWM, WD, T2
8XC654 CEPROM 16K 256 40 4 UART,I2C 2 16K ROM, I2C Serial Bus
8XC524 CEPROM 16K 512 40 4 UART, I2C 3 16K, 512 bytes, WD
8XC528 CEPROM 32K 512 40 4 UART,I2C 3 32K ROM, 512 RAM, WD
ReadTimer: MOV ValH,TH0 ;Read initial timer high and low values.
MOV ValL,TL0
MOV A,TH0 ;Read timer high byte again.
CJNE A,ValH,ChkHigh ;Has it changed?
SJMP RTEX ;If not, first sample is OK.
The 80C51 has no basic compare instruction. However, the CJNE (compare and jump if not
equal) instruction leaves the carry flag set after execution, allowing further magnitude
comparisons to be made.
CJNE A,direct,rel
CJNE A,#data,rel
CJNE Rn,#data,rel
CJNE @Ri,#data,rel
The 80C51 does not have any specific built-in facility for allowing a hardware single step
operation. However, when a Return from Interrupt instruction is executed, at least one
instruction from the originally interrupted routine is always executed before another
interrupt may be serviced.
Thus, if execution of RETIs are carefully controlled while an interrupt is pending, a
software single step may be effected.
Assumption: use external interrupt 0 for Note: to measure pulse low time in this
the pulse input. Use timer 0 in gated manner, the input must be inverted
mode. externally.
Assumption: use external interrupt 0 for Note: this method may entail some loss of
the pulse input. precision due to the possibility of
variable interrupt latency.
Setup: (same as previous example, but leave timer gate function turned off)
MOV TMOD,#01h ;Timer 0 in mode 1.
timer
Assumption: use any spare port bit for Note: the precision of pulses generated using
the output. this method will vary depending on the
interrupt latency of the timer interrupt.
FFFF
Problem: move any random
external data memory block of
any length to another location.
{
{
0000
Often, an application may require a second UART communication function. A simplex (transmit or
receive only at any one time) UART can be programmed with the use of one timer.
The transmit routine will simply start the timer, create a start bit, and then send one bit at every timer
interrupt, until finally sending the stop bit. The transmit bit may be any unused port bit.
Since the receive routine must sample each bit somewhere in the middle of the bit cell, it starts the timer
with a value of a half bit cell when a start is detected. Then, on the first timer interrupt, it verifies the
presence of the start bit and changes the timer count to one full bit cell. On every subsequent timer
interrupt, one data bit is read, until finally the stop bit is verified. The receive bit must be an external
interrupt pin (usually INT0 or INT1).
Start Transmit
Exit
Start Receive
(START bit Interrupt)
Exit
Timer Interrupt
Y
Receive? Receive One Bit
Y
Done? Send STOP bit.
Exit
Exit
· Supports 80C51 derivative microcontrollers that have external program memory access
and serial port.
· Connects to an MS-DOS compatible PC via serial port (PC runs user interface software).
· Line assembler and disassembler.
· Register and memory contents may be viewed and altered.
· Source, memory, register windows.
· 32K user program memory on board.
· Software breakpoints.
· Help screens.
· Symbolic debugger.
· Upload and download of object and hex files.
· Fully documented. User's manual includes experiments for learning the development
board and the 80C51 architecture.
· Switches, LEDs, and a potentiometer are included to allow simple experiments to be
performed without additional circuitry.
· 8031/51 · 8xC550
· 8032/52 · 8xC552
· 8xC31/51 · 8xC528
· 8xC32/52 · 8xC652/654
· 8xC451 · 8xC851
Type 2 (limited support via I2C bus to type 1 device and PC)
· 8xC410
· 8xC751
· 8xC752
The 8xC751 and 8xC752 have no external program memory capability and do not
support user program loading on the DB-51.
The 8xC410 does not have an on-chip UART and must be communicated with via its I2C
port. The current version of the DB-51 does not support user program loading on the
8xC410.
MS-DOS PC Software
Compatible (user interface)
PC
Emulation
RS-232 Type 1 Memory
Interface Microcontroller 32K x 8
Monitor
I 2C EPROM
bus
Type 2
Microcontroller
· Self training and experimentation system for customers, FAEs, sales, factory, etc.
· Low cost development support, allows limited hardware and software prototyping.
Metalink
· macro cross assembler ASM51
· Public Domain! Free on the Signetics BBS
2500 AD software
· Macro assembler
· Cross assembler
· Simulator / debugger
· Download software:
- Public Domain 80C51 support tools
- Demonstration code
(800) 451-6644
or
(408) 991-2406