Agenda

MOS Transistor Modeling

Threshold Voltage, VT DC I-V Equations Body Effect Subthreshold Region

TAMU-474-09

J. Silva-Martinez

MOS Transistor
P-type transistor
S G

Thin oxide B S G

BASIC IDEA:
Thick oxide D

SOURCE-DRAIN CURRENT IS CONTROLLED BY THE SOURCE-GATE VOLTAGE. The system is isolated if the diodes are biased in reverse region by using the Bulk terminal.

N+

P+ N P-channel

P+

Substrate or well

Polysilicon (heavily doped)

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Threshold Voltage, VT
[Razavi]

Applying a positive voltage to the gate repels holes in the p-substrate under the gate, leaving negative ions (depletion region) to mirror the gate charge

Before a channel forms, the device acts as 2 series caps from the oxide cap and the depletion cap If VG is increased to a sufficient value the area below the gate is inverted and electrons flow from source to drain
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VT Definition
[Silva]

The threshold voltage, VT, is the voltage at which an inversion layer is formed
For an NMOS this is when the concentration of electrons equals the concentration of holes in the p- substrate

VT = MS + 2 F +

Qdep = MS + 2 F + 2 F Cox

MS is the difference between the work functions of the polysilicon gate and the silicon substrate F is the Fermi potential, F = kT N sub ln q n i

Qdep is the depletion region charge, Qdep = 4q si F N sub Cox is the gate cap/area, Cox =

ox
tox

Note, will be defined later

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TAMU-474-09

J. Silva-Martinez

MOS Transistor
Accumulation: Two diodes back to back D-S current is zero
B VS=0 VG<0 VD>0 B P+ substrate N+ P
++++++++++

N-type transistor
D G

N+ S

P+

Inversion: Channel is connecting D and S D-S current is possible

B VS=0 VG>0 VD>0

Under this condition, there are 3 possible applications: Subthreshold (extremely low-voltage lowpower applications) Linear region (voltage controlled resistor, linear OTAs, multipliers, switches) Saturation region (Amplifiers)

P+ Substrate

N+ P

---------IDS

N+ Quasi free electrons N+

-8-

TAMU-474-09

J. Silva-Martinez

MOS Transistor
Triode Region (D-S channel is complete)
B VS=0 VG>0 VD ~ 0 B P+ substrate N+ P

N-type transistor
D G

----------

N+ S

Channel Saturation Region (D-S channel is incomplete)

B VS=0 VG>0 VD > 0

In this condition, there are 3 possible applications: Subthreshold (extremely low-voltage lowpower applications) Linear region (voltage controlled resistor, linear OTAs, multipliers, switches) Saturation region (Amplifiers)

P+ substrate

N+ P

N+

N-channel
-9-

TAMU-474-09

J. Silva-Martinez

MOS Transistor
Subthreshold (weak inversion)
B VS=0 VT >VG>0 VD>0

N-type transistor
IDS Linear region VGS3
Saturation

P+ substrate

N+ P (NA)

--------

N+ Subthreshold

VGS2

Mobile carriers concentration< NA Saturation (Strong inversion)

B VS=0 VG>VT VD>0

VGS1 VD
S

Subthreshold (extremely low-voltage lowpower applications) Linear region (voltage controlled resistor, linear OTAs, multipliers, switches) Saturation region (Amplifiers)

P+ substrate

N+ P (NA)

--------

N+

Mobile carriers Concentration> NA

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MOS Equations in Triode Region (Small VDS)

[Sedra/Smith]
Current from Source to Drain : I = dQ dQ dx = = Qd ( x) dt dx dt

Incremental Charge Density : Qd ( x) = COX W (VGC ( x ) VT ) Gate - to - Channel Voltage : VGC ( x ) VT = VGS VCS ( x) VT Electron Velocity : = n E ( x ) = n I DS = I = COX W (VGS VCS ( x) VT ) n dv( x ) dx dv( x ) dx

I
0

DS

dx =

VDS

C
n 0

OX

W (VGS VT VCS ( x))dv( x )

I = I DS
Capacitance per unit gate area : Cox = Electron mobility : n

I DS = nCOX

ox
t ox

1 W VGS VT VDS VDS 2 L

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Triode or Linear Region

[Silva]

VDS

V (0 ) = 0

x=0

V ( x ) = VDS

VGC ( x ) = VGS V ( x ) = VGS VDS

x L

V (L ) = VDS

x=L

Channel depth and transistor current is a function of the overdrive voltage, VGS-VT, and VDS Because VDS is small, VGC is roughly constant across channel length and channel depth is roughly uniform
I DS = W nCOX (VGS VTn 0.5VDS )VDS L
RDS 1

x L

For small VDS

W Cox (VGS VTn ) L

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TAMU-474-09

J. Silva-Martinez

MOS Equations in Linear Region

GND tox
N+

VGS

VDS

Drain current: Expression used in SPICE level 1

ID =

W n C OX (VGS VT 0.5VDS )VDS L

N+

ID

L VGS

Linear approximation

GND tox
N+

VDS

IDSAT

N+

VGS > VT VDS VDSAT

Non-linear channel
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Triode Region Channel Profile

[Sedra/Smith]

VGC ( x ) = VGS V ( x ) = VGS VDS

x L

If VGC is always above VT throughout the channel length, the transistor current obeys the triode region current equation
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Saturation Region Channel Profile

VGC ( x ) = VGS V ( x ) = VGS VDS x L

When VDS VGS-VT=VOV, VGC no longer exceeds VT, resulting in the channel pinching off and the current saturating to a value that is no longer a function of VDS (ideally)

[Sedra/Smith]
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Saturation Region
[Silva]

VDSsat=VGS-VT

VDS-VDSsat

VGC ( x ) = VGS V ( x ) = VGS VDS

x L

V (0 ) = 0

x=0

V ( x ) = VDS

x L

V (L ) = VDS

x=L

Channel pinches-off when VDS=VGS-VT and the current saturates After channel charge goes to 0, the high lateral field sweeps the carriers to the drain and drops the extra VDS voltage
I DS = nCOX W V VGS VTn DS VDS 2 VDS =VGS VTn L VDSsat = VGS VTn

I DS =

nCOX W
2 L

(VGS VTn )2
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NMOS ID VDS Characteristics

VOV = VGS VTN
[Sedra/Smith]

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MOS Large-Signal Output Characteristic

[Sedra/Smith]

Note: Vov=VGS-VT

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What about the PMOS device?

NMOS PMOS [Silva]

The current equations for the PMOS device are the same as the NMOS EXCEPT you swap the current direction and all the voltage polarities
NMOS
W nCOX (VGS VTn 0.5VDS )VDS L W nCOX (VGS VTn )2 Saturation: I DS = 2L

PMOS
I SD =

Linear: I DS =

W p COX VSG VTp 0.5VSD VSD L 2 W I SD = p COX VSG VTp 2L

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PMOS ID VSD Characteristics

VOV = VSG VTP
[Karsilayan]

(Saturation)

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Body Effect
[Razavi]

If the body and source potential are equal, a certain VG=VT0 is required to form an inversion layer
VT 0 = MS + 2 F + Qdep 0 = MS + 2 F + 2 F Cox

VT = VT 0 +

2 F + VSB 2 F

Body effect coefficient, =

2q si N sub Cox

typically ranges from 0.3 to 0.4V1 2

As VS becomes positive w.r.t. VB, a larger depletion region forms, which requires a higher VG to form a channel The net result is that VT increases due to this body effect Note, it also works in reverse, as if you increase VB w.r.t. VS, then VT lowers
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TAMU-474-08

J. Silva-Martinez

MOS MODEL: SPICE LEVEL-II

NMOS : I DS = W nCOX (VGS VTn 0.5VDS )VDS L

Drain current, Triode region

PMOS : I SD =

W pCOX VSG VTp 0.5VSD VSD L

Drain Current, Saturation region

NMOS : I DS =
PMOS : I SD

W 2 nCOX (VGS VTn ) 2L 2 W = pCOX VSG VTp 2L

Threshold voltage (zero bias)

VT 0 = MS + 2 F + 2 F

Threshold voltage

VT = VT 0 +

2 F + VSB 2 F VT 0 VSB =0

KP and (Spice Model)

KP = COX ; =

2q si N sub COX

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Subthreshold Region
So far we have assumed that ID=0 when VGS<VT However, in reality an exponentially decreasing current exists for VGS<VT
V q In subthreshold region : I D = I 0 exp GS kT where I 0 is a scale current

> 1 is a nonideality factor

The steepest subthreshold slope is 1dec./60mV with = 1

[Razavi]

VT values are often set by extrapolating above threshold data to current values of zero or infinite Ron A rough value often used is the VGS which yields ID/W=1A/m

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Subthreshold Current & VT Scaling

This subthreshold current prevents lowering VT excessively Assuming VT=300mV and has an 80mV subthreshold slope, then the Ion/Ioff ratio is only on the order of 10^(300/80)=5.6e3 Reducing VT to 200mV drops the Ion/Ioff ratio to near 316 If we have a large number of off transistors on our chip these subthreshold currents add up quickly, resulting in significant power dissipation This is a huge barrier in CMOS technology scaling and one of the main reasons Vdd scaling has slowed
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