Instruction Set Architectures

The ARM processor architecture provides support for the 32-bit ARM and 16-bit Thumb Instruction Set Architectures (ISAs) along with architecture extensions to provide support for Java acceleration (Jazelle), security (TrustZone), SIMD, and NEON technologies. The ARM architecture supports implementations across a wide range of performance points. It is established as the dominant architecture in many market segments. The architectural simplicity of ARM processors leads to very small implementations, and small implementations mean devices can have very low power consumption. Implementation size, performance, and very low power consumption are key attributes of the ARM architecture. The ARM architecture is a Reduced Instruction Set Computer (RISC) architecture, as it incorporates these typical RISC architecture features:

Large uniform register file Load/store architecture, where data-processing operations only operate on register contents, not directly on memory contents Simple addressing modes, with all load/store addresses being determined from register contents and instruction fields only.

In addition, the ARM architecture provides:

Instructions that combine a shift with an arithmetic or logical operation Auto-increment and auto-decrement addressing modes to optimize program loops Load and Store Multiple instructions to maximize data throughput Conditional execution of almost all instructions to maximize execution throughput.

These enhancements to a basic RISC architecture enable ARM processors to achieve a good balance of high performance, small code size, low power consumption, and small silicon area. The ARM Instruction Architecture is constantly improving to meet the increasing demands of leading edge applications developers, while retaining the backwards compatibility necessary to protect investment in software development. ARM uses the Universal Assembly Language to provide a canonical form for all ARM and Thumb instructions. This allows the user to write assembly code which can be assembled for either instruction set.

ARM The ARM 32-bit instruction set is the base 32-bit ISA used in the ARMv4T, ARMv5TEJ and ARMv6 architectures. In these architectures it is used in applications requiring high performance, or for handling hardware exceptions such as interrupts and processor start-up. The ARM 32-bit ISA is also supported in the Cortex-A and Cortex-R profiles of the Cortex architecture for performance critical applications, and for legacy code. Most of its functionality is subsumed into the Thumb-2 instruction set, which also benefits from improved code density. ARM instructions are 32-bits wide, and are aligned on 4-byte boundaries. All ARM instructions can also be "conditionalised" to only execute when previous instructions have set a particular condition code. This means that instructions only have their normal effect on the programmers model operation, memory and coprocessors if the N, Z, C and V flags in the Application Program Status Register satisfy a condition specified in the instruction. If the flags do not satisfy this condition, the instruction acts as a NOP, that is, execution advances to the next instruction as normal, including any relevant checks for exceptions being taken, but has no other effect. This conditionalisation of instructions allows small sections of if- and while-statements to be encoded without the use of branch instructions. The condition codes are: Condition Code N Z C V Meaning Negative condition code, set to 1 if result is negative Zero condition code, set to 1 if the result of the instruction is 0 Carry condition code, set to 1 if the instruction results in a carry condition Overflow condition code, set to 1 if the instruction results in an overflow condition.

THUMB With cost-sensitive embedded control applications such as cell phones, disk drives, modems and pagers all hitting the performance ceilings of their current generation CISC controllers, designers are looking for ways to achieve 32-bit performance and address space but without the costs associated with going to a 32-bit system.

Thumb offers the designer

Excellent code-density for minimal system memory size and cost 32-bit performance from 8- or16-bit memory on an 8- or 16-bit bus for low system cost. Plus the established ARM features Industry-leading MIPS/Watt for maximum battery life and RISC performance Small die size for integration and minimum chip cost Global multi-partner sourcing for secure supply.

Thumb technology is an extension to the 32-bit ARM architecture. The Thumb instruction set features a subset of the most commonly used 32-bit ARM instructions which have been compressed into 16-bit wide opcodes. On execution, these 16-bit instructions are decompressed transparently to full 32-bit ARM instructions in real time without performance loss. Designers can use both 16-bit Thumb and 32-bit ARM instructions sets and therefore have the flexibility to emphasise performance or code size on a sub-routine level as their applications require. A "Thumb-aware" core is a standard ARM processor fitted with a Thumb decompressor in the instruction pipeline. The designer therefore gets all the underlying power of the 32-bit ARM architecture as well as excellent code density from Thumb, all at 8-bit system cost. Thumb has better code density than common 8 and 16-bit CISC/RISC Controllers and is at a fraction of the code size of traditional 32-bit architectures. This means that program memory can be smaller and hence cost reduced. The Thumb architecture is supported by a complete Windows software development environment as well as development and evaluation cards. THUMB-2

Improved Code Density with Performance and Power Efficiency

Thumb-2 technology is the instruction set underlying the ARM Cortex architecture which provides enhanced levels of performance, energy efficiency, and code density for a wide range of embedded applications. Thumb-2 technology builds on the success of Thumb, the innovative high code density instruction set for ARM microprocessor cores, to increase the power of the ARM microprocessor core available to developers of low cost, high performance systems. The technology is backwards compatible with existing ARM and Thumb solutions, while significantly extending the features available to the Thumb instructions set. This allows more of the application to benefit from the best in class code density of Thumb. For performance optimised code Thumb-2 technology uses 31 percent less memory to reduce system cost, while providing up to 38 percent higher performance than existing high density code, which can be used to prolong battery-life or to enrich the product feature set. Thumb-2 technology is featured in the processor, and in all ARMv7 architecture-based processors.
http://www.arm.com/products/processors/technologies/instruction-set-architectures.php

Why Cortex-M3
Delivering higher performance and richer features Introduced in 2004 and recently updated with new technologies and configurability, the Cortex-M3 is the mainstream ARM processor developed specifically with microcontroller applications in mind. Performance and Energy Efficiency With high performance and low dynamic power consumption the Cortex-M3 processor delivers leading power efficiency 12.5 DMIPS/mW based on 90nmG. Coupled with integrated sleep modes and optional state retention capabilities the Cortex-M3 processor ensures there is no compromise for applications requiring low power and excellent performance. Full featured The processor executes Thumb-2 instruction set for optimal performance and code size, including hardware division, single cycle multiply, and bit-field manipulation. The Cortex-M3 NVIC is highly configurable at design time to deliver up to 240 system interrupts with individual priorities, dynamic reprioritization and integrated system clock. Rich connectivity The combination of features and performance enables Cortex-M3 based devices to efficiently handle with multiple I/O channels and protocol standards such as USB OTG (On-The-Go).