I C Passive Comp

IC Passive Components (1/13/00)
Page 1 -1
INTEGRATED CIRCUIT PASSIVE COMPONENTS

INTRODUCTION Objective The objective of this presentation is: 1.) Show the passive components that are compatible with BJT and CMOS technologies 2.) Modifications to the standard BJT and CMOS processes 3.) Physical influence on passive components Outline Capacitors Resistors Inductors Modifications to the standard BJT and CMOS processes Diodes Summary
ECE 6421 - Analog IC Design
P.E. Allen and J.A. Connelly 2000
Page 1 -2
INTEGRATED CIRCUIT CAPACITORS PN Junction Concept:

Metallurgical Junction p-type semiconductor n-type semiconductor
iD
+vD Depletion region p-type semiconductor n-type semiconductor
iD
vD + xd xp 0 xn x
1. Doped atoms near the metallurgical junction lose their free carriers by diffusion. 2. As these fixed atoms lose their free carriers, they build up an electric field which opposes the diffusion mechanism. 3. Equilibrium conditions are reached when: Current due to diffusion = Current due to electric field
Page 1 -3
PN Junction Characterization Cross section of an ideal pn junction:

xd xp
p-type semiconductor
Impurity concentration (cm-3) ND
xn
n-type semiconductor
0 -NA
iD
Depletion charge concentration (cm-3)

+vD -
qND xp 0 -qNA Electric Field (V/cm) x E0 Potential (V) 0 vD xd xn x
x
Fig. 2.3-2A
Page 1 -4
Summary of PN Junction Analysis Barrier potentialkT NAND NAND o = B = ln = V ln t n2 q ni2 i Depletion region widthsxn = xp = 2si(o-vD)NA qND(NA+ND) 2si(o-vD)ND qND(NA+ND)
1 N
Depletion capacitanceCj = A siqNAND 2(NA+ND) 1 o-vD = Cj0 vD 1- o

Fig. 2.3-3B
Cj Cj0 0
0 vD
Breakdown voltagesi(NA+ND) 1 2 BV = E max N 2qNAND
Page 1 -5
Summary of PN Junction Analysis - Continued Graded junction:

Impurity Concentration (cm-3) ND x 0 NA
PC00
Above expressions become: Depletion region widths 2si(o-vD)NA m x n = qN (N +N ) D A D 2si(o-vD)ND m x p = qN (N +N ) D A D
3 1 m x N 2.5 2
Cj Depletion capacitance1.5 Cj0 Cj0 1 siqNAND m 1 = Cj = A2(N +N ) v D m A D ( o-vD) m 1 0.5 o
m=0.333 m=0.5
where 0.33 m 0.5. (Note that m = MJ)
-10
-8
-6
-4 vD 0
-2
2
PC01A
Page 1 -6
Summary of PN Junction Analysis - Continued Current-Voltage Relationship2 -VGO vD Dppno D n n p o qAD ni 3 iD = Isexp - 1 where I = qA + = KT exp s Ln L N Vt Lp Vt
25 20
iD 15 Is 10
5 0 -5
-4
-3
-2
-1
vD/Vt
10 x1016 8 x1016
16 iD 6 x10 Is 4 x1016
2 x1016 0 -40 -30 -20 -10 0 vD/Vt 10 20 30 40
Page 1 -7
Cross-Section of an NPN BJT All passive components must be compatible with this structure.
Substrate p Collector Base

Emitter n+ p n-epitaxial layer n+ n+ buried layer p- substrate
Heavily Doped p Lightly Doped p Intrinsic Doping Lightly Doped n Heavily Metal Doped n BJTNPN
Page 1 -8
Collector-Base Capacitance (C ) Illustration:

Substrate p
Model:
C CCB = C B

Collector Base p n+ n-epitaxial layer n+ buried layer p- substrate
Sidewall contribution:
Asidewall = Pd 2
where
PC02
CCS Substrate
P = perimeter of the capacitor d = depth of the diffusion
Values: Includes the bottom plus sidewall capacitance. C 1fF/m2 (dependent on the reverse bias voltage) Can also have base-emitter capacitance and collector-substrate capacitance
Page 1 -9
MOS Capacitors Polysilicon-Oxide-Channel for Enhancement MOSFETs Bulk connected to V SS

G D,S VDG =VGS >V T Gate VGS>VT Source p+ pSubstrate/Bulk n+
Poly Channel
VSS VSS
Bulk
CGS
Drain n+
Comments: Capacitance = CGS CoxWL Channel must be formed, therefore VGS > VT With VGS > VT and VDS = 0, the transistor is in the active region.
Page 1 -10
MOS Capacitors - Continued Bulk tuning of the polysilicon-oxide-channel capacitor (0.35m CMOS)
CG -0.65V CG vB VT 1.0 Volts or pF 0.8 0.6 0.4 0.2 0.0 -1.5 -1.4 -1.3 -1.2 -1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 vB (Volts)
Fig. 2.5-3
Cmax/Cmin 4
Page 1 -11
MOS Capacitors - Continued Bulk connected to Source-Drain

G D,S VDG =VGS >V T Gate VGS>VT Bulk p+ pSubstrate/Bulk Source n+
Poly Channel
CGS CGB
Drain n+
CG-D,S
CG-D,S = CGS(oxide) + CGB(depletion) Comments: Capacitance is more constant as a function of VG-D,S Still not a good capacitor for large voltage swings
CGS VT CBG
VG-D,S
Page 1 -12
MOS Capacitors - Continued Accumulation-Mode Capacitor12
Comments: 30% tuning range (Tuned by the voltage across the capacitor terminals) Q 25 for 3.1pF at 1.8 GHz (optimization leads to Qs of 200 or greater)

=
CG-D,S Source Oxide Drain
Polysilicon
Substrate
n+
Source n+
n+
p+
Channel
n-well
Fig. 2.5-4
T. Soorapanth, et. al., Analysis and Optimization of Accumulation-Mode Varactor for RF ICs, Proc. 1998 Symposium on VLSI Circuits, Digest of Papers, pp. 32-33, 1998.
2
R. Castello, et. al., A 30% Tuning Range Varactor Compatible with future Scaled Technologies, Proc. 1998 Symposium on VLSI Circuits, Digest of Papers, pp. 34-35, 1998.
Page 1 -13
MOS Capacitors - Continued Polysilicon-Oxide Diffusion/Active for Enhanced MOSFETs

A A IOX FOX poly n-active n-well p-substrate poly IOX B IOX FOX B
n-active n-well p-substrate
Unit capacitance 1.2 fF/m2 Voltage dependence: C(V) C(0) + a1V + a2V2, where a1 0 and a2 210 ppm/V2 (Not as good linearity as poly-poly capacitors)
Page 1 -14
MOS Capacitors - Continued Polysilicon-Oxide-Polysilicon (Poly-Poly)

A IOX IOX FOX substrate
Polysilicon II Polysilicon I
IOX FOX
Best possible capacitor for analog circuits Less parasitics Voltage independent Approach for increasing the voltage linearity:
Top Plate Bottom Plate Top Plate Bottom Plate
Page 1 -15
Implementation of Capacitors using Available Metal and Poly Interconnect Layers

M3 M2 B M1 Poly M3 T M2 M1 B T T
M2 B M1 Poly T
M2 M1 B
Fig. 2.5-8
Page 1 -16
Fractal Capacitors Capacitance between conductors on the same level and use lateral flux..
Fringing Capacitance
Top View of a Lateral Flux Capacitor
PC10
These capacitors are called fractal capacitors because the fractal patterns are structures that enclose a finite area with an infinite perimeter. In certain cases, the capacitor/area can be increased by a factor of 10 over vertical flux capacitors.
Page 1 -17
Capacitor Errors 1.) Oxide gradients 2.) Edge effects 3.) Parasitics 4.) Voltage dependence 5.) Temperature dependence
Page 1 -18
Capacitor Errors - Oxide Gradients Error due to a variation in oxide thickness across the wafer.
No common centroid layout Common centroid layout
A1
A2
A1
A2
y x1 x2 x1
Only good for one-dimensional errors. An alternate approach is to layout numerous repetitions and connect them randomly to achieve a statistical error balanced over the entire area of interest.
A C B B A C C B A A C B B A C C B A A C B B A C C B A
0.2% matching of poly resistors was achieved using an array of 50 unit resistors.
Page 1 -19
Capacitor Errors - Edge Effects There will always be a randomness on the definition of the edge. However, etching can be influenced by the presence of adjacent structures. For example,
Matching of A and B are disturbed by the presence of C.
C A B
Improved matching achieve by matching the surroundings of A and B.
C A B
Page 1 -20
Capacitor Errors - Area/Periphery Ratio The best match between two structures occurs when their area-to-periphery ratios are identical. Let C1 = C1 C1 and C2 = C2 C2 where C = the actual capacitance C = the desired capacitance (which is proportional to area) C = edge uncertainty (which is proportional to the periphery) Solve for the ratio of C2/C1,
C2 1 C2 C2 C 2 C 2 C2 C1 = C 1 C 1 = C1 C 1 1 C
1
C 2 C C C C C2 - C 1 C2 1 C 2 + - C 1 C 1 C 1 + 1 2 1 1 2 1 C2 C1 C 2 C 2 If C = C , then C = C 2 1 1 1
Therefore, the best matching results are obtained when the area/periphery ratio of C2 is equal to the area/periphery ratio of C1.
Page 1 -21
Capacitor Errors - Relative Accuracy Capacitor relative accuracy is proportional to the area of the capacitors and inversely proportional to the difference in values between the two capacitors. For example,
0.04 Unit Capacitance = 0.5pF Relative Accuracy 0.03 Unit Capacitance = 1pF 0.02
0.01 Unit Capacitance = 4pF 0.00 1 2 4 8 16 Ratio of Capacitors 32 64
Page 1 -22
Capacitor Errors - Parasitics Parasitics are normally from the top and bottom plate to ac ground which is typically the substrate.
Top Plate Top plate parasitic Desired Capacitor Bottom plate parasitic
Bottom Plate
Top plate parasitic is 0.01 to 0.001 of Cdesired Bottom plate parasitic is 0.05 to 0.2 Cdesired
Page 1 -23
Other Considerations on Capacitor Accuracy Decreasing Sensitivity to Edge Variation:

A B A' B' B Sensitive to edge varation in upper plate only. A A' B'
Fig. 2.6-13
Sensitive to edge variation in both upper andlower plates
A structure that minimizes the ratio of perimeter to area (circle is best).
Top Plate of Capacitor
Bottom plate of capacitor
Fig. 2.6-14
Page 1 -24
Capacitor Errors - Temperature and Voltage Dependence Polysilicon-Oxide-Semiconductor Capacitors Absolute accuracy 10% Relative accuracy 0.2% Temperature coefficient +25 ppm/C Voltage coefficient -50ppm/V Polysilicon-Oxide-Polysilicon Capacitors Absolute accuracy 10% Relative accuracy 0.2% Temperature coefficient +25 ppm/C Voltage coefficient -20ppm/V Accuracies depend upon the size of the capacitors.
Page 1 -25
Capacitor Layout
Double-polysilicon capacitor
Metal FOX Substrate Polysilicon 2
Triple-level metal capacitor.

Metal 3 Metal 2 Metal 1
Polysilicon 2
Cut
,,,, ,,,, ,,,, ,,,, ,,,, ,,,,

Polysilicon gate
FOX Substrate Metal 3 Metal 2 Metal 1 Metal 3 Via 2
Polysilicon gate
Via 2 Cut Metal 1 Metal 1

Fig. 2.6-17
Metal 2 Via 1
Page 1 -26
INTEGRATED CIRCUIT RESISTORS Resistor Layout

Direction of current flow
W T Area, A L
Fig. 2.6-15
Resistance of a conductive sheet is expressed in terms of L L R = A = W T ( ) where = resistivity in -m Ohms/square: L L R= = S W ( ) T W where
S is a sheet resistivity and has the units of ohms/square
Page 1 -27
Base and Emitter Diffused Resistors Cross-section of a Base Resistor:

Substrate p Collector
Comments:
Sheet resistance 100 / TCR = +1500ppm/C Note: 1% 104 = C C Emitter Resistor: Sheet resistance 52 / area) TCR = +600ppm/C

A B A n+ p n-epitaxial layer Cj 2 p- substrate n+ buried layer
RAB Cj 2 Collector
PC03
to 200 /
to 10 /
(Generally too small to make sufficient resistance in reasonable
Page 1 -28
Base Pinched Resistor Good for large value of sheet resistance. Cross-section:
Substrate p A
IV Curves and Model:

B p n+ n-epitaxial layer n+ p- substrate
PC06
iAB
Pinched operation
RAB
vAB
Collector
PC05
Comments: Sheet resistance is 5 to 15k/ Voltage across the resistor is limited to 6V or less because of breakdown TCR 2500ppm/C
Page 1 -29
Epitaxial Pinched Resistors Cross section:

Substrate p
Sheet resistance 1-10k/ Top View:

A B p n+ n-epitaxial layer p- substrate
PC06
PC07
Page 1 -30
MOS Resistors - Source/Drain Resistor

Metal SiO2 p+
FOX
n- well p- substrate
FOX
Fig. 2.5-16
Diffusion: 10-100 ohms/square Absolute accuracy = 35% Relative accuracy = 2% (5 m), 0.2% (50 m) Temperature coefficient = +1500 ppm/C Voltage coefficient -200 ppm/V
Ion Implanted: 500-2000 ohms/square Absolute accuracy = 15% Relative accuracy = 2% (5 m), 0.15% (50 m) Temperature coefficient = +400 ppm/C Voltage coefficient -800 ppm/V
Comments: Parasitic capacitance to well is voltage dependent. Piezoresistance effects occur due to chip strain from mounting.
Page 1 -31
Polysilicon Resistor
Metal
,,
,,,,,
Polysilicon resistor
FOX
p- substrate
Fig. 2.5-17
30-100 ohms/square (unshielded) 100-500 ohms/square (shielded) Absolute accuracy = 30% Relative accuracy = 2% (5 m) Temperature coefficient = 500-1000 ppm/C Voltage coefficient -100 ppm/V Comments: Used for fuzes and laser trimming Good general resistor with low parasitics
Page 1 -32
N-well Resistor
Metal n+
FOX
n- well p- substrate
FOX
FOX
Fig. 2.5-18
1000-5000 ohms/square Absolute accuracy = 40% Relative accuracy 5% Temperature coefficient = 4000 ppm/C Voltage coefficient is large +8000 ppm/V Comments: Good when large values of resistance are needed. Parasitics are large and resistance is voltage dependent
Page 1 -33
Example of Resistor Layouts

Metal
FOX FOX FOX
Metal
FOX FOX
Substrate Active area (diffusion) Contact Active area or Polysilicon W
Substrate Active area (diffusion) Well diffusion Active area Contact Cut Well diffusion W
Cut L
Metal 1
Metal 1
Fig. 2.6-16
Diffusion or polysilicon resistor
Well resistor
Corner corrections:
0.5
1.45
1.25
Fig. 2.6-16B
Page 1 -34
Example 2.6-1 Resistance Calculation Given a polysilicon resistor like that drawn above with W=0.8m and L=20m, calculate s (in /u ), the number of squares of resistance, and the resistance value. Assume that for polysilicon is 9 10-4 cm and polysilicon is 3000 thick. Ignore any contact resistance. Solution First calculate s. 9 10 -4 - c m s = T = = 30 /u 3000 10 -8 c m The number of squares of resistance, N, is 20m L N = W = 0.8m = 25 giving the total resistance as R = s = 30 25 = 750
Page 1 -35
Integrated Circuit Passive Component Performance Summary Component Type Poly-oxide-semiconductor Capacitor Poly-Poly Capacitor Base Diffused Emitter Diffused Base Pinched Epitaxial Pinched Source/Drain Diffused Ion Implanted Resistor Poly Resistor n-well Resistor Thin Film Range of Values 0.35-1.0 fF/m2 0.3-1.0 fF/m2 100-200/sq. 2-10/sq. 2k-10k/sq. 2k-5k/sq. 10-100 /sq. 0.5-2 k/sq. 30-200 /sq. 1-10 k/sq. 0.1k-2k/sq. Absolute Relative Accuracy Accuracy 10% 20% 20% 20% 50% 50% 35% 15% 30% 40% 0.1% 0.1% 0.2% 2% 10% 7% 2% 2% 2% 5% Temperature Coefficient 20ppm/C 25ppm/C +1750ppm/C +600ppm/C +2500ppm/C +3000ppm/C 1500ppm/C 400ppm/C 1500ppm/C 8000ppm/C 10 to 200ppm/C Voltage Coefficient 20ppm/V 50ppm/V Poor Poor -200ppm/V -800ppm/V -100ppm/V -10kppm/V -
5-20% 0.2-2%
Page 1 -36
INDUCTORS Inductors What is the range of values for on-chip inductors?

12 10 8 6 4 2
,,,,,, ,,,,,,
Inductor area is too large L = 50 Interconnect parasitics are too large 0 0 10 20 30 40 Frequency (GHz) 50
Inductance (nH)
Fig. 6-5
Consider an inductor used to resonate with 5pF at 1000MHz. 1 1 = 5nH L= 2 2 = 4 fo C (2109)25x10-12 Note: Off-chip connections will result in inductance as well.
Page 1 -37
Candidates for inductors in CMOS technology are: 1.) Bond wires 2.) Spiral inductors 3.) Multi-level spiral 4.) Solenoid Bond wire Inductors:
d
Fig.6-6
Function of the pad distance d and the bond angle Typical value is 1nH/mm which gives 2nH to 5nH in typical packages Series loss is 0.2 /mm for 1 mil diameter aluminum wire Q 60 at 2 GHz
Page 1 -38
Planar Spiral Inductors Spiral Inductors on a Lossy Substrate:
L C1 R1
R C2 R2
Fig. 16-7
Design Parameters: Inductance, L = (Lself + Lmutual) Quality factor, Q =
L R
1 Self-resonant frequency: fself = LC Trade-off exists between the Q and self-resonant frequency Typical values are L = 1-8nH and Q = 3-6 at 2GHz
Page 1 -39
Planar Spiral Inductors - Continued Inductor Design

I W
ID
,,,,,
SiO2
Silicon Fig. 6-9
S I Nturns = 2.5
Typically: 3<Nturns <5 and S = Smin for the given current Select the OD, Nturns, and W so that ID allows sufficient magnetic flux to flow through the center. Loss Mechanisms: Skin effect Capacitive substrate losses Eddy currents in the silicon
Page 1 -40
Planar Spiral Inductors - Continued Influence of a Lossy Substrate

L C1 R1 R C2 R2
Fig. 12.2-13
CLoad
where: L is the desired inductance R is the series resistance C1 and C2 are the capacitance from the inductor to the ground plane R1 and R2 are the eddy current losses in the silicon Guidelines for using spiral inductors on chip: Lossy substrate degrades Q at frequencies close to fself To achieve an inductor, one must select frequencies less than fself The Q of the capacitors associated with the inductor should be very high
Page 1 -41
Planar Spiral Inductors - Continued Comments concerning implementation: 1.) Put a metal ground shield between the inductor and the silicon to reduce the capacitance. Should be patterned so flux goes through but electric field is grounded Metal strips should be orthogonal to the spiral to avoid induced loop current The resistance of the shield should be low to terminate the electric field 2.) Avoid contact resistance wherever possible to keep the series resistance low. 3.) Use the metal with the lowest resistance and furtherest away from the substrate. 4.) Parallel metal strips if other metal levels are available to reduce the resistance. Example:
Fig. 6-10
Page 1 -42
Multi-Level Spiral Inductors Use of more than one level of metal to make the inductor. Can get more inductance per area Can increase the interwire capacitance so the different levels are often offset to get minimum overlap. Multi-level spiral inductors suffer from contact resistance (must have many parallel contacts to reduce the contact resistance)
Page 1 -43
Solenoid Inductors Example:
Upper Metal
,, ,,,,,,,, ,,
e Curr l i o C Coil Cur
nt
Contact Vias rent
Magnetic Flux
Lower Metal
SiO2
Silicon
Fig. 6-11
Comments: Magnetic flux is small due to planar structure Capacitive coupling to substrate is still present Potentially best with a ferromagnetic core
Page 1 -44
OTHER CONSIDERATIONS OF CMOS TECHNOLOGY Lateral Bipolar Junction Transistor P-Well Process NPN LateralVDD Base Emitter Collector
n+
p+ p-well
n+
n+
n-substrate
Page 1 -45
Lateral Bipolar Junction Transistor - Continued Field-aided LateralF 50 to 100 depending on the process
Keep channel from forming VDD Base Emitter VGate Collector
n+
p+ p-well
n+
n+
n-substrate
Good geometry matching Low 1/f noise (if channel doesnt form) Acts like a phototransistor with good responsitivity
Page 1 -46
Geometry of the Lateral PNP BJT Minimum Size layout of a single emitter dot lateral PNP BJT:
n-well n-well contact p-diffusion contact p-substrate diffusion Base Lateral Collector Emitter 31.2 m
40 emitter dot LPNP transistor (total device area is 0.006mm2 in a 1.2m CMOS process):
71.4 m
Base V SS Lateral Collector V SS Emitter 33.0 m Gate (poly) 84.0 m
Gate
Page 1 -47
Performance of the Lateral PNP BJT Schematic:

Emitter Gate
Base Lateral Collector
Vertical Collector ( V SS )
L vs ICL for the 40 emitter dot LPNP BJT:

150
VCE = 4.0 V
Lateral efficiency versus IE for the 40 emitter dot LPNP BJT:

1.0
VCE = 4.0 V VCE = 0. 4V
130 Lateral Efficiency 100 A 1 mA Lateral
0.8
110
VCE = 0. 4V
0.6
90
0.4
70
0.2
50 1 nA
10 nA
100 nA 1 A 10 A Lateral Collector Current
0 1 nA
10 nA
100 nA 1 A 10 A Emitter Current
100 A
1 mA
Page 1 -48
Performance of the Lateral PNP BJT - Continued Typical Performance for the 40 emitter dot LPNP BJT: Transistor area Lateral Lateral efficiency Base resistance En @ 5 Hz En (midband) fc (En) In @ 5 Hz In (midband) fc (In) fT Early voltage 0.006 mm2 90 0.70 150 2.46 nV / Hz 1.92 nV / Hz 3.2 Hz 3.53 pA / Hz 0.61 pA / Hz 162 Hz 85 MHz 16 V
Page 1 -49
High Voltage MOS Transistor The well can be substituted for the drain giving a lower conductivity drain and therefore higher breakdown voltage. NMOS in n-well example:
Source
Gate
Oxide
Drain-substrate/channel can be as large as 20V or more.

Drain
Polysilicon
Substrate
n+ Source
Channel
n+
p+
n-well
p-substrate
Fig. 2.6-7A
Page 1 -50
Latch-up in CMOS Technology Latch-up Mechanisms 1. SCR regenerative switching action. 2. Secondary breakdown. 3. Sustaining voltage breakdown. Parasitic lateral PNP and vertical NPN BJTs in a p-well CMOS technology:
VDD D G S S G D
,, ,, ,, ,, ,, ,, ,,,,,,,,,, ,, ,, ,, ,, ,, ,, ,, ,, ,, ,, ,, ,, ,,,, | |
A B
VSS n+ p+ p+ p-well n+ n+ p+ RNRPn- substrate VDD VDD A Vin VSS B Vout B RPVSS VSS
Fig. 2.6-9 +
Fig. 2.6-8
Equivalent circuit of the SCR formed from the parasitic BJTs:

RN-
Page 1 -51
Preventing Latch-Up in a P-Well Technology 1.) Keep the source/drain of the MOS device not in the well as far away from the well as possible. This will lower the value of the BJT betas. 2.) Reduce the values of RN- and RP-. This requires more current before latch-up can occur. 3.) Make a p- diffusion around the p-well. This shorts the collector of Q1 to ground.
p-channel transistor n+ guard bars n-channel transistor p+ guard bars
VDD
VSS
FOX
FOX
FOX
FOX
FOX
p-well
FOX
FOX
n- substrate
Figure 2.6-10
For more information see R. Troutman, CMOS Latchup, Kluwer Academic Publishers.
Page 1 -52
Electrostatic Discharge Protection (ESD) Objective: To prevent large external voltages from destroying the gate oxide.
Electrical equivalent circuit VDD p+ to n-well diode To internal gates n+ to p-substrate diode p+ resistor
Bonding Pad
VSS Implementation in CMOS technology Metal
FOX
n+
FOX n-well
p+
FOX
p-substrate
Fig. 2.6-11
Page 1 -53
Temperature Characteristics of Transistors Fractional Temperature Coefficient 1 x Typically in ppm/C TCF = x T MOS Transistor V T = V(T0 ) + ( T-T 0 ) + , where -2.3mV/C (200K to 400K) = KT-1.5 BJT Transistor Reverse Current, IS: 1 I S 3 1 VG0 = + IS T T T kT/q Empirically, IS doubles approximately every 5C increase Forward Voltage, vD: V G0 - v D 3kT/q vD = - T -2mV/C at vD = 0.6V T
Page 1 -54
Noise in Transistors Shot Noise i2 = 2qIDf (amperes2) where q = charge of an electron ID = dc value of iD f = bandwidth in Hz i2 2 Noise current spectral density = f (amperes /Hz) Thermal Noise Resistor: v2 = 4kTRf (volts2) MOSFET: iD2 = where k = Boltzmanns constant R = resistor or equivalent resistor in which the thermal noise is occurring. gm = transconductance of the MOSFET 8kTgmf (ignoring bottom gate) 3
Page 1 -55
Noise in Transistors - Continued Flicker (1/f) Noise

Ia iD2 = Kf b f f
where Kf = constant (10-28 Faradamperes) a = constant (0.5 to 2) b = constant (1)

Noise power spectral density 1/f
log(f)
Fig. 2.6-12
Page 1 -56
Design Rules Design rules are geometrical constraints which guarantee the proper operation of a circuit implemented by a given CMOS process. These rules are necessary to avoid problems such as device misalignment, metal fracturing, lack of continuity, etc. Design rules are expressed in terms of minimum dimensions such as minimum values of: Widths Separations Extensions Overlaps Design rules typically use a minimum feature dimension called lambda. Lambda is usually equal to the minimum channel length. Minimum resolution of the design rules is typically half lambda. In most processes, lambda can be scaled or reduced as the process matures.
Page 1 -57
DIODES BJT Diode Different configurations
Diode
PC08A PC08B PC08C PC08D PC08E PC08F
Condition Series Resistance VF @10mA Breakdown Voltage Storage Time
IC = 0 rbb 960mV BVEBO 70ns
IE = 0 rbb+rcc 950mV BVCBO 130ns
IE =0 no emitter rbb+rcc 950mV BVCBO 80ns
V CB = 0 rbb/ 850mV BVEBO 6ns
V EB = 0 rbb/ + rcc' 940mV BVCBO 90ns
VCE = 0 rbb 920mV BVEBO 150ns
Page 1 -58
MOS Diode
PC09
iD = (v D -V T )2
Page 1 -59
Comparison of the BJT and MOS diodes Assume the Is = 1fA, o = 99 and VD = 0.65V for the BJT diodes and = 300A/V2 and VT = 0.5V for the MOS diode. Find the dc current, the static resistance, and the dynamic resistance of the BJT diode in the first and fourth columns and the MOS diode. IC=0 diode: IC 1fA 1fA ID = = 99 exp(0.65/0.026) = 99 (7.2x10+10) = 0.727A , 1 1 iD Isexp(0.65/0.026) ID = v = = = V t 35.7k V t rd D VCB=0 diode: IC 1+o ID = IE = IC+IB = = Isexp(0.65/0.026) = 72.7A , o Vt rd = I = 357 D MOS diode: ID = 300A/V2(0.65-0.5)2 = 6.75A, 0.65V 1 1 Rstatic = 6.75A = 100k , r d g = = 11.1k m 23006.75 0.65V Rstatic = 72.7A = 8.93k r d = 35.7k 0.65V Rstatic = 0.727A = 893k
Page 1 -60
SUMMARY Showed passive components that were compatible with silicon IC technology Capacitors are inherently the most accurate passive components Inductors are possible at frequencies in excess of 100Mhz Modifications to the standard active device include: - Lateral PNP transistor for a BJT technology - Lateral BJT with the base the well in CMOS technology - Substrate BJTs - High voltage transistors - Latch up - ESD protection in CMOS technology Diodes include BJT and CMOS (BJT diodes are more ideal)

I C Passive Comp

Caricato da

Informazioni sul documento

Titolo originale

Copyright

Formati disponibili

Condividi questo documento

Condividi o incorpora il documento

Opzioni di condivisione

Hai trovato utile questo documento?

Questo contenuto è inappropriato?

Copyright:

Formati disponibili

I C Passive Comp

Caricato da

Copyright:

Formati disponibili

IC Passive Components (1/13/00)

INTEGRATED CIRCUIT PASSIVE COMPONENTS

ECE 6421 - Analog IC Design

P.E. Allen and J.A. Connelly 2000

IC Passive Components (1/13/00)

INTEGRATED CIRCUIT CAPACITORS PN Junction Concept:

+vD Depletion region p-type semiconductor n-type semiconductor

ECE 6421 - Analog IC Design

P.E. Allen and J.A. Connelly 2000

IC Passive Components (1/13/00)

PN Junction Characterization Cross section of an ideal pn junction:

Impurity concentration (cm-3) ND

Depletion charge concentration (cm-3)

qND xp 0 -qNA Electric Field (V/cm) x E0 Potential (V) 0 vD xd xn x

ECE 6421 - Analog IC Design

P.E. Allen and J.A. Connelly 2000

IC Passive Components (1/13/00)

Depletion capacitanceCj = A siqNAND 2(NA+ND) 1 o-vD = Cj0 vD 1- o

Breakdown voltagesi(NA+ND) 1 2 BV = E max N 2qNAND

ECE 6421 - Analog IC Design

P.E. Allen and J.A. Connelly 2000

IC Passive Components (1/13/00)

Summary of PN Junction Analysis - Continued Graded junction:

Above expressions become: Depletion region widths 2si(o-vD)NA m x n = qN (N +N ) D A D 2si(o-vD)ND m x p = qN (N +N ) D A D

Cj Depletion capacitance1.5 Cj0 Cj0 1 siqNAND m 1 = Cj = A2(N +N ) v D m A D ( o-vD) m 1 0.5 o

where 0.33 m 0.5. (Note that m = MJ)

ECE 6421 - Analog IC Design

P.E. Allen and J.A. Connelly 2000

IC Passive Components (1/13/00)

2 x1016 0 -40 -30 -20 -10 0 vD/Vt 10 20 30 40

ECE 6421 - Analog IC Design

P.E. Allen and J.A. Connelly 2000

IC Passive Components (1/13/00)

ECE 6421 - Analog IC Design

P.E. Allen and J.A. Connelly 2000

IC Passive Components (1/13/00)

Collector-Base Capacitance (C ) Illustration:

P = perimeter of the capacitor d = depth of the diffusion

ECE 6421 - Analog IC Design

P.E. Allen and J.A. Connelly 2000

IC Passive Components (1/13/00)

MOS Capacitors Polysilicon-Oxide-Channel for Enhancement MOSFETs Bulk connected to V SS

ECE 6421 - Analog IC Design

P.E. Allen and J.A. Connelly 2000

IC Passive Components (1/13/00)

ECE 6421 - Analog IC Design

P.E. Allen and J.A. Connelly 2000

IC Passive Components (1/13/00)

MOS Capacitors - Continued Bulk connected to Source-Drain

ECE 6421 - Analog IC Design

P.E. Allen and J.A. Connelly 2000

IC Passive Components (1/13/00)

MOS Capacitors - Continued Accumulation-Mode Capacitor12

ECE 6421 - Analog IC Design

P.E. Allen and J.A. Connelly 2000

IC Passive Components (1/13/00)

MOS Capacitors - Continued Polysilicon-Oxide Diffusion/Active for Enhanced MOSFETs

n-active n-well p-substrate

ECE 6421 - Analog IC Design

P.E. Allen and J.A. Connelly 2000

IC Passive Components (1/13/00)

MOS Capacitors - Continued Polysilicon-Oxide-Polysilicon (Poly-Poly)

ECE 6421 - Analog IC Design