Chapter 1

Introduction and Analysis Methods

1.1 Switching Power Electronics
Read Chapter 1 of Principles of Power Electronics (KSV) by J. G. Kassakian, M.
F. Schlecht, and G. C. Verghese, Addison-Wesley, 1991.
Linear Regulator
io
+ Vx
+

+
Vin Vo

Figure 1.1: Linear Regulator
Control v
x
such that V
o
= V
o,REF
: Simple, accurate, high-bandwidth, but
1
2 CHAPTER 1. INTRODUCTION AND ANALYSIS METHODS
P
diss
= < v
x
i
o
> > 0 (1.1)
P
out
=
P
in
V
o
i
o
=
V
in
i
o
V
o
= (1.2)
V
in
@ V
in
= 15v, V
o
= 5v = 33% (1.3)
For eciency we will consider switching power converters:
q(t)

+
Vo Vin
0
1 q(t)
+ DT T
v(t)
<Vo> = dVin

Figure 1.2: Considering Switching Power Convertor
Add ltering:
NOTE: Only lossless elements. L, C (energy storage).
Use semiconductors as switches. Switches: Block V, carry I, but NOT at the same
time!
1.2. ANALYSIS TECHNIQUES 3

+
+
+

+
Vin Vo
Vx
v(t)
Vx
<Vo> ~ dVin
+
+
Vin Vo


Figure 1.3: Add Filtering
1.2 Analysis Techniques
1.2.1 Methods of Assumed States
Semiconductor switches are typically not fully controllable. Lets consider how to
analyze a switching circuit in time domain:
Simple Rectier
Example: (trivial but fundamental)
Vd
+
id
+
Vo
VsSin(t)

Figure 1.4: Simple Rectier
Diodes: Uncontrolled
Cannot sustain positive voltage (will turn on)
4 CHAPTER 1. INTRODUCTION AND ANALYSIS METHODS
Cannot sustain negative Current (will turn o)
id
Vd
Figure 1.5: Diode
The method of assumed states allows us to gure out which un/semi-controlled
switches are on as a function of time.
1. Assume a state (on/o) for all un/semi-controlled switches.
2. Calculate voltages and currents in the system (linear circuit theory).
3. See if any switch conditions are violated (e.g., on diode has negative current
and o diode has positive voltage.)
4. If no violations, then done, else if violation assume a new set of states go back
to step 1.
Vd
+
id
+
Vo
VsSin(t)

Figure 1.6: Simple Rectier
1.2. ANALYSIS TECHNIQUES 5
If V
s
sin(t) > 0 and we assume diode o: v
d
> 0, since this is not possible
diode must be on during this condition.
If V
s
sin(t) < 0 and we assume diode on: i
d
< 0, since this is not possible
diode must be o during this condition.
V
s
sin(t) > 0 diode on:
+
Vo
VsSin(t)

Figure 1.7: Simple Rectier with Diode On
V
s
sin(t) < 0 diode o:
+
Vo
VsSin(t)

Figure 1.8: Simple Rectier with Diode O
Vs

Vo
VsSin( t)
<Vo> =
t

2
i=(VsSin( t))/R
Figure 1.9: Rectier Waveform
Very simple example but principle works in general.
6 CHAPTER 1. INTRODUCTION AND ANALYSIS METHODS
1.2.2 Periodic Steady State
In power electronics we are often interested in the periodic steady state. In periodic
steady state the system returns to the same point at the end of cycle (beginning
matches end), so things are operating cyclicly.
In periodic steady state (P.S.S.):
di
V = L
dt
di
< V > = < L >
dt
di
= L < >
dt
di
since < >= 0 < V > = 0 (1.4)
dt

Therefore, in P.S.S.:
Inductor < V
L
>= 0 average
di
L
= 0
dt
Capacitor < V
C
>= 0 average
dV
dt
C
= 0
The P.S.S. conditions are useful for analysis. Consider adding a lter to smooth
the ripple current in our simple rectier:
VsSin( t)
+
Vo
VL
+ +
Vd
+
Vx




Figure 1.10: Simple Rectier with Filter
If we assume diode is always on in P.S.S., then:
1.2. ANALYSIS TECHNIQUES 7
VL
+
+
Vo
VsSin(t)

Figure 1.11: Simple Rectier with Filter and Diode On
V
s
sin(t) V
L
v
o
= 0
< V
s
sin(t) > = 0 in P.S.S.
< V
L
> = 0 in P.S.S.
v
o
= 0 (1.5)
If diode were always on < V
o
>= 0 and i
o
must be < 0 part of the time. We know
diode must turn o during part of cycle by the method of assumed states. What
happens:
VsSin( t)

2
t
io
Vx
Figure 1.12: Rectier with Filter Waveform
Negative voltage for part of cycle drives i 0. Exact analysis in KSV, Section
3.2.2. Good for review of time-domain analysis.
Main point: Method of assumed states and P.S.S. condition are useful tools to
determine system behavior.
8 CHAPTER 1. INTRODUCTION AND ANALYSIS METHODS
Now, in P.S.S. < V
x
>=< V
o
>, since < V
L
>= 0. < V
x
> is pos
1
2
sin plus some
neg
1
2
sin, so we lose some voltage as compared to a pos
1
2
sin.
Solution: Free-wheeling diode Half-wave Rectier.
Vd VL
+ - +
D1
io
+ +
Vo
VsSin(t) D2
Vx
-
-
Figure 1.13: Simple Rectier with Free Wheeling Diode
D
2
clamps so that V
x
never goes negative. i
o
free-wheels.
Using method of assumed states:
D
1
conducts when V
s
sin t > 0.
D
2
conducts when V
s
sin t < 0.
2
Io =
t

Vx
VsSin( t)
R
V0
Figure 1.14: Rectier with Free Wheeling Diode Waveform
< V
L
> = 0 in P.S.S.
< V
o
> = < V
x
>
=
1
2


0
V
s
sin()d

1.2. ANALYSIS TECHNIQUES 9
V
s
= (1.6)

NOTE: This circuit is rarely used in line applications today for several reasons,
but the analysis technique is the key point. Full-wave rectier is more common.
NOTE: For analyzing output current, output voltage, etc., we can do an equivalent-
source replacement. Linear circuit with sum of fourier sources.
io
Veq(t)
+
Vo
Veq(t)
-
t
Figure 1.15: Linear Circuit with Sum of Fourier Sources

V
eq
= B
n
cos(nt +
n
) (1.7)
n=0
v
o
()

If H() = V
o
= H(n) B
n
cos(nt +
n
+ < H(n)) (1.8)
v
x
()

n
| |
Main point: We can replace dicult to handle part of circuit with an equivalent
voltage source, then use linear circuit theory to analyze from there.
Summary of analysis thechniques:
Method of assumed states
Periodic Steady State
Equivalent source replacement
Chapter 2
Introduction to Rectiers
Read Chapter 3 of Principles of Power Electronics (KSV) by J. G. Kassakian, M.
F. Schlecht, and G. C. Verghese, Addison-Wesley, 1991.
Start with simple half-wave rectier (full-bridge rectier directly follows).
Ld
+
Id
Vx
D1
id
+ +
t
Vo
VsSin(t) D2
Vx
2

VsSin(t)
D1 ON D2 ON
Figure 2.1: Simple Half-wave Rectier
In P.S.S.:
< v
o
> = < v
x
>
v
s
= (2.1)

10
2.1. LOAD REGULATION 11
v
s
If L
d
Big i
d
I
d
=
R
(2.2)
If
L
R
d

2

we can approximate load as a constant current.
2.1 Load Regulation
.
Now consider adding some ac-side inductance L
c
(reactance X
c
= L
c
).
Common situation: Transformer leakage or line inductance, machine winding
inductance, etc.
L
c
is typically L
d
(lter inductance) as it is a parasitic element.
Lc Ld
D1
+
R
VsSin(t) D2
Vx

Figure 2.2: Adding Some AC-Side Inductance
Assume L
d
(so ripple current is small). Therefore, we can approximate load
as a special current source.
v
x
Special since < v
L
>= 0 in P.S.S. I
d
=< > (2.3)
R
Assume we start with D
2
conducting, D
1
o (V sin(t) < 0). What happens when
V sin(t) crosses zero?
12 CHAPTER 2. INTRODUCTION TO RECTIFIERS
i1
Lc
D1
VsSin(t) D2
i2
Id
Figure 2.3: Special Current
D
1
o no longer valid.
But just after turn on i
1
still = 0.
Therefore, D
1
switches from D
2
and D
2
to D
1
.
are both on d
Lc
uring a commutation period, where current
i1
D1
+
VsSin( t) D2 Vx
Id
_
i2
Figure 2.4: Commutation Period
D
2
will stay on as long as i
2
> 0 (i
1
< I
d
).
Analyze:
di
1
1
= V
s
sin(t)
dt L
c

t
V
s
i
1
(t) = sin(t)d(t)
0 L
c
V
s
0
=
L
c
cos()|
t
V
s
= [1 cos(t)] (2.4)
L
c
2.1. LOAD REGULATION 13
i1
u
Id
t
Figure 2.5: Analyze Waveform
Commutation ends at t = u, when i
1
= I
d
.
Commutation Period:
V
s
L
c
I
d
I
d
=
L
c
[1 cos u] cos u = 1
V
s
(2.5)
As compared to the case of no commutating inductance, we lose a piece of output
voltage during commutation. We can calculate the average output voltage in P.S.S.
from < V
x
>:
1


< V
x
> = V
s
sin()d
2 u
V
s
= [cos(u) + 1]
2
L
c
I
d
from before cos(u) = 1
V
s
X
c
I
d
= 1
V
s
V
s
L
c
I
d
< V
x
> = [1 ] (2.6)
V
s
So average output voltage drops with:
1. Increased current
14 CHAPTER 2. INTRODUCTION TO RECTIFIERS
u
VsSin(wt)
Vx
t
+u 2 2
i1
Id
t
u +u 2 +u
D1 D2
2
D1+D2
Figure 2.6: Commutation Period
2. Increased frequency
3. Decreased source voltage
We get the Ideal no L
c
case at no load.
We can make a dc-side thevenin model for such a system as shown in Figure 2.7.
No actual dissipation in box: resistance appears because output voltage drops
when current increases.
This Load Regulation is a major consideration in most rectier systems.
Voltage changes with load.
Max output power limitation
2.1. LOAD REGULATION 15
Id
+
<Vx>
<Vx>
Id
2
slope
2
Lc
Lc
2Vs
Lc

+


Vs


Vs
Figure 2.7: DC-Side Thevenin Model
All due to non-zero commutation time because of ac-side reactance.
occurs in most rectier types (full-wave, multi-phase, thyristor, etc.).
rectier has similar problem (similar analysis).
Read Chapter 4 of KSV.
This eect
Full-bridge
+ <Vx>
D3
D2
D1
D4
VsSin( t)
Lc
2Vs
FullBridge
Vs
Vx Id

1/2Bridge
Id
Vs 2Vs
Lc Lc

Figure 2.8: Full-Bridge Rectier
Chapter 3
Power Factor and Measures of
Distortion
Read Chapter 3 of Principles of Power Electronics (KSV) by J. G. Kassakian, M.
F. Schlecht, and G. C. Verghese, Addison-Wesley, 1991. Look at the AC side.
Denitions and Identities
Two functions X and Y are orthogonal over [a, b] if:
_
b
X(t)Y (t)dt = 0 (3.1)
a
Now:
_
2
sin(mt) sin(nt + )dt = 0, if n = m sinusoids of dierent frequencies
0

are orthogonal.
16
17
_
2

0
sin(t) cos(t)dt = 0 sine and cosine are orthogonal.
In general:
1
_
2
1
sin(t) sin(t + ) = cos (3.2)
2 0 2
These denitions will be useful for calculating power, etc.
Suppose we plug a resistor into the wall.
Rwire
Fuse
i
+
V RL
VsSin(t)

Figure 3.1: Resistor
P = < V i >
= V
RMS
i
RMS
= i
2
R (3.3)
RMS
The fuse is rated for a specic RMS current. Above that, it will blow so that
dissipation in R
wire
does not start a re. Neglecting R
wire
, for 115V
AC,RMS
, 15A
RMS
fuse, we get 1.7kW max from wall.
Suppose instead we plug an inductor into the wall.
Neglecting R
wire
:
_
_

_
18 CHAPTER 3. POWER FACTOR AND MEASURES OF DISTORTION
Rwire
Fuse
i
+
V L
VsSin(t)

Figure 3.2: Inductor
V
s
i =
L
cos(t) (3.4)
1
< P > = V (t)i(t)d(t)
2
V
2
=
s
sin(t) cos(t)d(t)
2L
= 0 (of course) (3.5)
Mathematically, it is because V and i are orthogonal. While we draw no real
power, we still draw current.
1
2
i
RMS
= i
2
(t)d(t)
2 0
V
s
= (3.6)
2L
@115V, 60Hz, L 20mH i
RMS
15A (3.7)
So we still will blow the fuse (to protect the wall wiring), even though we do not


_
19
draw any real power at the output! (some power dissipated in R
wire
). In this case we
are not utilizing the source well.
Power Factor
To provide a measure of the utilization of the source we dene Power Factor.
.
< P > Real Power
P.F. = = (3.8)
V
RMS
i
RMS
Apparent Power
For a resistor < P >= V
RMS
i
RMS
P.F. = 1 best utilization. For a inductor
< P >= 0 P.F. = 0 worst utilization.
Consider a rectier drawing some current waveform,
VsSin( t) V(t)
+
Rectifier
i(t)

Figure 3.3: Rectier
Express i(t) as a Fourier series:

i(t) = i
n
sin(nt +
n
) Sum of weighted shifted sinusoids (3.9)
n=0
1 1 1
Note: i
RMS
= i
1
2
+ i
2
2
+ + i
2
+
2 2

2
n

1
< P > = V (t)i(t)d(t)
2 2
_
_
_
20 CHAPTER 3. POWER FACTOR AND MEASURES OF DISTORTION
1

= V
s
sin(t) i
n
sin(nt +
n
)
2 2
n


1
= V
s
i
n
sin(t) sin(nt +
n
) (3.10)
2 2
n=0
By orthogonality all terms except fundamental drop out.
1
< P > = V
s
i
1
sin(t) sin(t +
1
)
2 2
V
s
i
1
= cos
1
2
= V
s,RMS
i
1,RMS
cos
1
(3.11)
So the only current that contributes to real power is the fundamental component
in phase with the voltage.
V
RMS
i
1,RMS
P.F. = cos
1
V
RMS
i
RMS
i
1,RMS
= cos
1
(3.12)
i
RMS
We can break down into two factors:
i
1,RMS
P.F. = ( ) cos
1
i
RMS

= k
d
(distortion factor) k

(displacement factor)
(3.13)
k
d
, distortion factor ( 1) tells us how much the utilization of the source is
reduced because of harmonic currents that do not contribute to power.






_


21
k

, displacement factor ( 1) tells us how much utilization is reduced due to

phase shift between the voltage and fundamental current.
Total Harmonic Distortion (THD)
Consider another measure of distortion: Total Harmonic Distortion (THD).
. n=1
i
n
2
THD =
_

(3.14)
i
2
1
This measure the RMS of the harmonics normalized to the RMS of the funda
mental (square root of the power ratio). Distortion factor and THD are related:

n=1
i
2
THD =
_
n
i
2
1
i
2
RMS
i
2
1,RMS
=
i
2
1,RMS
i
2
THD
2
=
i
2
RMS
1
1,RMS
i
2
RMS
= 1 + THD
2
i
2
1,RMS
i
RMS
=

1 + THD
2
i
1,RMS
1
k
d
= (3.15)
1 + THD
2
Example:
V = V
s
sin(t)
_ _
22 CHAPTER 3. POWER FACTOR AND MEASURES OF DISTORTION
_

4
i
pk
_
i
n
=
n 2
i(t) = square wave


_
i
0
= i
ave
=
1
2
i
pk
THD = 121%
i
pk 4 1
2

2
k
d
=
i
pk

2
2
=

P.F. = 0.63 (3.16)
i(t)
Ipk
t
2
Figure 3.4: Example
(Passive) Power Factor Compensation (KSV: Section 3.4.1)
Lets focus on the displacement factor component of power factor. For simplicity,
lets assume a linear load (e.g. R-L) so that voltages and currents are sinusoidal.
For sinusoidal V and i:
< P >
P.F. = = cos (3.17)
V
RMS
i
RMS
is the power factor angle:
Leading < 0 Capacitive
Lagging > 0 Inductive
23
Real power:
P = V
RMS
I
RMS
cos (3.18)
Dene reactive power as:
.
Q = V
RMS
I
RMS
sin (3.19)
Q
S
P
Figure 3.5: Reactive Power
In vector form S

= P + jQ. In phaser form V ,

i S

=< V I

>
units
Apparent Power S = S

= V
RMS
I
RMS
V A
Average Power Re{S} = P = V
RMS
I
RMS
cos W
Reactive Power Im{S} = Q = V
RMS
I
RMS
sin V AR
We can use these results to help adjust the displacement factor of a system. (make
Q
net
0).
24 CHAPTER 3. POWER FACTOR AND MEASURES OF DISTORTION
i

2 2
R +( L)
L
L
VsCos( t)
R
Im
S
i*
R
v Re
i
Figure 3.6: R-L Load
Suppose we have an R-L load (e.g. an induction machine):
V
s
L
i(t) =

2
L
2
+ R
2
cos(t arctan(
R
))
since S =
.
V I

L
voltage-current phase = arctan( )
R
L
P.F. = cos(arctan( ))
R
R
=
R
2
+
2
L
2
< 1 (3.20)
We can add some additional reactive load to balance out and give net unity power
factor.
S = V
RMS
I
RM S
=
V
2
2

2
L
s
2
+ R
2
(3.21)
P = S cos
= V
RMS
I
RMS
cos
25
V
2
R
=
s
(3.22)
2(
2
L
2
+ R
2
)
jQ = jS sin
= jV
RMS
I
RMS
sin
LV
2
= j
s
(3.23)
2(
2
L
2
+ R
2
)
So we have real and reactive power.
Suppose we add a capacitor in parallel:
i
C
VsSin(t)
Figure 3.7: Capacitor
Z
c
1
Z
c
V
phase
i
phase
i

P

1
=
jC
=
1
e
j

2
C
= Ce
j

(3.24)
2
= 90


= V
s
C sin(t + ) (3.25)
2
= V
RMS
I
RMS
1
= V
s
2
C (3.26)
2
= 0 (3.27)
26 CHAPTER 3. POWER FACTOR AND MEASURES OF DISTORTION
1
Q

= j
2
V
s
2
C (3.28)
So by placing the capacitor in parallel:
t) VsCos(
L
R
P, Q Q
C
Figure 3.8: Parallel Capacitor
S = P + jQ + jQ

make jQ and jQ

cancel: Q + Q

= 0
LV
2
1
s
j
2(
2
L
2
+ R
2
)
j
2
V
2
C = 0
s
L
C = (3.29)

2
L
2
+ R
2
Example:
= 377RAD/sec (HZ)
R = 1
L = 2.7mH
C = 1.32mF
27
If we know our load, we can add reactive elements to compensate so that no dis
placement factor reduction of line utilization occurs. Real, reactive power denitions
are useful to help us do this. This does not help with distortion factor.
Chapter 4
Phase-controlled Rectifiers
Read Chapter 5 of "Principles of Power Electronics" (KSV) by J. G. Kassakian, M.
F. Schlecht, and G. C. Verghese, Addison-Wesley, 1991.
Thyristor Devices: SCR (Silicon Controlled Rectifier)
K
Figure 4.1: Thyristor
SCR: Acts like a diode where you can select when conduction will st art , but not
when it stops.
Stay off until a gate pulse is applied while VAK> 0.
Once on, behaves like a diode and does not t urn off until i +0.
To stay off (after VaK > 0 again) must have i stay at 0 for a short time t, (10 -
loops)
So the device is semi-controlled: we control t he t urn on point, but only turns off
when circuit conditions force it to.
Simple example:
Figure 4.2: Example
Phase of thyristor t urn on (with respect t o line voltage) is termed firing angle a.
Consider a full-bridge converter (inductive/current load).
Diode version:
CHAPTER 4. PHASE-CONTROLLED RECTIFIERS
A
o t
2-
Dl, D2
./
D3, D4
/
- Conduct - - Conduct
Figure 4.3: Diode Version
Thyristor (phase-cont rolled) version (firing angle a):
Ql,Q2 == Q3,Q4
Con uct ( Conduct Conduct
Figure 4.4: Thyristor Version
Lets analyze the output voltage < v, >:
Id >0 by necessity
(conducbon of thyristor)
A <Vx>
Rectification
a
z>
Rectification Inversion
( <vx>>o
\ /
- - <vx><o >
Power Flows Power Flows .....................
AC -> DC DC -> AC
Quadrants of 0 ration
in ol,17
Figure 4.5: Out put Voltage
So with a phase controlled converter, we can regulate t he output voltage by varying
firing angle a. We can even cause power flow from dc-side t o ac-side as long as Id > 0
(e.g., pull power out of inductor and put into line).
Consider the power factor of a phase-controlled converter:
V,i
Figure 4.6: Power Factor
CHAPTER 4. PHASE-CONTROLLED RECTIFIERS
Phase shift of fundamental of square wave in phase with square wave, therefore,
= a. So t he power factor of a phase-controlled converter varies with firing angle
a.
Consider the effect of ac-side reactance:
No LC
+
r
Ql
r
Q ~ A
LC
-
il A
4 4
il VsSin@t)
Qz
r
-
+~d
No LC
\
a+u o t
>
a n
-Id
QLQZ Q3,Q4
All- All-
+?-= e +?-= e
+ e
Q3,Q4
Figure 4.7: AC-S ide Reactance
Similar t o t he diode rectifier case, a commutation period exists during which all
devices are on, while current in LC switches between +Id and -Id (between Q1/Q2
and Q 3 I Q 4 .
A similar analyze t o t he diode case shows t hat for t he full-bridge thyristor con-
verter:
2K
< v, >= -
Xc I d
- 1 - a [cos
K n-
Note t hat t he need t o commutate devices places a limit on how negative t he out put
voltage can be made as a function of X$-d and a. This is analyzed in KSV, Chapter
5. (require a +u < n-) .
Summary:
VdO
!
Commutation Limit
Figure 4.8: Summary

Chapter 5
Introduction to DC/DC
Converters
Analysis techniques: Average KVL, KCL, P.S.S. Conditions.
KCL
I1
i2
in
Figure 5.1: KCL
i
j
= 0 (5.1)
34





35
Average over time:
1

i
j
= 0
T T

1

T T
i
j
= 0

< i
j
> = 0 (5.2)
KCL applies to average current as well as instantaneous currents. (Derives from
conservation of charge).
KVL
V2
Vn
V1
+

+

Figure 5.2: KVL
V
k
= 0 (5.3)
Average over time:
1

V
k
= 0
T T

1
V
k
= 0
T T
< V
k
> = 0 (5.4)


36 CHAPTER 5. INTRODUCTION TO DC/DC CONVERTERS
KVL applies to averaged variables.
P.S.S.
To analyze converters in Periodic Steady State (P.S.S.):
Average KCL < i
j
> = 0 (5.5)
Average KVL < V
k
> = 0 (5.6)
di
L
from < V
L
> = L < >
dt
di
L
in P.S.S. < > = 0
dt
Inductor in P.S.S. < V
L
> = 0 (5.7)
dV
L
from < i
C
> = C < >
dt
dV
L
in P.S.S. < > = 0
dt
Capacitor in P.S.S. < i
C
> = 0 (5.8)
If Circuit is Lossless: P
in
= P
out
(5.9)
Consider the DC/DC converter from before (see Figure 5.3):
q(t)
iL
I2
1
Pulse Width Modulation (PWM)
+

I1
q(t) = 1
+
t
+
q(t) = 0
+
VL

dT T T+dT 2T
Duty Ratio d
Vx C2 V2 Vx(t)
V1
C1
V1

(V1>0)
<Vx> = dV1

t
dT T T+dT 2T
Figure 5.3: DC/DC Converter
37
Assume Ls and Cs are very big, therefore:
v
C
(t) V
C
(5.10)
i
L
(t) I
L
(5.11)
Analyze (using average relations) in P.S.S.:
< V
L
> = 0
< V
L
> = dT (V
1
V
2
) + (1 d)T (V
2
)
dV
1
T V
2
T = 0
V
2
= dV
1
(5.12)
(Since < V
L
>= 0, < V
2
>=< V
x
>= dV
1
.)
Consider currents:
< i
C2
> = 0
I
1
= I
2
(5.13)
< i
C1
> = 0
I
C1
= (I
1
I
2
dT ) + I
1
(1 d)T = 0
I
1
= dI
2
(5.14)
Combining:
I
1
= dI
2
dV
1
= V
2
dV
1
I
1
= dI
2
V
2
V
1
I
1
= I
2
V
2
(5.15)
38 CHAPTER 5. INTRODUCTION TO DC/DC CONVERTERS
Therefore, power is (ideally) conserved.
Note: Trick in this type of average analysis is to be careful when one can use
an average value and when one must consider instantaneous quantities.
With the following type of external network and V
1
, V
2
> 0, power ows from
1 2.
Switch implementation: buck or down converter (see Figure 5.4).
+
V1
C2
+
V2 C1


Figure 5.4: Buck (down) Converter
Type of direct converter because a DC path exists between input and output
in one switch state.
Suppose we change the location of source and load: Rene switching function so
q(t) = 1 when switch is in down position (see Figure 5.5).
Similar analysis:
< V
L
> = 0
(V
1
V
2
)(1 d)T + V
1
dT = 0
1
V
2
= V
1
(5.16)
1 d
By conservation of power:
I
2
= (1 d)I
1
(5.17)
39
q(t)
1
iL t
I2 I1
q(t) = 0 dT T T+dT 2T
+
-
+
Vx(t)
- +
+
q(t) = 1
VL
V2
V2 C1 Vx C2 V1
t
-
dT T T+dT 2T
-
VL
dT T
V1
V1-V2
Figure 5.5: Change the Location of Source and Load
In this case, energy ows from 2 1 and the P.S.S. output voltage (V
2
) is higher
than input voltage (V
1
).
With the following switch implementation: boost or up converter. Another
type of direct converter (see Figure 5.6).
C2 C1 V2
+
+ V1


Figure 5.6: Boost (up) Converter
In general power ows direction depends on:
1. External network
2. Switch implementation
40 CHAPTER 5. INTRODUCTION TO DC/DC CONVERTERS
3. Control
We may need to know all of these to determine behavior.
The boost converter is often drawn with power owing left to right. However,
there is nothing fundamental about this (see Figure 5.7).
C1 C2 +
V1
V2
+


Figure 5.7: Boost (up) Converter Drawn Left to Right
Boost: Switch turns on and incrementally stores energy from V
1
in L. Switch
truns o and this energy and additional energy from input is transferred to output.
Therefore, L used as a temporary storage element.
Either the buck or boost can be seen as the appropriate connection of a canonical
cell (see Figure 5.8).
A
B
C
Figure 5.8: Direct Canonical Cell
The direct connection has B as the common node. The rest of operation is
determined by external network, switch implementation and control.
Switch implementation: Dierent switches can carry current and block voltage
only in certain directions.
41
MOSFET can block positive V and can carry positive or negative i (see Figure 5.9).
D
D
i
+
G V
Body Diode
G
S
S
Figure 5.9: MOSFET
BJT (or darlington) is similar, but negative V blows up device (see Figure 5.10).
i i
+ +
Same for
V V

IGBT

Figure 5.10: BJT
Combine elements:
1. Block positive V and carry positive and negative i (see Figure 5.11).
+
V
i

Figure 5.11: Combine Elements 1
2. Block positive and negative V and carry positive i (see Figure 5.12).
42 CHAPTER 5. INTRODUCTION TO DC/DC CONVERTERS
i
+
V

Figure 5.12: Combine Elements 2
3. Block positive and negative V and carry positive and negative i (see Fig
ure 5.13).
i
+
V

Figure 5.13: Combine Elements 3
We can also construct indirect DC/DC converters. Store energy from input, trans
fer energy to output, never a DC path from input to output (see Figure 5.14).
+ +
B A
V1 V2

C
Figure 5.14: Canonical Cell
Split capacitor (see Figure 5.15):
43
q(t) = 1 q(t) = 0
+

q(t)
+
V1
V2 1
t

dT T T+dT 2T
q(t) = 0 q(t) = 1
V2
V1
VL
T dT
C2
+
V2


C1
V1
+
Split Capacitor
Figure 5.15: Indirect DC/DC Converter
< V
L
> = 0
< V
L
> = V
1
dT + (1 d)TV
2
d
V
2
= V
1
(5.18)
1 d
V
2
for 0 < d < 1 < < 0 (5.19)
V
1
Store energy in L(dT ) from V
1
.
Discharge it (the other way) in V
2
. (must have voltage inversion).
Buck/Boost or up/down converter (see Figure 5.16):
44 CHAPTER 5. INTRODUCTION TO DC/DC CONVERTERS
V1
+
+
V2
I2 I1


Figure 5.16: Buck/Boost or up/down converter
V
1
> 0
I
1
> 0
V
2
< 0
I
2
> 0
Other indirect converters include CUK and SEPIC variants.
Given conversion range <
V
2
< 0, why not always use indirect vs. direct?
V
1
1. Sign inversion (can x)
2. Device and component stresses
Look at averaged circuit variables (see Figure 5.17): Assume C, L are very large.
I
L
= I
1
+ I
2
|I
L
| = |I
1
| + |I
2
| (5.20)
By averaged KCL into dotted box: Maybe counter intuitive: I
1
= average tran
sistor current. I
1
+ I
2
= peak transistor current.
45
V1
+
+
V2
I2 I1
+
IL
iq
VC



iq
I1+I2
I1
dT T
Figure 5.17: Averaged Circuit Variables
By averaged KVL around loop:
V
C
= V
1
V
2
|V
C
| = |V
1
| + |V
2
| (5.21)
Therefore, for big L, C (see Figure 5.18):
V1
+
+
V2
I2 I1
Q
D
V1V2
I1+I2


+

Figure 5.18: Big L, C
Indirect converter:
So Q, D, L see peak current I = I
1
+ I
2
,
Q, D, C block peak voltage V = V
1
+ V
2
. | | | |
Consider direct converters (see Figure 5.19):
46 CHAPTER 5. INTRODUCTION TO DC/DC CONVERTERS
+
I1
Boost D
Q Vq
Buck
+
Vq +
I2
Vd
Q
D C V2
+
V1
+
+

V1
+

V2 C
Figure 5.19: Direct Converters
Buck:
V
C
= V
q,max
= V
d,max
= V
1
(5.22)
I
L
= i
q,max
= i
d,max
= I
2
(5.23)
Boost:
V
C
= V
q,max
= V
d,max
= V
2
(5.24)
I
L
= i
q,max
= i
d,max
= I
1
(5.25)
Direct converters (either type):
V
C
= V
q,max
= V
d,max
= max(V
1
, V
2
) (5.26)
I
L
= i
q,max
= i
d,max
= max(I
1
, I
2
) (5.27)
Device voltage and current stresses are higher for indirect converters than for
direct converters with same power. Inductor current and capacitor voltage are also
higher.
Summary:
For indirect converters (neglecting ripple) (see Figure 5.20):
47
VC
+
V1
+
+
V2
I2 I1
iL

iq
I1+I2
I1
dT T
Figure 5.20: Indirect Converters (neglecting ripple)
I
L
= i
sw,pk
= i
d,pk
= I
1
+ I
2
(5.28) | | | |
V
C
= V
sw,pk
= V
d,pk
= V
1
+ V
2
(5.29) | | | |
For direct converters (neglecting ripple) (see Figure 5.21):
IL
+
Boost
Vq
+
V2
IL
Buck
+
Vq +
Vd
V2
+
V1
+

V1
+

Figure 5.21: Direct Converters (neglecting ripple)
I
L
= i
sw,pk
= i
d,pk
= max(I
1
, I
2
) (5.30)
V
C
= V
sw,pk
= V
d,pk
= max(V
1
, V
2
) (5.31)
Based on device stresses we would not choose an indirect converter unless we
needed to, since direct converters have lower stress.
48 CHAPTER 5. INTRODUCTION TO DC/DC CONVERTERS
5.1 Ripple Components and Filter Sizing
Now, selecting lter component sizes does depend on ripple, which we have previously
neglected. Lets see how to approximately calculate ripple components. To eliminate
2
nd
order eects on capacitor voltage ripple:
1. Assume inductor is (i
pp
0).
2. Assume all ripple current goes into capacitor.
Similarly, to eliminate 2
nd
order eects in inductor current ripple:
1. Assume capacitors are (V
C,pp
0).
2. Assume all ripple voltage is across the inductor.
We can verify assumptions afterwards.
Example: Boost Converter Ripple (see Figure 5.22)
+
V2 id
id I1
V1
+


+
V2
Figure 5.22: Boost Converter Ripple
Find capacitor (output) voltage ripple (see Figure 5.23):
Assume L , therefore, i
1
(t) I
1
.
So a ripple model for the output voltage is (see Figure 5.24):
~
49 5.1. RIPPLE COMPONENTS AND FILTER SIZING
Figure 5.23: Capacitor Voltage Ripple
id
Including Ripple
D
Actual Waveform i
Id=<id>=(1-D)I1
T
I1
id
t
DT
DI1
t
DT T
C R
(1D)I1
+
~ ~
~
id V
VC

VCpp
2
t
T

VCpp
2
DT
Figure 5.24: Ripple Model with Capacitor
If we assume all ripple current into capacitor
1
2fsw C
R or

V
2
is small recpect
to V
2
.
Let us calculate the ripple:
i = C
dV
C
dt
V
C,pp
=

DT
0
1 D
C
I
1
dt
=
(1 D)DT
C
I
1
(5.32)
Therefore, to limit ripple:
~

50 CHAPTER 5. INTRODUCTION TO DC/DC CONVERTERS
(1 D)DT
C I
1
(5.33)
V
C,pp
Now let us nd the capacitor voltage ripple (see Figure 5.25):
<Vx>=(1D)V2
T
V2
Vx
+
Vx
Source Impedance
Zi
V1
+
+
V2 C1
Actual Vx Including Ripple
t
DT



Figure 5.25: Ripple
Replace V
x
with equivalent source and eliminate DC quantities (see Figure 5.26).
Vx
DV2
t
DT T
(1D)V2
+
~ ~
~
i1 Vx
i1

ipp
2
t
T

ipp
2
DT
Figure 5.26: Ripple Model with Inductor
Neglecting the drop on any source impedance (|Z
i
| 2f
sw
L).
1
DT
i
L,pp
= (1 D)V
2
dt
L 0
D(1 D)T
= V
2
(5.34)
L
51 5.1. RIPPLE COMPONENTS AND FILTER SIZING
Therefore, we need:
L
D(1

i
pp
D)T
V
2
(5.35)
Energy storage is one metric for sizing Ls and Cs. Physical size may actually be
determined by one or more of: energy storage, losses, packing constraints, material
properties. To determine peak energy storage requirements we must consider the
ripple in the waveforms.
Dene ripple ratios (see Figure 5.27):
V
C,pp
R
C
=
2V
C
(5.36)
i
L,pp
R
L
=
2I L
(5.37)
This is essentially % ripple: peak ripple magnitude normalized to DC value.
X
Xpk

Xpp
2

Xpp
2

Figure 5.27: Ripple Ratios
Specication of allowed ripple and converter operating parameters determines
capacitor and inductor size requirements.
Therefore:
V
C,pk
= V
C
(1 + R
C
) (5.38)
i
L,pk
= I
L
(1 + R
L
) (5.39)
52 CHAPTER 5. INTRODUCTION TO DC/DC CONVERTERS
So from our previous results (boost converter):
(1 D)DT
I
1
(5.40) C
2R
C
V
C
D(1 D)T
V
2
(5.41) L
2R
L
I
1
The ripple ratios also determine passive component energy storage requirements
and semiconductor device stresses.
So lets calculate the required energy storage for the capacitor:
1
CV
2
E
C
=
2
C,pk
1 (1 D)DT
I
1
V
2
=
2 2R
C
V
C
(1 + R
C
)
2
C
DI
2
V
2
(1 + R
C
)
2
=
4f
sw
R
C
DP
o
(1 + R
C
)
2
= (5.42)
4f
sw
R
C
So required capacitor energy storage increases with:
1. Conversion ratio
2. Power level
and decreases with switching frequency.
Similar result for inductor energy storage:
(1 D)P
o
(1 + R
L
)
2
E
L
= (5.43)
4f
sw
R
L
It can be shown that direct converters always require lower energy storage than
indirect converters.
53 5.2. DISCONTINUOUS CONDUCTION MODE
Table 5.1: Eect of Allowed Ripple on Switches
Converter Type Value L, C Finite L, C
Direct
Indirect
i
sw,pk
, i
d,pk
V
sw,pk
, V
d,pk
i
sw,pk
, i
d,pk
V
sw,pk
, V
d,pk
max(|I
1
|, |I
2
|)
max(|V
1
|, |V
2
|)
|I
1
|, |I
2
|
|V
1
|, |V
2
|
max(|I
1
|, |I
2
|)(1 + R
L
)
max(|V
1
|, |V
2
|)(1 + R
C
)
(|I
1
|, |I
2
|)(1 + R
L
)
(|V
1
|, |V
2
|)(1 + R
C
)
Consider eect of allowed ripple on switches (see Table 5.1):
Dene a metric for switch sizing (qualitative only):
.
Switch Stress P arameter(SSP ) = V
sw,pk
i
sw,pk
(5.44)
For a boost converter:
SSP = max(V
1
, V
2
)(1 + R
C
)max(I
1
, I
2
)(1 + R
L
)
= V
2
(1 + R
C
)I
1
(1 + R
L
)
P
o
= (1 + R
C
)(1 + R
L
)
1 D
V
2
= P
o
(1 + R
C
)(1 + R
L
) (5.45)
V
1
Therefore, SSP gets worse for:
Large power
Large conversion ratio
Large ripple
5.2 Discontinuous Conduction Mode
Consider the waveform of the boost converter (see Figure 5.28):
54 CHAPTER 5. INTRODUCTION TO DC/DC CONVERTERS
q(t)
Switching Function for Diode
qD(t)
t
I1
DT T
VL
L
R +
+

C
q(t)
V2
V1

V1V2
iL
T DT
t
V1
I1
t
DT T
Figure 5.28: Boost Converter Waveforms
V
1
DT
i
L,pp
= (5.46)
L
I
L
= I
1
V
2
= (5.47)
R(1 D)
i
L,pp
2
R
L
=
I
1
V
1
D(1 D)RT
=
2V
2
L
D(1 D)
2
RT
= (5.48)
2L
R
L
as R , L (5.49)
(see Figure 5.29 for an illustration)
Eventually peak ripple becomes greater than DC current: both switch and diode
o for part of cycle. This is known as Discontinuous Condition Mode (DCM). It
55 5.2. DISCONTINUOUS CONDUCTION MODE
t
iL
As R Increases
t
iL
DT T DT T
As L Decreases
Figure 5.29: Changing R and L
happens when R
L
> 1.
D(1 D)
2
RT
R
L
=
2L
R
L
R
>

1
2L
(5.50)
D(1 D)
2
T
At light load (big R and low power) we get DCM. Lighter load can be reached in
CCM for larger L. DCM occurs for:
L
D(1 D)
2
TR
(5.51)
2
The minimum inductance for CCM operation is sometimes called the critical
inductance.
D(1 D)
2
TR
L
CRIT,BOOST
= (5.52)
2
For some cases (e.g. we need to operate down to almost no load), this may be
unreasonably large.
Because of the new switch state, operating conditions are dierent (see Fig
ure 5.30).
56 CHAPTER 5. INTRODUCTION TO DC/DC CONVERTERS
q(t), q
D
(t)
VL
DT
t
DCM
(D+D2)T T
V1
(D+D2)T t
DT
T
V1-V2
iL Must Be Zero in Remaining Time
t
DT (D+D2)T T
Figure 5.30: Dierent Operating Conditions
Voltage conversion ratio:
< V
L
> = 0 in P.S.S.
V
1
DT + (V
1
V
2
)D
2
T = 0
V
1
(D + D
2
) = V
2
D
2
V
2
D + D
2
=
V
1
D
2
D
= 1 + (5.53)
D
2
where D
2
< 1 D.
How does this compare to CCM? In CCM:
V
2
1
=
V
1
1 D

57 5.2. DISCONTINUOUS CONDUCTION MODE
1 D + D
=
1 D
D
= 1 + (5.54)
1 D
Since
V
2
= 1 +
D
and D
2
< 1 D,
V
2
is bigger in DCM.
V
1
D
2
V
1
Eliminating D
2
from equations, can be shown for boost:
V
2
1 1 2D
2
RT
= + 1 + (5.55)
V
1
2 2 L
Therefore, conversion ratio depends on R, f
sw
, L, ... unlike CCM. This makes
control tricky, as all of our characteristics change for part of the load range.
How do we model DCM operation? Consider diode current (see Figure 5.31).
IL id
id
ipk
+

+ +
V2 id(t) V2
V1

I2
t
DT (D+D2)T T
Figure 5.31: DCM Operation Model
V
1
DT
i
pk
=
L
D
2
T = t
58 CHAPTER 5. INTRODUCTION TO DC/DC CONVERTERS
i
= L
V
V
1
DT
= L
L
V
2
V
1
V
1
D
D
2
= (5.56)
V
2
V
1
< i
out
> = < i
d
>
1 1
= (D
2
T )(i
pk
)
2 T
1 V
1
V
1
DT 1
= ( DT )( )
2 V
2
V
1
L T
V
2
TD
2
=
1
(5.57)
2(V
2
V
1
)
Model as controlled current source as a function of D.
So DCM sometimes occurs under light load, as dictated by sizing of L.
Sometimes we can not practically make L big enough.
Must handle control (changes from CCM to DCM).
Also, we get parasitic ringing in both switches (see Figure 5.32).
Vx
+

Ideal
L Rings with Parasitic Cs
V2
+
+
V2
V1
Vx
V1


t
DT D2T T
Figure 5.32: Parasitic Ringing
Sometimes people design to always be in DCM. Inductor size becomes very small
and we can get fast
di
(see Figure 5.33).
dt
59 5.2. DISCONTINUOUS CONDUCTION MODE
CCM
DCM
Desired i
V2
di/dt limited so cannot respond fast.
Figure 5.33: Design in DCM
In this case we get:
1. Very fast
di
capability.
dt
2. Simple control model i
out
= f(D).
3. Small inductor size (E
L
minimized @ R
L
= 1)
But we must live with:
1. Parasitic ringing
2. High peak and RMS currents
3. Need additional lters
DCM is sometimes used when very fast response speed is needed (e.g. for voltage
regulator modules in microprocessors), especially if means are available to cancel
ripple (e.g. interleaving of multiple converters). In many other circumstances DCM
is avoided, though one may have to operate in DCM under light-load conditions to
keep component sizes acceptable.