Introduction to IC Fabrication

Miniaturization of electronic components and correspondingly the balk and volume of equipments has been an aim which has been progressing concurrently with advance in electronics. This received a tremendous boost with the discovery of transistor in 1948. This simultaneously gave birth to a science and technology called Microelectronics. Microelectronics covers in its ambit not only miniaturization but along with it reliability, high speed, low cost, increased system complexity. Before the advent of integrated circuits, it was the practice to assemble the discrete components as per a planned layout on a metal base and wire them. As the base was the major contributor to bulkiness, it was replaced by printed circuit boards (single and double sided). Passive components like resistors and capacitors were created by depositing thin films of metal on a substrate like pyrex and discrete components were plugged at appropriate places and soldered. In the meantime vast improvements were made in the manufacture of the transistors by such processes as epitaxial growth, masked impurity diffusion, oxide growth and oxide etching using photo-lithography for definition. These processes helped in creating on a single-crystal chip of silicon, about 5 mils by 50 mils many circuits of both active and passive components. Hence the name Integrated Circuit IC, in short.

1) Film Circuits consist of layers ofr films of conducting and non-conducting materials on a passive (insulating) substrate like pyrex. In this way passive elements like resistors, inductors and capacitors, are fabricated to high accuracy. By controlling the thickness of the film deposited it can be made thin and thick. FETs are manufactured as thin transistors. 2) Monolithic Integrated Circuits A single wafer of silicon crystal is the substrate on which all the components are made. The wafer is lightly doped P type substrate. The wafer is for 10 cm dia and 10 to 15 units thick(0.2 to 0.3 mm). The single crystal is extremely pure. The wafer is lapped and polished to a mirror finish of 5 units thick approximately. The large piece is then sawed into 100 to 8000 rectangular chips of 1 to 10 mm sides. Each chip is a single IC. A chip may contain an average of 700 components. Epitaxial Growth On the p type substrate an n type layer, 1 mil (5 to 25 um) thick layer is grown by plcing the wafer in a furnace at 1200C and introducing a gas like phosphine (PH3) for n type doner. Or diborane(B2,H2) for p type acceptor.

The p type substrate has a resistivity of 10 ohm-cm giving Na of 1.4 x 10^15 atoms/cm3. For n layer the resistivity chosen is 0.1 to 0.5 ohm-cm. Isolation by oxidation A thin layer of SiO2 is grown on the epitaxial layer. It is 1 micron thick. A photoresist liquid is now coated over the SiO2 layer. This layer will harden on exposure to ultraviolet. A mask, a glass plate with pattern drawn on it, is now placed on the photo resist surface. The mask allows UV light to pass through selected areas and polymerizes(hardens) it. The mask is now removed and the layered substrate washed with a chemical(trichloroethylene) which removes the unexposed portions.

The chip after washing is shown in fig. Then plain areas are the unmasked portion. The chip is immersed in an etching solution of hydrofluoric acid and SiO2 layer is removed. The etching solution does not affect the unmasked polymerized areas. The photoresist is now removed. Completely by scrubbing with heated solvents. P type impurities are now diffused through the silicon turning the n type material into a p type channel extending into the p substrate. The concentration of p type channels is more than that of p type substrate and hence referred as p+. This process of SiO2 layers, photo resist and masking is repeated for a base collector junction, resistance diffusion etc. The wafer is diced into individual chips. The chip externally small and brittle and is cemented or soldered to gold plated header to which leads are connected. Finally it is hermetically scaled. To-5 can accommodate upto 14 pins. The number of complete logic gates in a single IC package is described as follows.

SSI(Small Scale Integration) up to 10 gates per package MSI(Medium Large Scale Integration) 10 to 100 gates per package LSI(Large Scale Integration) 100 to 1000 gates per package VLSI(Very Large Scale Integration) greater than 1000 gates per package

Production Process of Monolithic ICs

A monolithic IC is one in which all circuit components and their inter-connections are formed on a single thin wafer, called the substrate. The basic production processes for the monolithic ICs are given below :

Monolithic IC Manufacturing Process

1. P-Substrate.
As already mentioned in the previous article, it is the bottom most layer that serves as the body or substrate upon which the complete IC is built. A typical P-type crystal is grown in dimensions of 250 mm length and 25 mm diameter, as shown in figure. Silicon is preferred because its characteristics are more suitable for manufacture of ICs. The crystal is then cut by a diamond saw into thin slices called wafers. These wafers after being lapped and polished to mirror finish serve as the base or substrate on which hundreds of ICs are produced. The enlarged view of circular wafer is shown in figure. The wafer may also be rectangular in shape as shown in figure.

Manufaturing-Monolithic IC

2. Epitaxial Growth.
On the high resistivity P-type substrate a low resistivity 25 a m thick layer of N-type is epitaxially grown. For this purpose, the wafers are placed in a diffusion furnace at 1,200 C and a gas mixture of silicon atoms and pentavalent atoms is passed over the wafers. This forms a thin layer of N- type semiconductor on the heated surface of the substrate, as shown in figure. It is this expitaxial layer that all active and passive components of an IC are formed. This layer ultimately becomes the collector for a transistor or an element for a diode or a capacitor. The resistivity of P-type substrate for NA = 1.4 x 1021 atoms/m3 is typically 10 ohm-cm. The resistivity of N-type epitaxial layer is suitably chosen in the range of (0.1 0.5) ohm-cm. This layer is finally polished and cleaned.

Monolithic IC-Manufacturing

3. Insulation Layer.
In order to prevent the contamination of the epitaxial layer, a thin layer of Si0 2 is formed over the entire surface, as illustrated in figure. The Si Monolayer is grown by exposing the epitaxial layer to an oxygen atmosphere to about 1,000 C. This surface layer of Si02 will prevent any impurities from enter-ing4he N-type epitaxial layer. However, selective etching of this layer will permit the diffusion of the proper impurity into designed areas of the N-type epitaxial region of the silicon wafer.

Photolithographic Process-Monolithic IC

4. Photolithographic Process.
The monolithic technique requires the selective removal of the silicon-dioxide (SiO2) to form openings through which impurities may be diffused, if required. The photolithographic process shown in figure. is used for this purpose. During the process the wafer is coated with a thin layer of photo-sensitive material, commonly known as photo-resist (such as Kodak photoresist KPR). A large black and white layout of the desired pattern of openings or windows is made and then reduced photographically. This negative, or stencil, of the required dimensions is placed as a mask over the photo- resist, as illustrated in figure.This wafer surface with mask is then exposed to the ultraviolet light. Due to ultraviolet light, the photoresist below the transparent portions of the mask becomes polymerised. The mask is now removed, and the wafer is developed by using a chemical like trichlorolethylene. The chemical dissolves the unpolymerised portions of the photoresist film and leaves the surface as shown in figure. The oxide not covered by polymerised photoresist is then removed by immersing the chip in an etching solution of HCl. Those portions of the Si02 which are protected by the photoresist remain unaffected by the acid. After etching and diffusion of impurities, the resist mask is stripped off with a chemical solvent like hot sulphuric acid (H2 S04) and by means of a mechanical abrasion process. The appropriate impurities are then diffused through oxide free windows.

Monolithic IC Manufacturing

5. Isolation Diffusion.

Si02 layer is removed from the desired areas (four selected portions from the wafer, as illustrated in fig. using photolithographic etching process explained above. The remaining Si02 layer serves as mask for the diffusion of acceptor impurities. The wafer is now subjected to isolation diffusion at a suitably high temperature and for appropriate time period allowing P-type impurity (boron in this case) to penetrate into the N-type epitaxial layer through the openings in Si02 layer and ultimately reach the P-type substrate. The temperature and time period of diffusion are required to be carefully controlled. The process results in formation of N-type regions, called the isolation islands. The name is given as they are separated by back-to-back P-N junctions. Their purpose is to permit electrical isolation between various components of IC. Each electrical element is later on formed in a separate isolation island. The bottom of the Ntype isolation island ultimately forms the collector of an N-P-N transistor. The P-type substrate, is always kept negative with respect to the isolation islandsand provided with reverse bias at P-N junctions. If P-N junctions are forward biased, the isolation will get lost. Isolation diffusion is controlled so as to cause high acceptor concentration P+ (typically NA = 5 x 1026atoms/m3) in the region between the isolation islands. This concentration is much higher than that of P-type substrate. This is for preventing the depletion region of the reverse-biased isolation island-to-substrate junction from extending into P+ region and from possibly connecting two adjacent isolation islands. Two adjoining isolation islands are connected to the P-type substrate by a barrier capacitance or transition capacitance. This is undesirable and is called the parasitic Capacitance. It adversely affects the performance of the IC and puts a limitation on its use. The parasitic capacitance has two components; the capacitance C1 from the bottom of the re type region to the substrate and capacitance C2 from the sidewalls of the isolation islands to the P-region. The bottom component Ct is essentially due to step junction formed by ! epitaxial growth and, therefore, varies as the square root of the voltage V between the isolation region and substrate (i.e. C1 is directly proportional to V). The sidewall capacitance C2 is associated with a diffused graded junction and so varies as V-1/2. The total capacitance is of the order of a few p F.

Monolithic IC Production

6. Base Diffusion. During this process a new layer of Si02 is formed over the wafer. The new pattern of openings is created depending upon the circuit needs. In these openings P-type impurities like boron are diffused under regulated environments to form P-regions. This forms the base region of an N-P-N transistor or as well as resistors, the anode of diode, and junction capacitor. In this case, the diffusion time is so

controlled that the P-type impurities do not reach the substrate. The resistivity of the base layer is usually much higher than that of the isolation regions.

Monolithic IC construction

7. Emitter Diffusion. A layer of Si02 is again formed over the entire surface and openings in the P-type regions, as shown figure, are formed again by employing masking and etching processes. The N-type impurities like phosphorous are then diffused through these windows under controlled environments to form the transistor emitters, the cathode regions for diodes, and junction capacitors. Additional windows (such as Wj and W2 in figure) are usually made into the N-regions to permit aluminium metallic connections.

Monolithic IC Manufacturing

8. Aluminium Metalization.
For making electrical connection between various components of the IC, several windows are opened on a newly created Si02 layer. Now a thin layer of aluminium is deposited on the entire top surface. Further, photoresist technique is used to etch away all the unwanted aluminium areas. The structure then provides the connected strips to which leads are attached, as illustrated in figures represents the complete IC layout of the circuit shown in figure.

9. Scribing and Mounting.

In practice, a large number (several hundreds) of identical ICs are manufactured simultaneously on a silicon wafer. After the completion of the metallization process, the wafer is scribed with a diamond-tipped tool and separated into individual chips. Each chip is then mounted on a ceramic wafer and is attached to a suitable header. Next the package leads are connected to the IC chip by stich bonding of 25 micron aluminium or , gold wire from the terminal pad on the IC chip to the package lead.