ARM Operating Modes

ARM Operating Modes User mode: FIQ Fast Interrupt: IRQ Normal Interrupt: Supervisor mode (SVC): Abort
C): Abort mode: Undefined mode: System mode: a normal program execution state for fast interrupt handling for general purpose interrupt handling a protected mode for operating system
when a data or instruction pre-fetch is aborted when an undefined instruction is executed a privileged user mode for the operating system
ARM Processor States Arm state: Thumb state: Jazelle state: all instructionsare 32bits long, word-aligned. all instructionsare 16 bits wide, half-wordaligned. all instructionsare 8 bits widefor JavaBytecode (for v5TEJonly)
ARM Architecture Overview
ARM-State Registers
Thumb-State Registers
Program Status Register (PSR) CPSR : CurrentProgramStatusRegister SPSR : SavedProgramStatusRegister
ARM Exception Types Reset Hardware reset: when the processor reset pin is asserted Software reset: by branching to the reset vector (0x0000)
Undefined instruction the processor cannot recognize the currently execution instruction
Software Interrupt (SWI) By s/w instruction, to allow a program running in User mode to request privileged operations that are in Supervisor mode
Prefetch Abort Fetch an instruction from an illegal address
Data Abort A data transfer instr. try to load or store data at an illegal address
IRQ: The processor IRQ pin is asserted and the I bit in CPSR is clear FIQ: The processor FIQ pin is asserted and the F bit in CPSR is clear 6
ARM Exception Vectors
(1)
Memory 7
ARM Instruction Set Data processing instruction (x24) Arithmeticinstruction(x8) Bit-wiseLogic instruction(x4) Movementinstruction(x2) Comparisoninstruction(x4) Shift and rotator instruction(x6)
Load and store instructions (x4) Singleregister load/storeinstructions(x2) Multiple-register load/storeinstructions(x2)
Branch instruction (x2) Status Register Transfer instruction (x2) Exception Generating instructions (x2)
ARM Instruction Summary
ARM Instruction Summary
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ARM Instruction Condition Code In ARM,all instructionscan be conditionallyexecutedaccordingto the state of the CPSRconditioncodes
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Part- I: UBoot S tartup
1. setupexceptionvector table, _start: and eachhandler
1. set SVCmode reset: 2. turn off watchdog 3. disableall IRQs 4. set SystemClock( cpu_init_crit: 1. flush I and D cache 2. flush TLB memsetup: 3. disableMMUstuff and caches data sheet 7-22 )
cpu_init_crit:
In /board/smdk2410/ 1. enableand set memory 2. returnto /cpu/arm920t/
memsetup.S
start.S
reset: 1. returnto reset : 16
Part- I: UBoot S tartup 1. SetupC environmentand run on RAM reset: - copy U-Boot code/ initializeddata to RAM from: _start: 0x0, Flashbase to: _TEXT_BASE,0x33F80000,Entry on RAM relocate: size: _armboot_start ~ bss_start (0x33F80000) (0x33F98558) - setupstackpointer sp = _TEXT_BASE glb data heap _start_armboot: irq_stack fiq_stack abrt_stack - clear BSS start_armboot() (_bss_start~ _bss_end)
In lib_arm/board.c 1. Flashinitialization 2. Init environment
main_loop()
3. Set IP addr 4. Set MACaddr 5. Devicesinitialize In common/main.c 6. Consoleinitialize 7. Enableinterrupts 8. EnableEthernet
In C code
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Part- I: U-boot-1.1.2 Linker Descriptor /board/smdk2410 /u-boot.lds
[root@test u-boot-1.1.2]# make : arm-linux-ld Bstatic Tuboot-1.1.2/board/smdk2410/u-boot.lds Ttext 0x33F80000 :
U-boot-1.1.2/board/smdk2410 TEXT_BASE = 0x33F8000
/config.mk UBoot entry point address 18
Part- I: U-boot-1.1.2 UBoot traces tartup (1/7) /cpu/arm920t / start.S
19
20
21
22
/lib_arm/board.c 23
/board/smdk2410/
memsetup.S
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Part- I: U-boot-1.1.2 UBoot traces tartup (7/7) /board/smdk2410 /memsetup.S
r0 as src (SMRDARA addr on Flash) r1 as dest (BWSCONreg addr) r2 as copy length(13 words)
.. ..
13 words ...... 25
Part- III: Boot Requirements for Linux (2/6)
What does the loader do before giving control to Linux kernel? 1. Initialize base hardware CPU speed, memory timings, detect location and size of RAM (passed to Kernel by detect machine type (passed to Kernel by r1 ) tagged list )
2. Initialize devices any device that needs for reading Kernel and RFS images Init UART to be Kernel console (passed to Kernel by tagged list .)
3. Copy Kernel and RFS images to RAM arrange a block of contiguous physical memory for the Kernel, and another contiguous one for RFS (no need to be adjacent) Note Copy (or download remotely) and decompress (if needed) the Kernel and RFS image to their contiguous areas . Linux Kernel kernel uses 16K of RAM below it to store Tables. The recommended placement is 32KB into RAM. 30 Page
4. Setup the Kernel Tagged List (see next slide) 5. Calling the Linux Kernel with following settings CPU register settings r0 = 0, r1 = machine architecture number (the MACH_TYPE_XXX in kernel)
Must match one of define in linux/arch/arm/tools/mach-types. r2 = physical address of tagged list in system RAM
CPU mode All forms of interrupts must be disabled (IRQs and FIQs) CPU must be in SVC mode
Cache, MMU MMU must be off D-cache must be off and no any stale data (I-Cache can be on/off)
Device DMA to/from devices should be quiesced. 31
How does boot-loader pass data to the Kernel? CPU registers (r0, r1, r2) Kernel Tagged List (located in memory) A tag includes a header and a body Tag header has two fields: tag ID and tag size (header+body) Tag body: the structure depends on tag ID. A tagged list starts with ATAG_CORE and ends with ATAG_NONE
ATAG_CORE may or may not be empty. An empty ATAG_CORE has size = 2, ATAG_NONE has size = 0 The loader must pass at a minimum the size and location of the system memory (specified in ATAG_MEM ).
A minimum Tagged list: ATAG_CORE, ATAG_MEM, ATAG_NONE. There are also some other TAGs for use ATAG_RAMDISK ATAG_INITRD ATAG_INITRD2 ATAG_CMDLINE 32 : how the ramdisk will be used in kernel : virtual addr of the compressed ramdisk image : physical addr of the compressed ramdisk image
TAG format header TAG ID: TAG size: body (header+body)
ATAG_CORE ATAG_MEM ATAG_RAMDISK ATAG_INITRD Increasing ATAG_INITRD2 ATAG_CMDLINE : ATAG_NONE An example of a tagged list
start
depends on TAG type
Tagged list
ATAG_CORE ATAG_MEM ATAG_NONE A minimum tagged list
address
end
Note:
For some embedded systems, the tagged list is hard-coded in the Kernel. In such case, the bootloader does not need to setup it.
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ARM Linux Kernel Boot Requirements 1. Setup and initialise RAM Existingboot loaders: MANDATORY Newboot loaders: MANDATORY 2. Initialise one serial port Existingboot loaders: OPTIONAL,RECOMMENDED Newboot loaders: OPTIONAL,RECOMMENDED 3. Detect the machine type Existingboot loaders: OPTIONAL Newboot loaders: MANDATORY 4. Setup the kernel tagged list Existingboot loaders: OPTIONAL,HIGHLYRECOMMENDED Newboot loaders: MANDATORY 5. Calling the kernel image (with special settings) Existingboot loaders: MANDATORY Newboot loaders: MANDATORY Reference http://www.arm.linux.org.uk/developer/booting.php 34
Part- III: UBoot Tool - mkimage
Build mkimage and intall [root@testu-boot-1.1.2]# [root@testu-boot-1.1.2]# make tools cp tools/mkimage/usr/bin
Usage: mkimageA arch O os T type C compressa loadaddre entrypoint\ n named data_file[:data_file] outputimage
Example 1: Kernel [root@testtftpboot]# [root@testtftpboot]# gzip -9 < Image > Image.gz mkimage n Kernel 2.4.18 A arm O linux \ > T kernel C gzip a 30008000 e 30008000 \ vmlinux-2.4.18.img > -d Image.gz Example 2: Kernel+RFS [root@testtftpboot]# mkimage n Kernel+initrd 2.4.18 A arm O linux \ > T multi C gzip a 30008000 e 30008000 \ :initrd.gz multi-2.4.18.img 35 > -d Image.gz
Part- III: U-boot-1.1.2 UBoot trace - Linux boot (1/3) /include/image.h
Image header 36
Part- III: U-boot-1.1.2 UBoot trace - Linux boot (2/3) /common/cmd_bootm.c
do_bootm()
Read image header Check image magic number Verify image header checksum Verify image data checksum Show image information For IH_TYPE_STANDALONE, Check hdr->ih_comp Uncompress image Check hdr->ih_type For IH_OS_LINUX, Check hdr->ih_os run corresponding OS function run do_bootm_linux(), whichis in /lib_arm/ armlinux.c 37 run fromits hdr->ih_ep; Otherwise,handleit later Uncompressimageusinggzip or bzip2basedon ih_comp
must be the sameto
IH_MAGIC
Part- III: U-boot-1.1.2 UBoot trace - Linux boot (3/3) /lib_arm/armlinux.c
do_bootm_linux() see P.xx for whats bootargs theKernel = (void (*)(int, int, uint))ntohl(hdr-> ih_ep ); If initrd exists, Check whether initrd image exists load it as well disableinterrupts turn off I/D-cache flush I/D-cache ARMusesr0~r3for functionparameters. So, this will make r0 = 0 cleanup_before_linux (); r1 = arch_number r2 = boot_params theKernel (0, arch_number, boot_params); beforestartupKernel 38
*commandline = getenv ("
bootargs
");
Setup Tagged list setup_start_tag() setup_memory_tags() setup_initrd_tag( ) setup_commandline_tag(commandline) setup_end_tag()
ARM Linux Kernel Boot Requirement http://www.arm.linux.org.uk/developer/booting.php
ARM Instruction Set Instruction set encoding Conditional field Data processing instructions Branch instructions Load-store instructions Software interrupt instruction Program status register instructions Semaphore instructions Coprocessor instructions Extending instructions
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ARM Thumb Mode Why Thumb? Instruction set encoding Branch instructions Data processing instructions Load and store instructions Switching between ARM and Thumb mode
use.
ARM Exceptions and Interrupts Exception vector table Exception modes Exception and interrupt handling
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Detailed Outline
ARM Firmware Bootloader Standalone code Example of initialization
Copyright (c) 2006 by Ajay Dudani May not be reproduced or redistributed for commercial use.
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Detailed Outline
ARM Caches Memory hierarchy Cache policy Flushing policy Software performance
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Detailed Outline
ARM MMU and MPU Protected memory Example of memory protection Virtual memory concepts Example of virtual memory system
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Outline
ARM Technology Overview ARM Tools & Products ARM Processor ARM Toolchain ARM Instruction set Thumb instruction set ARM exception and interrupts ARM Firmware ARM Caches Memory management and protection ARM Future development Copyright (c) 2006 by Ajay Dudani May not be reproduced or redistributed for commercial use. 17
ARM Technology Overview
ARM: The Architecture For The Digital World ARM is a physical hardware design and intellectual property company ARM licenses its cores out and other companies make processors based on its cores ARM also provides toolchain and debugging tools for its cores
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ARM Technology Overview (2)
Companies licensing ARM IP: 3Com Agilent Technologies Altera Epson Freescale Fijitsu NEC Nokia Intel IBM Microsoft Motorola Panasonic Qualcomm Sharp Sanyo Sun Microsystems Sony Symbian Texas Instruments Toshiba Wipro
Source: ARM Website
and many more 19
ARM History
Acorn Computer Group developed worlds first RISC processor in 1985
Roger Wilson and Steve Furber were the principle developers
ARM (Advanced RISC Machines) was a spin out from Acorn in 1990 with goal of defining a new microprocessor standard
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ARM History (2)
Acorn Computer Group
Source: Wikipedia
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ARM History (3)
ARM delivered ARM6 in 1991 Introduced 32 bit addressing support New instruction for program status registers Variant used in Apple Newton PDA
By 1996 ARM7 was being widely used Microsoft started port of WinCE to ARM Added multimedia extensions
Exponential growth from then on
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ARM and StrongARM
Intel gained certain IP from ARM as part of lawsuit settlement and modified ARM architecture branding it as StrongARM
StrongARM name was changed to XScale Processor SA1000 , SA1100
XScale is close to ARMv5 instruction set
XScale division of Intel was sold to Marvel Inc. in 2006
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ARM Today
ARM7xxx 3 stage pipeline Integer processor MMU support for WinCE, Linux and Symbian Used in entry level mobiles, mp3 players, pagers ARM9xxx 5 stage pipeline Separate data and instruction cache Higher end mobile and communication devices Telematic and infotainment systems ARM and Thumb instruction set
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ARM Today (2)
ARM11xxx 7 stage pipeline Trustzone security related extensions Reduced power consumption Speed improvements More DSP and SIMD extensions Used in PDA, smartphones, industrial controllers, mobile gaming
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ARM Processor Family
ARM has devised a naming convention for its processors
Revisions: ARMv1, v2 v6, v7
Core implementation: ARM1, ARM2, ARM7, StrongARM, ARM926EJ, ARM11, Cortex
ARM11 is based on ARMv6
Cortex is based on ARMv7
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ARM Processor Family (2)
Differences between cores Processor modes Pipeline Architecture Memory protection unit Memory management unit Cache Hardware accelerated Java and others
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Examples: ARM7TDMI No MMU, No MPU, No cache, No Java, Thumb mode ARM922T MMU, No MPU, 8K+8K data and instruction cache, No Java, Thumb mode ARM1136J-S MMU, No MPU, configurable caches, with accelerated Java and Thumb mode
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Naming convention ARM [ x ][ y ][ z ][ T ][ D][ M][ I ][ E ][ J ][ F ][ S ]
x Family y memory management/protection z cache T Thumb mode D JTAG debugging M fast multiplier I Embedded ICE macrocell E Enhanced instruction (implies TDMI) J Jazelle, hardware accelerated Java F Floating point unit S Synthesizable version Copyright (c) 2006 by Ajay Dudani May not be reproduced or redistributed for commercial use. 29
Outline
ARM Technology ARM Tools & Products ARM Processor ARM Toolchain ARM Instruction set Thumb instruction set ARM exception and interrupts ARM Firmware ARM Caches Memory management and protection ARM Future development Copyright (c) 2006 by Ajay Dudani May not be reproduced or redistributed for commercial use. 30
ARM Tools & Products
Disclaimer: All owners own their respective trademarks Copyright (c) 2006 by Ajay Dudani May not be reproduced or redistributed for commercial use.
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ARM Chips
ARM Ltd Provides ARM cores Intellectual property
Analog Devices ADuC7019, ADuC7020, ADuC7021, ADuC7022, ADuC7024, ADuC7025, ADuC7026, ADuC7027, ADuC7128, ADuC7129
Atmel AT91C140, AT91F40416, AT91F40816, AT91FR40162 Freescale MAC7101, MAC7104, MAC7105, MAC7106 Samsung S3C44B0X, S3C4510B Sharp LH75400, LH75401, LH75410, LH75411 Texas Instruments TMS470R1A128, TMS470R1A256, TMS470R1A288 And others
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ARM Development Tools
Compilers: GNU Compiler ADS from ARM (older version) RVCT Real View compiler tools from ARM 3rdParty Debugging GNU gdb Lauterbach JTAG/Trace32 tools ETM hardware debugging & profilingmodules Windriver tools
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ARM Single Board Computers
TS-7200 ARM Single board computer 200 MHz ARM9 processor with MMU 32 MB RAM 8 MB Flash Compact flash 10/100 Ethernet
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ARM Single Board Computers (2)
Cirrus Logic ARM CS98712 16 MB RAM 1MB Flash 1 Serial port LED lights
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ARM Single Board Computers (3)
LN24x0/LP64 200 Mhz ARM9 processor LCD controller Touchscreen USB, IrDA ports HDD and CD-ROM support Speaker JTAG ports
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Recommended Text
ARM System Developers Guide Sloss, et. al. ISBN 1-55860-874-5 ARM Architecture Reference Manual David Seal ISBN 0-201-737191 Softcopy available at ARM system-on-chip architecture Steve Fuber ISBN 0-201-67519-6 www.arm.com
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Outline
ARM Design Philosophy
ARM core uses RISC architecture Reduced instruction set Load store architecture Large number of general purpose registers Parallel executions with pipelines But some differences from RISC Enhanced instructions for Thumb mode DSP instructions Conditional execution instruction 32 bit barrel shifter
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ARM Programming Model
A=B+C
To evaluate the above expression Load A to a general purpose register R1 Load B to a general purpose register R2 Load C to a general purpose register R3 ADD R1, R2, R3 Store R1 to A
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Registers
ARM has a load store architecture
General purpose registers can hold data or address
Total of 37 registers each 32 bit wide
There are 18 active registers 16 data registers 2 status registers
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Registers (2)
Registers R0 thru R12 are general purpose registers R13 is used as stack pointer (sp) R14 is used as link register (lr) R15 is used a program counter (pc) CPSR Current program status register SPSR Stored program status register
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 (sp) R14 (lr) R15 (pc) CPSR SPSR
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Registers (3)
Program status register CPSR is used to control and store CPU states CPSR is divided in four 8 bit fields Flags Status Extension Control
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Registers (4)
Program status register flags N:1 Negative result Z:1 Result is zero C:1 Carry in addition operation C:0 Borrow in subtraction operation V:1 Overflow or underflow
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Registers (5)
Program status register controls I:1 IRQ interrupts disabled F:1 FIQ interrupts disabled T:0 ARM Mode T:1 Thumb Mode
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Registers (6)
Program status register control modes 0b10000 User mode 0b10001 FIQ mode 0b10010 IRQ mode 0b10011 Supervisor mode 0b10111 Abort mode 0b11011 Undefined mode 0b11111 System mode
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Processor Modes
Processor modes are execution modes which determines active registers and privileges List of modes Abort mode Fast interrupt mode Interrupt mode Supervisor mode System mode Undefined mode User mode All except User mode are privileged modes User mode is used for normal execution of programs and applications Privileged modes allow full read/write to CPSR
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Banked Registers
Of total 37 registers only 18 are active in a given register mode
User/System Supervisor R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 (sp) R13_svc (sp) R14 (lr) R14_svc (lr) R15 (pc) CPSR SPSR SPSR_svc
Abort
FIQ
IRQ
Undefined
R13_abt (sp) R14_abt (lr)
R8_fiq R9_fiq R10_fiq R11_fiq R12_fiq R13_fiq (sp) R14_fiq (lr)
R13_irq (sp) R14_irq (lr)
R13_und (sp) R14_und (lr)
SPSR_abt
SPSR_fiq
SPSR_irq
SPSR_und 48
Pipeline
Pipelining is breaking down execution into multiple steps, and executing each step in parallel
Basic 3 stage pipeline Fetch Load from memory Decode Identify instruction to execute Execute Process instruction and write back result
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Pipeline (2)
Fetch Cycle 1 ADD
Decode
Execute
T im e
Cycle 2
SUB
ADD
Cycle 3
CMP
SUB
ADD
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Pipeline (3)
ARM7 has a 3 stage pipeline Fetch, Decode, Execute
ARM9 has a 5 stage pipeline Fetch, Decode, Execute, Memory, Write
ARM10 has a 6 stage pipeline Fetch, Issue, Decode, Execute, Memory, Write
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Pipeline (4)
In theory, each instruction is one instruction cycle
In practice, there is interdependency between instructions Solution: instruction scheduling
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Memory Protection
Two modes for ARM memory protection Unprotected mode No hardware protection, software does protection of data between tasks Protected mode Hardware protects areas of memory and raises exceptions when policy is voilated ARM divides memory to regions and programmer can set attributes on regions ARM provides mechanisms to define and set attributes of regions programmatically
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Memory Management
ARM supports memory management and virtual memory Programmatically access translation lookaside buffers ARM memory management unit also supports Fast Context Switching Extensions that optimizes use of caches in multitasking environments Details in later section
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Outline
Toolchain
GNU Tools gcc binutils ld as GNU Linker GNU assembler Front end to GNU compiler Binary tools
And others gdb GNU Debugger
uClib Small footprint C Library
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Toolchain (2)
GCC Invoked language specific modules Invoked assembler and linker arm-elf-gcc arm-elf-gcc test.c o test arm-elf-gcc test.S o test command
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Toolchain (3)
GCC ARM specific options mapcs-frame frame mbig-endian mno-alignment-traps : Generate big endian code : Generate code that assumes that : Generate ARM procedure call compliant stack
MMU does not trap on handling misaligned data mcpu=name : Specify CPU name; gcc can determine what
instructions it can use to generate output accordingly mthumb msoft-float : Generate code for ARM Thumb mode : Generate code assuming floating point hardware
is not present. Do floating point operation optimization in software Refer to GCC manual page for more on compiler options
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Inline assembly
Developer can insert ARM assembly code in C code for example printf (Hello ARM GCC); __asm__ (ldr r15, r0); printf (Program may have crashed);
Above code will corrupt program counter, so use inline assembly carefully Also, it may lead to non portable code
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Inline assembly (2)
Developer can force use of certain registers using extended assembly asm ( assembler template : output operands /* optional */ : input operands /* optional */ : list of clobbered registers /* optional */ ); Example int a = 10, b; __asm__ (mov %0, %1 : =r(b) : =r(a)); :
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Inline assembly (3)
Developer can request variable to be assigned to specific register register int regVar __asm__(%r4); Can be used with local and global variables Need ffixed-<reg> compiler option for global variables Refer to GCC Inline Assembly reference for more examples
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GNU Toolchain
Reference: www.gnuarm.org www.sourceware.org/binutils/ www.gnu.org/software/gdb/ www.sourceware.org/insight/ www.uclibc.org
GCC improvements for ARM www.inf.u-szeged.hu/gcc-arm/
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ARM Toolchain
ADS: ARM Developer Suite is older version of compiler, assembler and linker tools from ARM
RCVT: Latest ARM compiler, assembler and linker
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ARM Toolchain
ARM also provides support for RealView tools it acquired as part of Keil acquisition JTAG Support: ARM provides debugging tools to be used with JTAG supported hardware ETM Support: Embedded Trace Module is hardware debug unit that extends on-target debugging capabilities by providing extra memory and registers for debugging purpose Refer to www.arm.com and www.keil.com/arm/
for details on ARM tools
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Other Toolchains
GNU X-Tools www.microcross.com
IAR ARM Kit www.iar.com
Intel Development Suite for XScale www.intel.com
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Outline
ARM Instruction Set
Overview
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ARM Instruction Set (2)
Condition fields
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Add
Subract
Multiply
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Bit shifting
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Status register operation
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Semaphore instruction
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Placeholder page
73
Outline
Thumb Instruction Set
Overview of 16 bit mode
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Thumb Instruction Set (2)
Thumb Instruction set details
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Thumb Instruction Set (3)
Switching between ARM and Thumb mode
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Outline
Exceptions
Exception handling is a programming language or hardware mechanism to catch runtime errors
C++ and Java support exception handling in software
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14.
void func() { try { int a = 100/0; } catch(...) { cout << "Caught exception" << endl; return; } cout << "No exception detected!" << endl; return; }
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Exceptions (2)
ARM support 7 exception modes Developers can write custom exception handlers to deal with exception conditions For example: Consider a system that crashes if PC is corrupted. This will cause an exception. In corresponding exception handler, programmer can save state of all registers to file system for debugging and reset
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Exceptions (3)
ARM Exceptions in order of priority Reset Data abort FIQ IRQ Prefetch abort Undefined instruction Software interrupt
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Reset exception
Highest priority exception
The reset handler runs in supervisor mode Handler is generally located at 0x00000000 In Reset handler, FIQ and IRQ are disabled Other exceptions are not likely to occur when in reset handler
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Reset exception (2)
Actions performed when reset is de-asserted R14_svc SPSR_svc CPSR[4:0] CPSR[5] CPSR[6] CPSR[7] PC is set to unpredictable value is set to unpredictable value is 0b10011 supervisor mode is 0 execute in ARM mode is 1 disable fast interrupts is 1 disable normal interrupts = 0x00000000
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Data abort exception
Data abort exception mean software is trying to read/write an illegal memory location Data abort has higher priority than FIQ While handling this more, IRQ is disabled The abort handler should not cause further aborts Consider case of prefetch abort in abort handler This will cause abort handler to be reentered Abort handler is generally located at 0x00000010
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Data abort exception (2)
Actions performed on data abort R14_abt SPSR_svc CPSR[4:0] CPSR[5] CPSR[6] CPSR[7] PC = 0x00000010 = address of abort instruction + 8 = CPSR is 0b10111 abort mode is 0 execute in ARM mode is unchanged is 1 disable normal interrupts
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Fast interrupt
FIQ exception mode exists if developer wants to handle certain interrupts faster Additional banked registers in FIQ mode make execution fast Higher priority in IRQ Disabled IRQ and FIQ Default ARM cores do not handle nested interrupts FIQ handler is generally located at 0x0000001C
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Fast interrupt (2)
Actions performed on fast interrupt R14_fiq execute + 4 SPSR_fiq CPSR[4:0] CPSR[5] CPSR[6] CPSR[7] PC = 0x0000001C = CPSR is 0b10111 FIQ mode is 0 execute in ARM mode is 1 disable fast interrupts is 1 disable normal interrupts = address of next instruction to
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Normal interrupt
Normal interrupt is lower priority than fast interrupts
Disabled IRQ when handling normal interrupts
Default ARM cores do not handle nested interrupts
IRQ handler is generally located at 0x00000018
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Normal interrupt (2)
Actions performed on normal interrupt R14_irq SPSR_irq CPSR[4:0] CPSR[5] CPSR[6] CPSR[7] PC = address of next instruction to execute + 4 = CPSR is 0b10010 IRQ mode is 0 execute in ARM mode is unchanged is 1 disable normal interrupts = 0x00000018
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Prefetch abort
If processor reads instruction from undefined memory, it causes a prefetch abort exception Prefetch abort occurs when instruction reaches execution stage of pipeline Disabled normal interrupts when handling prefetch abort Prefetch abort handler is generally located at 0x0000000C
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Prefetch abort (2)
Actions performed on prefetch abort R14_abt execute + 4 SPSR_irq CPSR[4:0] CPSR[5] CPSR[6] CPSR[7] PC = 0x0000000C = CPSR is 0b10111 abort mode is 0 execute in ARM mode is unchanged is 1 disable normal interrupts = address of next instruction to
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Undefined instruction
When executing coprocessor instructions, ARM waits for coprocessor to acknowledge that it can execute the instruction If no coprocessor can handle given instruction, undefined instruction exception is raised In simulators, this can be used to simulate coprocessor in software Undefined instruction handler can parse instructions and process them in software simulator Undefined instruction handler is generally located at 0x00000004
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Undefined instruction (2)
Actions performed on undefined instruction R14_und SPSR_und CPSR[4:0] CPSR[5] CPSR[6] CPSR[7] PC = address of next instruction to execute = CPSR is 0b11011 undefined mode is 0 execute in ARM mode is unchanged is 1 disable normal interrupts = 0x00000004
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Software interrupt
Software interrupt exception is used to enter supervisor mode to execute a privileged OS function Typically applications run in user mode and kernel in supervisor mode Execution of any system call will cause SWI software interrupt to change mode to supervisor mode Software interrupt handler is generally located at 0x00000008
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Software interrupt (2)
Actions performed on software interrupt R14_svc after SWI SPSR_irq CPSR[4:0] CPSR[5] CPSR[6] CPSR[7] PC = CPSR is 0b10011 supervisor mode is 0 execute in ARM mode is unchanged is 1 disable normal interrupts = 0x00000008 = address of next instruction to execute
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Exception table
Memory layout 0x00000000 0x00000004 0x00000008 0x0000000C 0x00000010 0x00000018 0x0000001C High vectors Some implementation keep this table in 0xFFFF0000 to 0xFFFF001C range which is known as high vector location reset exception handler undefined instruction handler software interrupt handler prefetch abort handler data abort handler normal interrupt handler fast interrupt handler
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Exception handling
1. 2. 3. 4.
Exception is raised Lookup to exception table to find exception handler Exception handler is executed Return from exception handler
Application MOV r0, r1 SWI 0x1D ADD r0,r2,r0
0x00 0x04 0x08 0x0c 0x10 0x14 0x18 0x1c
Exception Vector Table Reset_Handler Undef_Handler SWI_Handler PAbt_Handler DAbt_Handler ... IRQ_Handler FIQ_Handler
SWI Handler ... ... ... MOV PC, R14_svc
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Outline
ARM Firmware
Now the earth was formless and empty. Darkness was on the surface of the deep. God's Spirit was hovering over the surface of the waters. God said, Let there be light, and there was light. For the processor, someone needs to read application and copy it into RAM to start execution What address to copy it to RAM Setup stack and heap Transfer control to application
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System initialization
Two stages of initialization: 1. Initialize stack, vectors and I/O system 2. Initialize application and associated libraries
The system set up could be With an RTOS, in which case it does initialization of system environment (stack, vectors etc.). User application then starts with main() or RTOS specific entry point Without an RTOS, ROM code handles transferring control to user application. User application need additional code to setup system environment
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Initialization
Execution environment: 1. At reset Processor is in SVC mode Interrupts are disabled Running in ARM mode
2. Entry point on powerup Use assember directive ENTRY to specify entry point ROM code usually has entry point 0x00
101
Initialization (2)
Execution environment: 3. Setup exception vector table If ROM is mapped to address 0x00, it contains hard coded exception vector table If ROM is mapped elsewhere, exception table is copied to RAM address 0x00 4. Initialize memory system Initialize memory management and memory protection before running any application code Setup stack pointers, sp_SYS, sp_IRQ etc. Initialize I/O devices. Note interrupts are still disabled Change processor mode to user mode. At this stage we are ready to initialize application
102
Initialization (3)
Application environment: 1. Initialize ZI writable region with zeroes 2. Initialize non zero data by copying initialization values 3. Pass on control to main function
103
Initialization Example
Consider user code:
1. int main (void)
2. {
3.
printf (Hello ARM World);
4.
return 0;
5. }
104
Initialization Example (2)
Consider ROM mapped at address 0x24000
RW Data
Application Code
0x24000000
Vector table & Init Code
Above image shows setup before application has been loaded
105
At initialization, ROM code at 0x24000000 is in flash. Flash is mapped at 0x24000000 address
On Reset, Flash will be remapped by hardware to address 0x00 ROM init code performs certain initialization Initialized vector tables and data regions to RAM Copies application code from ROM to RAM Sets REMAP bit to map RAM to address 0x00
106
Code (RO+RW) 0x24000000
Code (RO+RW) I/O Addresses Stack
Flash UART
Heap ZI data Initialized RW data Code aliased from 0x24000000
RAM
Code (RO+RW) Vector table
107
Firmware
Typically the ROM code is bootloader Developers configure the bootloader as per their requirements to specify memory map, bootup address, policy to copy code to RAM Application code can Either be single binary with RTOS in which case RTOS provides basic OS services For simple applications there may be no RTOS, just application compiled with simplified C library
108
Firmware (2)
Some examples of bootloaders Grub Lilo RedBoot Some examples of RTOS Linux eCos vxWorks Some examples of embedded libraries Busybox ucLib
109
Outline
Memory hierarchy
Registers
Caches
RAM Memory
Hard disk
External & network storage
111
Caches
A cache
is high speed memory location
generally used to reduce latency in memory access for data and instructions Whenever CPU reads data from (slower) RAM, a copy is stored in (faster) cache If CPU access the same data again, it can be served from cache. This is a A write buffer memory speeds up writing to main hit
112
Cache properties
Set associativity Fully associative Direct mapped Cache size Unified or separate Caches for data and instruction Write through or write back Property associated with mechanism to write data back to main memory Read allocate or write allocate Property associated dealing with cache miss Replacement strategy Property associated with replacing cache data with newer ones
113
Cache issues
Address mapping changes Virtual or physical address can get remapped
Cache coherence and invalidation
Direct Memory Access (DMA) operation can update main memory without going through cache
114
ARM and caches
Cache and write buffers are controlled with coprocessor registers
Register 1: C bit: Cache enable/disable W bit: Enable/disable write buffer I bit: Enable/disable instruction cache RR bit: Cache replacement strategy
115
ARM and caches (2)
Register 7: Controls cache and write buffers Different opcodes written to this register result in different behavior. Some examples: Invalidate entire instruction/data cache Flush prefetch buffer Writeback outstanding cache data to main memory
116
ARM and caches (3)
Register 9: Controls cache lockdown Caches can slow down worst case execution time of code and be undeterministic because It needs to handle cache misses Write back of data to main memory can take time Cache mechanism can load more data than request by process Cache lockdown helps control these parameters to remove undeterministic behavior in critical code
117
Caches
Caches can provide huge performance improvements to the system
As a developer, one should do profiling by changing various caching options when developing board support package
118
Outline
Memory Management
We saw earlier that during initialization, code from ROM is copied to RAM
But what is code size is larger than RAM available? Options: Do not allow program to be loaded Load only part of program and swap parts of program as requested Or allow program to see large virtual memory
120
Virtual Memory
Program is loaded into RAM until full
Application starts running with partial program loaded in memory
When program wants to access virtual memory address that is not in physical memory it generated a page fault
Page fault handler is responsible to get new page of memory into RAM
121
ARM MMU
MMU handles translation from virtual to physical memory Presents 4 GB address space Supports 3 options for memory granularity: 1 MB sections 64 KB pages 4 KB pages Page fault is indicate by abort Abort handler is responsible for fetching pages
122
ARM Memory Protection
Memory protection is required to prevent one application from overwriting other applications code
This facility can be enabled by using MMU
Using MMU, system goes to abort mode when application accesses memory to which it does not have permissions
123
ARM Memory Protection (2)
ARM MPU allows memory protection without using MMU facilities ARM defines up to 8 protection regions which can be configured through MPU registers MPU offers good memory protection option for cases Where 8 protection regions are enough Virtual memory is not required
124
MPU Registers
CP15 M bit: enable/disable memory protection Cache bits: control if cache buffer is enabled/disabled Buffer bits: control if write buffer is enabled/disabled Access control bits: control access rights of 8 regions Mechanism to define 8 memory regions
125
Outline
ARM Future Development
ARMv7 based processors ARM Cortex-M3 TI OMAP Qualcomm Scorpion
In embedded systems its not just speed, its about speed/watt
Approximately 2 billion ARM based devices selling each year and growing!
127
ARM Future Development (2)
Qualcomms SnapDragon based on Scorpion: 1 GHz microprocessor CDMA and UMTS network support Upto 12 mega pixels camera support Enhanced multimedia support DVD quality display support GPS support Support for various peripherals like hard disk, monitor, USB devices, bluetooth etc.
128
ARM Future Development (3)
Its ARM v/s x86 for UMPC and mobile devices market
129
Outline
Questions & Comments
131

ARM Operating Modes

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ARM Operating Modes

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ARM Operating Modes User mode: FIQ Fast Interrupt: IRQ Normal Interrupt: Supervisor mode (SVC): Abort

ARM Architecture Overview

ARM Architecture Overview

ARM Architecture Overview

Program Status Register (PSR) CPSR : CurrentProgramStatusRegister SPSR : SavedProgramStatusRegister

ARM Architecture Overview

Prefetch Abort Fetch an instruction from an illegal address

ARM Architecture Overview

ARM Exception Vectors

ARM Architecture Overview

Load and store instructions (x4) Singleregister load/storeinstructions(x2) Multiple-register load/storeinstructions(x2)

ARM Architecture Overview

ARM Instruction Summary

ARM Architecture Overview

ARM Instruction Summary

ARM Architecture Overview

Part- I: UBoot S tartup

1. setupexceptionvector table, _start: and eachhandler

In /board/smdk2410/ 1. enableand set memory 2. returnto /cpu/arm920t/

reset: 1. returnto reset : 16

In lib_arm/board.c 1. Flashinitialization 2. Init environment

3. Set IP addr 4. Set MACaddr 5. Devicesinitialize In common/main.c 6. Consoleinitialize 7. Enableinterrupts 8. EnableEthernet

Part- I: U-boot-1.1.2 Linker Descriptor /board/smdk2410 /u-boot.lds

[root@test u-boot-1.1.2]# make : arm-linux-ld Bstatic Tuboot-1.1.2/board/smdk2410/u-boot.lds Ttext 0x33F80000 :

U-boot-1.1.2/board/smdk2410 TEXT_BASE = 0x33F8000

/config.mk UBoot entry point address 18

Part- I: U-boot-1.1.2 UBoot traces tartup (1/7) /cpu/arm920t / start.S

Part- I: U-boot-1.1.2 UBoot traces tartup (2/7) /cpu/arm920t / start.S

Part- I: U-boot-1.1.2 UBoot traces tartup (3/7) /cpu/arm920t / start.S

Part- I: U-boot-1.1.2 UBoot traces tartup (4/7) /cpu/arm920t / start.S

Part- I: U-boot-1.1.2 UBoot traces tartup (5/7) /cpu/arm920t / start.S

Part- I: U-boot-1.1.2 UBoot traces tartup (6/7) /cpu/arm920t / start.S

Part- I: U-boot-1.1.2 UBoot traces tartup (7/7) /board/smdk2410 /memsetup.S

Part- III: Boot Requirements for Linux (2/6)

Part- III: Boot Requirements for Linux (3/6)

Device DMA to/from devices should be quiesced. 31

Part- III: Boot Requirements for Linux (4/6)

Part- III: Boot Requirements for Linux (5/6)

TAG format header TAG ID: TAG size: body (header+body)

depends on TAG type

ATAG_CORE ATAG_MEM ATAG_NONE A minimum tagged list

Part- III: Boot Requirements for Linux (6/6)

Part- III: UBoot Tool - mkimage

Build mkimage and intall [root@testu-boot-1.1.2]# [root@testu-boot-1.1.2]# make tools cp tools/mkimage/usr/bin

Part- III: U-boot-1.1.2 UBoot trace - Linux boot (1/3) /include/image.h

Part- III: U-boot-1.1.2 UBoot trace - Linux boot (2/3) /common/cmd_bootm.c

must be the sameto

Part- III: U-boot-1.1.2 UBoot trace - Linux boot (3/3) /lib_arm/armlinux.c

*commandline = getenv ("

Setup Tagged list setup_start_tag() setup_memory_tags() setup_initrd_tag( ) setup_commandline_tag(commandline) setup_end_tag()

ARM Linux Kernel Boot Requirement http://www.arm.linux.org.uk/developer/booting.php

ARM Firmware Bootloader Standalone code Example of initialization

ARM Technology Overview

ARM Technology Overview (2)

Source: ARM Website

and many more 19

Acorn Computer Group developed worlds first RISC processor in 1985

Roger Wilson and Steve Furber were the principle developers

ARM History (2)

Acorn Computer Group

ARM History (3)

Exponential growth from then on

ARM and StrongARM

StrongARM name was changed to XScale Processor SA1000 , SA1100