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CS501-Advance Computer Architecture

CS501-Assignment No. 1
Assignment Solution
Question: 1 Write short answers to the following questions: a. Differentiate between computer architecture and computer organization. Answer: Computer architecture: Computer architecture refers to the attributes of a computer that are visible to a programmer, including The instruction set The number of bits used to represent various data types I/O mechanisms Memory addressing modes, etc. Computer organization: Computer organization refers to the operational units of a computer and their interconnections that realize the architectural specifications. These include The control signals Interfaces between the computer and its peripherals Memory technology used, etc. b. Why is MIPS (millions of instructions per second) a poor measure of a computers performance? Answer: MIPS is defined as MIPS = IC/ (ET x 106) This measure is not a very accurate basis for comparison of different processors. This is because of the architectural differences of the machines; some machines will require more instructions to perform the same job as compared to other machines. c. What fields should be essentially specified in an instruction? Answer: Every instruction must contain encodings within it to specify the following four things, either explicitly or implicitly. Type of operation This is specified by the opcode. Place to find source operands The operand location may be explicitly specified, as in memory address or general register number, or it may be implicit within the opcode as in the

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CS501-Advance Computer Architecture accumulator in the accumulator based machines or on the stack of the stack based machines. Place to store the results The result location may need to be explicitly mentioned or it may be implicit in the opcode. Source of the next instruction In inline code the next instruction to execute is the next instruction in the sequence. In the instructions that alter the flow of the program statement execution the branch or jump address must be given as part of the current instruction. d. Identify the instruction type and describe its respective instruction format of the following SRC instruction neg R3, R4 Answer: Instruction Type Instruction Format Modified Type D Functionality: Negates (obtains 2s complement) R4 and stores in R3. 2-address format and register addressing mode is used. e. Define the Reverse Assembly. Answer: Conversion of a machine language instruction required to find the equivalent assembly language instruction is known as Reverse Assembly. Question: 2 Write the code to implement the following expression on 3, 2, 1, and 0 address machines. A=B x C D x E Answer: 3-Address mpy A,B,C mpy X,D,E sub A,A,X 2-Address load A,B mpy A,C load X,D mpy X,E sub A,X 1-Address lda B mpy C sta A lda D mpy E sub A sta A 0-Address push B push C mpy pop A push D push E mpy push A sub pop A

Question: 3

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CS501-Advance Computer Architecture Consider a machine having a 100 MHz clock and three instruction types with following parameters. Now suppose that two different compilers generate code for the same program. The instruction count for each is given as follows: IC in millions Control ALSU Data Transfer Instruction Type Control ALSU Data Transfer Code from compiler 1 5 2 2 CPI 2 3 4 Code from compiler 2 10 1 1

Compare the two codes according to MIPS and according to execution ti me. Answer: CPI = clock cycles for each type of instruction / IC, and ET = IC/(MIPS * 106) IC1= 5+2+2=9 CPI1= (52+23+42)/9=2.67, MIPS1= 100106/2.67106 = 37.49995 ET1 = 9*106/(37.49995*106) = 0.2368 Sec IC2= 10+1+1=12 CPI2= (102+13+14)/12 = 2.25, 6 6 MIPS2= 10010 /2.2510 = 44.44 ET2 = 12*106/(44.44*106) = 0.2700 Sec So code generated by compiler 2 has high MIPS rating. Question: 4 Identify the addressing modes of the following instructions: a. ldr R1, 14 b. ld R3, 6(R2) c. Stop d. str R7, 32 e. addi R3, R4, 25 f. nop g. ori R2, R4, 56

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CS501-Advance Computer Architecture h. lar R3, 48 Answer: a. b. c. d. e. f. g. h. Relative addressing mode Displacement addressing mode None Register relative addressing mode Immediate addressing mode None Immediate addressing mode Register relative addressing mode

Question: 5 Convert the following machine language instruction of SRC into the equivalent SRC assembly language instruction showing all the necessary steps. 724E8000 h Answer: 1. Write the given hexadecimal instruction in binary form 724E8000 h 0111 0010 0100 1110 1000 0000 0000 0000 b 2. Examine the first five bits of the instruction, and pick the corresponding mnemonic from the SRC instruction set listing arranged according to ascending order of op-codes 01110 b 14 d sub subtract 3. Now we know that this instruction uses the type D format, the 5-bit field after the opcode field represents the destination and the two 5-bits fields after destination represents two source registers respectively, and that the remaining 12-bits in the instruction are unused. 0111 0010 0100 1110 1000 0000 0000 0000 b
op-code ra rb rc 12-bits unused





0 h=0 d

4. Therefore, the assembly language instruction is sub R9, R7, R8

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