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IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, VOL. 55, NO.

2, APRIL 2013

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Detection of Electromagnetic Interference in Microcontrollers Using the Instability of an Embedded Phase-Lock Loop
Shih-Yi Yuan, Member, IEEE, Yu-Lun Wu, Richard Perdriau, Senior Member, IEEE, and Shry-Sann Liao, Member, IEEE

AbstractThis paper presents a combined hardwaresoftware mechanism for the detection of electromagnetic interference of a microcontroller (C) in daily usage. This detection mechanism is based on the instability of phase-lock loop embedded in the target C. It can detect the presence of EMI with higher sensitivity than polling the hardware status of the C internal registers and thus provides a better detection margin within the 10 kHz to 1 GHz EMI frequency range. Despite its relative slowness and its resource consumption, it is very robust, can be implemented in virtually any application software, and does not require any electromagnetic compatibility test equipment. Index TermsElectromagnetic compatibility (EMC), electromagnetic radiation, near elds, phase-locked loops.

I. INTRODUCTION

URRENT trend of consumer electronics requires compactness and durable power. Power supply voltages of such applications are drastically cut down to reduce power consumption along with a negative inuence on noise margin. In the meantime, radiofrequency interference (RFI) or electromagnetic interference (EMI) sources are becoming more and more ubiquitous due to ever growing wireless communication environment. In addition, data transfer rates are becoming much faster (up to several GHz) while system complexity and functionalities are increasing; printed circuit board (PCB) tracks in high-speed circuits are getting relatively longer and become electromagnetic (EM) antennas [1] which can propagate RFI up to sensitive devices or integrated circuits (ICs). Therefore, in normal operations and daily usages, electromagnetic susceptibility (EMS) issues of microcontroller (C) or embedded systems have become more and more important [2].

Manuscript received December 8, 2011; revised May 4, 2012 and July 30, 2012; accepted August 28, 2012. Date of publication October 26, 2012; date of current version April 11, 2013. This work was supported by the National Science Council (NSC) of the Republic of China under the Project 100-2221E-035-035 and NSC-101-2221-E-035-050. S.-Y. Yuan is with the Department of Communications Engineering, Feng Chia University, Taichung 40724, Taiwan (e-mail: yuanmark@gmail.com). Y.-L. Wu is with the Department of Ph.D. Program of Electrical and Communications Engineering, Feng Chia University, Taichung 40724, Taiwan (e-mail: p9840171@fcu.edu.tw). R. Perdriau is with the Department of Electronics and Physical Sciences, ESEO, Angers 49009, France (e-mail: richard.perdriau@eseo.fr) S.-S. Liao is with the Department of Communications Engineering, Feng Chia University, Taichung 40124, Taiwan (e-mail: ssliao@fcu.edu.tw). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TEMC.2012.2218285

Cs can be affected or even subject to total malfunction under powerful RFI in common environments. Modern C cannot determine whether RFI is strong enough to disturb its functionality during normal operations. Previous researches focused on IC EM simulation [3][5], IC EM measurement and analysis [5][7], IC EM modeling and parameter extraction [8][10], IC EM laboratory device design and modeling [11][13], or IC EM detection by laboratory equipment [7], [11], [12]. These research works are for different design phases. However, in nal products, it is still not possible to embed any EMI measurement device small enough into a C system to detect EMI for daily usages. The solution for detecting EMI under such conditions is a tough problem. It needs to inform users or to trigger some EMI defensive strategies through software interface. Thus, it requires a combined hardwaresoftware EMI detection mechanism. The mechanism can generate alert signals by special hardware, inform users by software, and activate proper EMI defensive software strategies embedded in the C. This paper focuses on building such detecting mechanism which can provide system software (for example, an operating system) with a presence of EMI piece of information or alert. This paper focuses mainly on the construction and validation of the proposed hardwaresoftware coworking detection mechanism. This paper also discusses the sensitivity of the mechanism, the congurability of the criterion, and the accuracy and overhead of the mechanism. The purpose of this paper does not study the failure mechanisms of any functional parts of a C. Just like other studies on C EMI modeling and parameter extractions [8][10], due to the complexity of C, the relationship between the proposed mechanism and the internal functional parts of a C is not this papers scope either. This detection mechanism requires several important characteristics: rst of all, it must be sensitive enough to detect external EMI when EMI appears. Second, the sensitive level adjustment and triggering should be easy and congurable. Third, it can provide some methods (or channels) to communicate with software. Fourth, it should be fast enough to decrease the response time of defensive software. Last but not least, it requires as few computing resources as possible in order to reduce detection overhead in such systems. Generally, a modern C is equipped with at least one programmable embedded phase-lock loop (PLL). The embedded PLL is used to keep the system clock accurate from jitter and

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instability. The effects of EMI on PLL are reported by Lee et al. [7]when H-eld strength is applied on PLL, a jitter variation is observed. A PLL includes a voltage controlled oscillator which is also proven to be very sensitive to power disturbances [6]. However, different intensity of EMI may or may not lead to loss of data or fail of a Cthe detection criteria should be more sensitive and respond faster before the failure conditions. Since the PLL is sensitive to external EMI, it fullls the rst detection mechanism requirement. As will be detailed in following sections, the proposed mechanism counts the status changes and the duration of these changes as criteria of the external EMI detection. Because the criteria depend on the counting of the status change and durations, one can easily change the alert condition (or sensitivity level) by modifying the tolerance of the deviation of the normal condition. Thus, the second requirement is fullled. Thanks to the current embedded PLL designs, the PLL is programmable and can reect its status to software system. The PLL status can be communicated between system hardware and software by polling or interrupt mechanisms [11]. In many Cs, the hardware statuses of peripherals are stored in status registers which can be queried by software. Thus, modern PLL can be used to feed EMI information to software through such software communication channel and the third characteristic is satised. Of course, the software communication channel requires a software loop to scan the status registers repeatedly. This kind of hardwaresoftware mechanism is called polling. Polling is not efcient and much CPU time is wasted. Another way for software to get the updating of the status registers is by a new kind of hardware help: interrupt mechanism. Special hardware is designed to raise an interrupt ag when a predened event occurs (for example, a state change of a status register). Interrupt mechanism is both response faster than polling mechanism and consumes less CPU time. All modern Cs are equipped with at least one PLL and PLL status register. Generally, modern Cs include PLL interrupt status registers as well. These designs make PLL software detection a good candidate for EMI detection. Due to the interrupt mechanism implemented in PLL, the last two requirements are fullled. However, the proposed mechanism depends on several hundreds of detection iterations for robustness. Thus, the current mechanism of the EMI detectiondecisionalert cycle is still slow. This can be traded off between the EMI detection false-alarm ratio and detection response time. Since a PLL is not designed for EMI detection purpose, some concerns can be raised. One of them is how can it be sure that, when a C is under an EMI aggression, the PLL is the most sensitive one and, hence, is the most suitable candidate for EMI detection. The second concern is that the PLL hardware is limited and is used for system synchronization. There is no dedicated PLL for the proposed EMI detection mechanism. The third concern is that a PLL can be stopped under very severe EMI aggression and, therefore, the proposed method is not applicable to such scenario. The fourth concern is how to design defensive software which can take countermeasures to avoid the loss of data when the proposed mechanism detects EMI.

These concerns may be addressed as follows. For the rst concern, the other functional parts (such as ALU, internal ash, internal RAM, etc.) are digital circuits. Research [14] has shown that the functionalities of digital circuits are less sensitive to EMI. If a device includes both analog and digital circuit (in this case, a C), the analog PLL EMI behavior is more sensitive than digital parts and can make early EMI warnings to the digital parts. About the second concern, this paper aims to demonstrate that the proposed hardwaresoftware mechanism can actually detect RFI through the use of an embedded PLL. If this concept is acknowledged and adopted by industry, it is quite certain that more suitable hardware or designs, based on this concept, will be integrated into stock Cs. For now, a designer can still implement this concept into a system by using a low-cost spare C dedicated to EMI detection if EMI detection is critical concerns in the applications. The third concern is important: the PLL may stop working under severe RFI, which leads to the proposed mechanism being unusable. This issue must be taken into account and many preliminary tests must be conducted in order to determine the validity domain of this method. This issue will be fully considered in Section II-C. It should be noticed that the immunity to electrostatic discharges, which can also disturb the PLL operation, is not the scope of this paper. The fourth concern is about the defensive software design issue but it is not the topic considered in this paper. Many different behaviors can be chosen once the system is aware of the EMI alert, for example, modifying the resolution of the analog todigital converter if RFI reduces its accuracy, saving critical data to nonvolatile storage, resetting or even shutting down the system in case of a more severe EMI aggression. Although this paper can inform software with the presence of EMI, the EMI defensive strategy and software must be customized according to the purpose of the target applications in target environments. This paper denes PLL lock time as the time from PLL being enabled to the time that system clock is locked by PLL. The proposed EMI detection mechanism bases on the counting of the PLL lock time to give an early stage EMI attacking warning. This is very important to life-critical or accuracy-critical embedded systems such as avionic system, guiding system, car electronics, etc. This method can only be implemented in embedded systems with the following characteristics. 1) The system must be equipped with at least one C. 2) The C must be equipped with at least one PLL functional part. 3) The status of the PLL functional part can be queried by software. It seems the limitations are many. However, these characteristics are generally included in modern Cs and the proposed method can be easily implemented. This paper proposes a method to detect the PLL lock times variation and its relationship to external EMI. The result shows that the proposed method can detect external EMI more sensitively. The extrasensitivity lefts the circuit more time to trigger (activate) strategies to dealing with EMI at early stage

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when the circuit is still functionally correct under external EMI attacks. A special PLL interrupt service routine (ISR) is designed for EMI detection; this ISR fullls both of the aforementioned requirements: it is a high-priority program with a fast response time. The ISR overhead of the detection mechanism can be neglected because it uses only small fraction of CPU time and memories. This paper also considers the sensitivity of the proposed method to EMI at different frequencies. The sensitivity is quantied by fault margin which is dened to be the RFI power difference between the malfunction of a target C and the detection of the RFI. Large fault margin means the detection mechanism can provide a C more time to trigger (activate) EMI defensive strategies. Negative fault margin at any interested frequencies means the failure of the proposed detection mechanism. The immunity of a C depends on what the EMS strategies or algorithms implemented in such C. The detection mechanism can only provide accurate information to the strategies. The proposed solution is for early warning of the external EMI and focuses on the software external EMI detection mechanism. In short, we provide a software EMI sensor mechanism. How the mechanism is used by EMS algorithm in a C is not what this papers topic. This paper is organized as follows. First, Section II introduces the experimental setup used in this study. Section III describes the concepts of the PLL-based detection method. Section IV presents all experimental results. Finally, Section V provides conclusions and perspectives. II. EXPERIMENTAL SETUP A. Device Under Test (DUT) The DUT of this paper is the same as in [12]. It is a 16-bit Freescale C belonging to the S12X family (MC9S12XDT256). The embedded PLL of the DUT can generate a stable internal clock from a lower frequency reference clock. The PLL output clock frequency is controlled by the input clock frequency and a programmable multiplication factor. The multiplication factors of the DUT are controlled by two registers: SYNR and REFDV. The SYNR register controls the multiplication factor of the PLL and the REFDV register (loop divider) provides a ner granularity for the PLL multiplier steps. The PLL frequency can be set by following formula: PLLCLK = 2 OSCCLK (SYNR + 1) (REFDV + 1) (1)

Fig. 1.

Test board.

Fig. 2.

Experimental injection setup.

The test board is designed by the University Institute of Technology (IUT) in Tarbes, France. It includes three seven-segment displays, one LCD module and four pushbuttons (see Fig. 1). In order to determine if the C is still in normal operation or has failed under interference, the embedded software makes one seven-segment display ash. Another seven-segment display is designed to be an alert signal. It will be turned ON by the system when the system gets an RFI alert from the implemented detection mechanism. B. Injection Method The RFI coupling method used in this paper is near-eld injection (NFI), which is under standardization process by the International Electrotechnical Commission (IEC) under the IEC 62132-9 reference. The setup for this experiment includes a signal generator, a 30-W power amplier (Amplier Research AR30W1000B), a power meter, and a directional coupler. Fig. 2 shows the proposed architecture, where P1 is the incident power and P2 is the reected power. The actual injected power can be calculated from P1, P2 and the attenuations of the directional coupler. In order to ensure a homogeneous eld coupling into the target C, a skate probe [9] is used courtesy of IUT Tarbes. The skate probe is a square PCB with a 1-cm2 area, covered by copper foil tape and tted with an SMA connector. These broadband probes make it possible to disturb the DUT with less power. An H-eld probe is used as an RFI source in this paper. The H-probe has two orientations (Hx and Hy ). Hx is

where OSCCLK is the frequency of the external reference clock and PLLCLK the frequency of the PLL output clock. The PLL has two states: locked and unlocked. Without EMI, the PLL state should change only once (from unlocked to locked) after it is enabled. The rst action to be taken in EMI testing is to conrm that, without EMI, this state actually changes once and not back and forth. For subsequent experiments, a 4-MHz input clock (crystal oscillator) is chosen.

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Fig. 5. Fig. 3. H -probe orientations.

Denition of clock count.

Fig. 4.

RFI detection setup.

determined with the current loop parallel to the VDDPLL pin, as shown in Fig. 3. The distance between the probe and the DUT is 1 mm. The whole RFI detection setup, with the generator, the amplier and the coupler, is shown in Fig. 4. We have run several testing routines (not shown in this paper) to make sure some of the targeted functionalities (PLL, I/O, and ALU) are correct. However, fully functional checking is out of our capability. A commercial product can be trusted to be fully functional when the design follows the design rule supported by the manufacturer and we have to trust the manufacturers QC procedure. This C is a commercial product from Freescale and is considered to be fully functionally qualied in the case of no EMI power injected. C. Verication of the Validity Domain of the Method This verication addresses the third concern raised in the introduction: the PLL may crash under sever RFI aggression, which will lead to the proposed hardwaresoftware mechanism fail. It is veried that the C can still working under maximum interference power (45 dBm) delivered by the amplier. Previous papers [10], [15] used 25 and 40 dBm maximum injection power, respectively. If the environment RFI is within this range, the presented mechanism can work successfully. If RFI levels are more severe than 45 dBm, it is likely to fail like other pure hardware-based EMI detection mechanism. If this limit is reached without any failure, the DUT is considered immune enough. Although only one C case (MC9S12XDT256, with many samples) is tested, this case study demonstrates that modern PLL technology can be robust enough to operate under 45-dBm power in an NFI experiment.

Fig. 6.

CC measurement ow by PLL ISR and PIT.

III. PROPOSED EMI DETECTION METHOD A. Denition of Clock Count (CC) The CC is dened as the number of system clock periods from the effective activation of the PLL to its locking, namely, the duration of the unlocked state (see Fig. 5). When applying EMI to the DUT, the loss of lock condition (the sequence of lock unlock lock) is also checked in this C. We use our power amplier to the largest power level allowable (see Fig. 2) and we nd no such condition occurs. However, if other C has such condition, our method can be modied by adding another Loss of Lock Counter (LoLC) for counting the number of loss of lock conditionsthe modied mechanism depends on these two counters: LoLC and CC. The modied mechanism would be slightly more complex. However, it can be easily applied to such C and can still provide an early stage warning. B. CC Measurement by ISR In order to measure CC, a specic PLL ISR is designed using an embedded timer (PIT, periodic interrupt timer), as depicted in Fig. 6. When the C starts executing its main routine, the ISR is also set to Active as indicated in Fig. 5. At the same time, the PIT is enabled to count down. When the PLL status switches to the locked state, the ISR is waken up by the interrupt signal, reads the PIT counter to measure the CC value, and transfers the CC value to the main program. This method also makes it possible to conrm the lock only once hypothesis in the

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Fig. 8. PLCs with RFI (dotted) and without RFI (solid) by NFI at 620-MHz disturbance injection (PLL output frequency = 4 MHz).

same statistics ow. However, due to no other literature results can be compared with, the comparisons of these frequencies reomitted. As can be seen, PLCs with and without EMI can be told apart, which means that PLC is sensitive to EMI. The worst case of the total RFI detection time tRFIdetect of the proposed EMI detection method implantation in this paper can be represented as
Fig. 7. Flowchart of CCs statistics.

tRFIdetect = ((NINIT + NISR + NSTAT ) Tclk Ncc + CCDur ) Nfreq . (2)

absence of EMI. The ISR ow and pseudocode are shown in Fig. 6. C. PLL Lock Curve (PLC) and Distance Measurement According to the CC measurement method developed above, 500 CCs are successively measured for a given PLL output frequency. The procedure of CC measurements are repeated for each output frequency, from 8 to 160 MHz in 8-MHz steps (20 PLL output frequencies), both with and without EMI. From the experiments conducted on the S12X C, it is noticed that the measured CCs (both with and without EMI) are limited to a small set of values, such as 406, 422, 438, 454, . . . , 598. Therefore, it is possible to build a histogram of the occurrences of these CCs. A CC histogram at a specic PLL locking frequency is dened as a PLC. A PLC without RFI is called the base PLC and a PLC with RFI is called the target PLC. The owchart for the establishment of PLCs is shown in Fig. 7. The experiments are performed after the whole setups are powered ON. The PLL is programmed according to Fig. 7 to be ON (or OFF) at specied time. There are 20 different histograms for these 20 different f . Each of them is measured under a single PLL output frequency. Since the process needs 500 CCs for each loop, the detection time is slow (about 0.5-s per frequency). This is about the same processing speed or a little faster than a standard IEC 62132-9 test for one frequency, but it can be implemented without any electromagnetic compatibility equipment. Fig. 8 plots the PLC under 620-MHz injection frequency which is one of the most sensitive frequencies for this DUT [12]; the output frequency of Fig. 8 is set to 4 MHz (f = 4 MHz) which is the same as [12]. Other frequencies can be measured by the

where NINIT , NISR , and NSTAT are the machine code count of the ISR/timer initialization, the PLL interrupt service routine, and the routines for statistics; Tclk is the clock period; Ncc is the number of a CC histogram measurement (or one f -iteration of Fig. 7); CCDur is the average time depending on ambient RFI condition; and Nfreq is the number of RFI frequency. In this paper, NINIT = 16, NISR = 3, NSTAT = 30, Tclk = 0.25 s (4 MHz), and Ncc = 500; the CCDur is among 94 146 s (depends on the RFI frequency injected); and Nfreq = 20. Although tRFIdetect is expressed by (2) for worst case estimation, CCDur is overlapped with other CPU execution time because CCDur is determined by PLL component and does not use CPU during the detection time. Thus, the proposed method does not waste any CPU time. The RFI detection can concurrently coexist with other programs (for example, the statistics program (NSTAT ) or any other unrelated application software). Thus, the worst case detection time for one frequency is less than 6.3 ms and the overall 20 frequencies detection time is less than 0.13 s which is much less than the time for current laboratory measurement, not to mention the preparation time for such measurement. Another issue is that due to the detection mechanism is based on interrupt mechanism. There is no loop inside the single RFI detection ow. Only the Ncc is a loop count for multiple RFI frequency detections. Since PLCs are sensitive to RFI, it is possible to detect EMI by comparing PLCs directly at a given PLL frequency. Since the establishment of a PLC consists in repeated measurements, only quasi-static EMI can be detected. The difference between two

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Fig. 10.

Flowchart of the RFI detection using the PLC method.

Fig. 9. Extraction of the nal base PLC from ten PLCs without EMI. (a) Ten measurements of the base PLC. (b) Average of (a).

PLCs can be dened by the squared Euclidean distance:


n

dist(A, B ) =
i =1

(ai bi )2

(3)

where A is the base PLC, B the target PLC, i the index in the CC set of values, and n the number of different CC values in the set. In this paper, the base PLC is constructed by averaging ten PLCs without EMI, as shown in Fig. 9; in fact, it can be seen that the PLC distributions of different measurements are very similar and stable. Then, the squared Euclidean distance between the target PLC (with EMI) and the base PLC is computed. The variations of more/less PLC measurements have been done from ve times up to 10 000 times. However, ten times PLC variation is very close to the variation of 10 000 times and we choose ten to save detecting time. The EMI detection threshold is set to the largest distance among the ten PLCs obtained without EMI. If the computed distance is greater than this threshold, it means that the C is being subject to EMI. In this case, the software triggers an EMI alarm which is indicated by one of the sevensegment displays. The detection algorithm is summarized in Fig. 10. IV. EXPERIMENTAL COMPARISON WITH OTHER DETECTION METHODS A. Register-Based Detection Method The most convenient procedure for the detection of operation failures in the S12X consists in monitoring its status registers, particularly the clock status register (CRGFLG). In all

Fig. 11. Immunity comparison between PLL ON (solid) and PLL OFF (dotted), courtesy of [12].

subsequent paragraphs, the test setup is the one described in Section II-A. The rst experiment, described in [12], consisted in determining the inuence of the PLL on the immunity of the C by E-eld skate probe. These results are obtained by polling the CRGFLG register for any change; with the PLL OFF, the self-clocked mode (SCM) bit is the only one used to identify a possible malfunction whereas, with the PLL ON, the LOCK and TRACK bits, respectively, representing the lock/unlock and acquisition states, are also polled. Fig. 11 represents the S12X susceptibility plots for both PLL-ON and PLL-OFF states (injected power versus frequency) between 10 MHz and 1 GHz; the lower the injected power, the more susceptible the C according to the criterion. It can be seen that, except for a few discrete frequencies (450 and 620 MHz) where the detection threshold of the PLL (LOCK bit) is lower (by 9 dB at 620 MHz), the register-based detection method using the PLL does not carry any improvement over the SCM bit.

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Fig. 12. Comparison between the register- and PLC-based detection method for a H x injection by the frequency of disturbance at 620 MHz.

Fig. 14. Susceptibility plots versus frequency in H y eld for the register-based method (dotted) and the PLC-based method (solid).

Fig. 13. Susceptibility plots versus frequency in H x eld for the register-based method (dotted) and the PLC-based method (solid). Fig. 15. Characterization of the fault margin for H x probe.

B. PLC-Based Detection Method With the aforementioned results as a reference, another experiment is conducted using the PLC method described in Section III. Since the PLL seemed to be particularly sensitive at 620 MHz, this frequency is chosen for the rst test. Fig. 12 plots measurement results for both methods in the same operating conditions (Hx injection). These preliminary results are quite promising (PLC improves the detection threshold by 7.9 dB over register polling). Therefore, a broadband EMI test is performed. As explained in Section II-A, one display is made to ash while another one showed detection information. The maximum injected power is set to 45 dBm (maximum power delivered by the amplier). Consequently, in subsequent plots, a 45 dBm susceptibility level indicates that the C could not detect any interference with either method. Figs. 13 and 14 depict susceptibility plots with both methods, respectively, for Hx and Hy injections. The dotted lines in Figs. 13 and 14 are similar but not the same to the solid line in Fig. 11. In Fig. 11, the power is injected by E-probe, while in Figs. 13 and 14 the power are injected by H-probe with two vertical directions. These experimental results show that the PLC-based method is always more sensitive than the register-based method in every frequency band. In Fig. 13, the minimum difference is 2.75 dB at 260 MHz. The Hy injection (see Fig. 14) presents similar results except for 560580 MHz where PLC is less sensitive. At this time, the authors do not have any explanation for this phenomenon.

Fig. 16.

Characterization of the fault margin for H y probe.

This demonstrates that PLC is a very efcient method that can detect EMI as low as 23 dBm (200 mW) depending on frequency. C. Fault Margin The fault margins (dened in Section I) of different frequencies are the sensitivity measurement of the proposed mechanism. The failure criterion is the output malfunction of the DUT. In this paper, the output malfunction of the DUT is the seven-segment display to stop ashing. As would be expected, the detection of EMI through the internal PLL is more sensitive than that through the Cs output responses by external measurement device (see Figs. 15 and 16). The fault margins of every frequency are non-

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negative. It means the EMI can be detected before the DUT fails at interested frequency range. Due to the EMI nonsensitive to some frequencies, these frequencies fault margins are zero (the power for EMI detection and failing of DUT are beyond the maximum power injected). V. CONCLUSION This paper proposes a combined hardwaresoftware mechanism for the detection of EMI in Cs. This detection mechanism uses the instability of integrated PLLs which are proven to be very sensitive to EMI. The purpose of this paper is the electromagnetic interference detection in microcontrollers through the relationships between the PLC variation and intensity of external EMI, the behavior changes due to such EMI, and the detection mechanism of such change. This paper neither studies the failure mechanisms of any functional parts nor the relationships of the detecting mechanism to any functional parts. This method is based on counting the number of clocks needed for the PLL to lock after being started. An NFI test in magnetic eld demonstrated that the EMI detection threshold using this method is much lower (by an average of 10 dB) than by polling the status register of the internal clock manager. Therefore, the inclusion of a second PLL dedicated to this mechanism could be a valuable solution to enhance EMI detection capabilities in Cs. The next step should consist in using this information to design defensive software which could take appropriate countermeasures to protect data in case of strong EMI. REFERENCES
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[11] J. L. Peterson and A. Silberschatz, Operating System Concepts, 6th ed. New York: Wiley, 2011. [12] S. Baffreau, R. Perdriau, and S. Y. Yuan, Assessment of the immunity of a dual-core 16-Bit microcontroller to near-eld injection, presented at the Int. Workshop Electromagn. Compat. Integrated Circuits, Toulouse, France, Nov. 2009. [13] S. Pan, J. Kim, S. Kim, J. Park, H. Oh, and J. Fan, An equivalent threedipole model for IC radiated emissions based on TEM cell measurements, in Proc. IEEE Int. Symp. Electromagn. Compat., Jul. 2010, pp. 652656. [14] B. Hu and K. Y. See, Impact of analog/digital ground design on circuit functionality and radiated EMI, presented at the 7th Electron. Packag. Technol. Conf., Singapore,, Dec. 2005. [15] A. Boyer, S. Bendhia, and E. Sicard, Modeling of a mixed signal processor susceptibility to near-eld aggression, in Proc. IEEE Int. Symp. Electromagn. Compat., Jul. 2007, pp. 15. Shih-Yi Yuan (M07) received the Ph.D. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, in 1997. He joined the Department of Communications Engineering, Feng Chia University, Taichung, Taiwan, where he is currently an Associate Professor and Member of Integrated Circuits Electromagnetic Compatibility (ICEMC) Center, Feng Chia University. His research interests include compiler design, ICEMC modeling, software solution for electromagnetic compatibility problems. Yu-Lun Wu was born in Changhua, Taiwan, in 1976. He received the M.S. degree in communication engineering from Feng Chia University, Taichung, Taiwan, in 2007, where he is currently working toward the Ph.D. degree in Ph.D. Program of Electrical and Communications Engineering. His research interests include integrated circuit electromagnetic compatibility and radio-frequency circuit design.

Richard Perdriau (M01SM07) was born in Angers, France, in 1971. He received the engineering degree in electronics and computer science from ESEO, Angers, in 1992, the Ph.D degree in applied science from the Catholic University of Louvain, Louvain-la-Neuve, Belgium, in 2004, and the Accreditation to Supervise Research (HDR) degree in electronics from the University of Rennes 1, Rennes, France, in 2012. Since 1992, he has been an Associate Professor at ESEO, in the elds of microelectronics and embedded systems. His research interests include electromagnetic compatibility of integrated circuits, mixed-signal hardware description languages, and integrated circuit design. Shry-Sann Liao (M02) was born in Taiwan in 1954. He received the B.S. and M.S. degrees in physics from Tamkang University, Tamshui, Taiwan, in 1976 and 1978, respectively, and the Ph.D. degree in physics from the University of Texas at Dallas, Richardson, in 1988. From 1979 to 1983, he was a Nuclear Engineer at the Taiwan Power Company, Taipei, Taiwan, where he was engaged in providing education and training to engineers who had worked in nuclear power plants. Since 1988, he has been an Associate Professor in the Department of Electronic Engineering, Feng Chia University, Taichung, Taiwan, where he has also been in the Department of Communication Engineering since 2002. In 2006, he had been a Professor in the Department of Communication Engineering and the Director of the integrated circuits electromagnetic compatibility Center. He has taught at various levels and has developed specialized courses in radio-frequency circuit design at both the undergraduate and graduate levels. The current research interests include electromagnetic compatibility, integrated circuits electromagnetic compatibility, and microwave.