1.1 Introduction and Motivation

Analysis of Ultra Low Power Fully Programmable Frequency Divider 2012-13
Dept of Electronics & Communication, SIT Tumkur Page 1

Chapter 1
Introduction
1.1 Introduction and Motivation
Over the last two decades, the continuous shrinking in the feature size of MOSFETs has
increasingly attracted the research and development of low-power radio frequency CMOS
integrated circuits. For mobile wireless communications, low-power operations are of crucial
importance for the mobile units as the battery lifetime is limited by the power consumption and the
low power consumption also helps to reduce the operating temperature resulting in more stable
performance. For the modern transceiver architecture, a fully integrated frequency synthesizer with
low power voltage-controlled oscillators (VCO) for quadrature signal generation and low power
frequency dividers with multi-channel selection is always a topic of interest in research.
Phase-locked loops (PLLs) are widely used in radio frequency synthesis. The PLL based frequency
synthesizer is one of the key building blocks of an RF front-end transceiver. The existing wireless
standards like Bluetooth and 802.11a/b/g offer relatively high data rates at the expenses of high
power consumption and high cost. The IEEE 802.15.4 standard has been specifically designed to
supply for the needs of low cost, low power, low data rate and short range wireless networks. Most
synthesizers have not scaled down the supply voltage to reduce the power consumption of digital
blocks. It is believed that power consumption of the frequency synthesizer (mainly frequency
divider) can be reduced significantly by further simplifying the circuit structures, and adapting
some power saving techniques to the digital blocks such as frequency dividers.

1.2 Approach
The project gives detailed analysis, specifications and design of low power fully programmable
integer-N frequency divider which a critical block of frequency synthesizers for IEEE 802.15.4.
The approach of the project is as follows:



Analysis of ultra-low power 2/3 TSPC prescaler
A detailed analysis of power consumption and propagation speed of the dynamic logic flip-flops is
carried out and an ultra-low power True-single-phase clock (TSPC) 2/3 prescaler is analysed which
is verified in the architecture of TSPC 32/33 prescaler in 180nm CMOS technology.
A low power TSPC 47/48 prescaler
The analysis of a fully programmable 1 MHz resolution divider for the 2.4 GHz frequency
synthesizer using a 32/33 prescaler, a 7-bit programmable P-counter and a 5-bit swallow S counter
results in 1 MHz output with duty cycle less than 25%. In order to improve the duty cycle, a low
power TSPC 47/48 prescaler is analyzed without an additional flip-flop. This new architecture is
similar to the architecture of 32/33 prescaler with an additional inverter.
1.3 Applications:
Frequency divider is a critical block of frequency synthesizer which has major applications in,
Local oscillators for modulation and demodulation
Phase locked loop (PLL) synthesizers and other counting circuits
Radio receivers
Mobile telephones
GPS systems
1.4 Organization of the report
Chapter 1 gives an introduction about the programmable frequency dividers and its principle in
brief. Chapter 2 provides in detail the literature survey of CMOS logic family and also its electronic
analysis. Chapter 3 describes steps in cadence tool to build the schematics and layouts and their
verification using gpdk180 library of the EDA tool. Chapter 4 describes the implementation of the
prescalers using cadence tools demonstrating the difference between the traditional and modified
architectures. Chapter 5 gives an exhaustive account of how the traditional prescaler is modified to
obtain new architectures.



Chapter 2
Literature Survey
John P Uyemura suggests that for any combinational or sequential circuit design, the analysis and
design of inverter is must. The analysis of inverter makes complex circuit analysis simpler as it
consists of less number of transistors and any flip-flop design can be compared with the inverter.
Hence analysis of inverter characteristics and design plays major role [1].
Neil H. E. Weste and Kamran Eshraghian suggests for low power sequential circuit design many
parameters have to be considered such as propagation delay, rise time fall time etc.. These all
parameters can be understood only by simple circuits such as inverter [2].
Sung Mo Kang and Yusuf Leblibici suggests a fabrication related issues like, layout design rules,
full custom mask layout design and also it suggests threshold voltage parameters by varying the
source to bulk voltage and it is mathematically analyzed such as defining the importance of gate
voltage ranges of NMOS-FET and PMOS-FET [3].



2.1 Logic family
A logic family of monolithic digital integrated circuit devices is a group of electronic logic gates
constructed using one of several different designs, usually with compatible logic levels and power
supply characteristics within a family were produced as individual components, each containing
one or a few related basic logical functions, which could be used as building blocks to create
systems or as so called glue to interconnect more complex integrated circuits. A logic family may
also refer to a set of techniques used to implement logic within VLSI integrated circuits such as
central processors, memories, or other complex functions. Packaged building block logic families
which are compatible to CMOS (complementary metal oxide semiconductor logic) and TTL
(Transistor Transistor Logic).
2.2 Comparison between TTL and CMOS logic families
TTL stands for Transistor-Transistor Logic. It is a classification of integrated circuits. The name is
derived from the use of two Bipolar Junction Transistors or BJTs in the design of each logic gate.
CMOS is also another classification of ICs that uses Field Effect Transistors in the design. A brief
comparison between these logic families highlights the advantage of CMOS as follows:
2.2.1 Characteristics of CMOS logic family
Some important characteristics of the CMOS logic family are as given below
Dissipates low power - The power dissipation is dependent on the power supply voltage,
frequency, output load, and input rise time. At 1 MHz and 50 pF load, the power dissipation
is typically 10 nW per gate [1].
Short propagation delays - Depending on the power supply, the propagation delays are
usually around 25ns to 50ns.
Rise and fall are controlled - The rise and falls are usually ramps instead of step functions,
and they are 20 to 40% longer than the propagation delays.



2.2.2 Characteristics of TTL logic family
Some important characteristics of the TTL logic family are as given below
Power dissipation is usually 10 mW per gate.
Propagation delays are 10 ns when driving a 15 pF/400 ohm load [2].
2.2.3 Advantages of CMOS over TTL
Some important advantages of the CMOS over TTL logic family are as given below
CMOS components are typically more expensive that TTL equivalents. However, CMOS
technology is usually less expensive on a system level due to CMOS chips being smaller
and requiring less regulation.
CMOS allows much higher density of logic functions in a single chip compared to TTL.
CMOS circuits do not draw as much power as TTL circuits while at rest. CMOS requires
lower current draw requires less power supply distribution, therefore causing a simpler
design.
Due to longer rise and fall times, the transmission of digital signals becomes simpler and
less expensive with CMOS chips.
2.3 Electronic analysis of MOSFET
The voltage applied to the gate controls the flow of electrons from the source to the drain. A
positive voltage (for NMOS) or negative voltage (for PMOS) applied to the gate attracts electrons
(holes) to the interface between the gate dielectric and the semiconductor. These electrons form a
conducting channel called the inversion layer. No gate current is required to maintain the inversion
layer at the interface since the gate oxide blocks any carrier flow. The net result is that the applied
gate voltage controls the current between drain and source.
2.3.1 Pass Characteristics of NMOS-FET
The schematic of NMOS-FET (nFET) pass transistor is as shown in the Fig. 2.1. The input pulse V
1

has a voltage 1.8V and the output voltage V
out
is measured across the capacitive load C
out
. The value
of capacitor represents the total capacitance at the output node and has several contributions.


Fig.2.1. Schematic Diagram of NMOS-FET
Fig.2.2 summarizes the behavior of the device when NMOS is used to pass the voltage from left to
right. Applying V
DD
to the gate ensures that the nFET is ON and the device acts like a closed
switch. If a logic 0V is applied to source of NMOS, this results in an output voltage of V
out
= 0V as
shown in Fig. 2.2. if input voltage of V
1
= V
DD
is applied, V
out
is reduced to a value
V
out
=V
DD
V
Tn
(2.1)

V
out
=1.8V 0.53V

V
out
=1.273V
Which is less than the input voltage V
1
this is referred to as threshold voltage loss. It arises due to
the fact that the minimum value of the gate-source voltage. So it needs to maintain an on state Gate
to source voltage.
V
GSn
=V
Tn
= 0.53V. (2.2)


Fig. 2.2 NMOS pass characteristic
From the waveforms in Fig 2.2 it can be concluded that,
NMOS-FET can pass strong logic 0
NMOS-FET can pass weak logic 1
2.3.2 Pass Characteristics of PMOS-FET
A pFET has opposite pass characteristics as of nFET. To examine the properties of PMOS, logic 0 is
applied to Gate as shown in Fig.2.3.

Fig. 2.3 Schematic diagram of pass PMOS-FET
However if input voltage of V
1
= 0 V is applied, V
out
is not equal to 0 V, but


V
out
=V
Tp
= 0.619V (2.3)
This is also due to a threshold effect. In order to keep the pFET ON it requires a minimum source-
gate voltage of
V
SGp
=V
Tp
= 0.619V (2.4)
From the waveforms in Fig 2.4 it can be concluded that,
PMOS-FET can pass strong logic 1
PMOS-FET can pass weak logic 0

Fig. 2.4 PMOS Pass characteristic
Thus following rules can be written as a basis for the design:
1. Use pFETs to pass logic 1 voltages of V
DD
.
2. Use nFETs to pass logic 0 voltages of V
SS
= 0V.
These allow us to build circuits that can pass the ideal logic voltages 0V and V
DD
to the output
terminal.
2.4 Summary
In this chapter, the different logic families for the integrated circuits are discussed. Based on the
discussion CMOS logic family was opted for the design part and implementation of the low power
circuits because of its many advantages over the TTL logic family. The pass characteristics of
NMOS-FET and PMOS-FET are observed.
Analysis of Ultra Low Power

Dept of Electronics & Communication,

Chapter 3
Implementation using Cadence Tools

Cadence on virtuoso platform provides tools for designing full
includes schematic entry, be
realization of silicon chips, system
quality [3].
3.1 Design Steps using Cadence Software
1. Create Library
In command Interpreter
Attach design library to
Fig. 3.1 c
2. Schematic Entry
In CIW, execute: File
In the blank schematic window add components from the respective library and set their
specifications to the requirement.
Add wires to the schematic, check and save, as shown in Fig 3.2. The CIW window is
checked for any errors or warning
Analysis of Ultra Low Power Fully Programmable Frequency Divider
Dept of Electronics & Communication, SIT Tumkur
Cadence on virtuoso platform provides tools for designing full-custom integrated circuits which
includes schematic entry, behavioral modeling and circuit simulation. Cadence enables the
realization of silicon chips, system-on-chip devices, and complete systems at lower costs with high
Design Steps using Cadence Software
In command Interpreter Window (CIW) or library manager execute:
Attach design library to an existing technology library and select gpdk as shown in Fig. 3
Fig. 3.1 creating a new library from the CIW window
New cell view.
specifications to the requirement.
checked for any errors or warnings in the schematic.
Fully Programmable Frequency Divider 2012-13
Page 9
custom integrated circuits which
havioral modeling and circuit simulation. Cadence enables the
chip devices, and complete systems at lower costs with high
IW) or library manager execute: File New Library
an existing technology library and select gpdk as shown in Fig. 3.1

reating a new library from the CIW window


3. Symbol creation
In the schematic window, execute: Create
Fill in the Symbol Generation Options (which include the positions and direction of pins)
appropriately, check and save, as shown in Fig 3.3.
4. Test schematic
In CIW, execute: File
A blank schematic window for the test schematic design appears.
Add the components using create instance.
Complete the connect
observed for any errors.
Fig. 3.2 Creation of TSPC schematic
In the schematic window, execute: Create Cell view From Cell view.
check and save, as shown in Fig 3.3.
Fig. 3.3 Creation of TSPC symbol
New Cell view
A blank schematic window for the test schematic design appears.
Add the components using create instance.
Complete the connection, check and save, as shown in Fig. 3.4. The CIW window is
observed for any errors.
Page 10

From Cell view.

ion, check and save, as shown in Fig. 3.4. The CIW window is


Fig. 3.4 Creation of TSPC test schematic
5. Simulation with spectre
In the test schematic window, execute: Launch
Choose Analysis as per
In the simulation window, execute: Outputs
In the simulation window, execute: simulation
Observe the transient plots
In the simulation window, execute: Session

Fig. 3.5 Simulation with spectre in ADEL environment
Fig. 3.4 Creation of TSPC test schematic
Simulation with spectre
In the test schematic window, execute: Launch ADEL, as shown in Fig 3.5
Choose Analysis as per requirement and set the specifications.
In the simulation window, execute: Outputs To be plotted select on schematic
In the simulation window, execute: simulation Net List
Observe the transient plots
In the simulation window, execute: Session Save State.
Page 11

ADEL, as shown in Fig 3.5
To be plotted select on schematic



6. Delay calculation
From the graph obtained after simulation, execute: Tools
window as shown in Fig. 3.6.
Select the delay function from the list of functions
Provide the two necessary signal inputs for delay calculation from the graph or the
schematic window.
In the same window, execute: Apply
Fig. 3.6 Delay calculation using the in
3.2 Design methodology
CADENCE: Electronic design automation
designing electronic systems such as
together in a design flow that chip designers
One of the EDA softwares is CADENCE DESIGN SYSTEM.
3.2.1 Design specifications
The bottomup design flow for a transistor
specifications. The specifications typically describe the expected functionality (Boolean operations)
of the designed block, as well as the maximum allowable delay times, the silicon area and other
properties such as power dissipation. Usually, the design specifications allow c
From the graph obtained after simulation, execute: Tools Calculator, which opens up the
window as shown in Fig. 3.6.
Select the delay function from the list of functions provided. Clear buffer and stack.
In the same window, execute: Apply Evaluate the buffer
Fig. 3.6 Delay calculation using the in-built calculator
Design methodology
Electronic design automation (EDA or ECAD) is a category of software tools for
designing electronic systems such as printed circuit boards and integrated circuits
that chip designers use to design and analyze entire semiconductor chips.
One of the EDA softwares is CADENCE DESIGN SYSTEM.
Design specifications
up design flow for a transistor-level circuit layout always starts with a set of design
ecifications typically describe the expected functionality (Boolean operations)
properties such as power dissipation. Usually, the design specifications allow c
Page 12
Calculator, which opens up the
provided. Clear buffer and stack.

built calculator
) is a category of software tools for
integrated circuits. The tools work
use to design and analyze entire semiconductor chips.
level circuit layout always starts with a set of design
ecifications typically describe the expected functionality (Boolean operations)
properties such as power dissipation. Usually, the design specifications allow considerable freedom


to the circuit designer on issues concerning the choice of a specific circuit topology, individual
placement of the devices, the locations of input and output pins, and the overall aspect ratio (width-
to-height ratio) of the final design. The basic components used, along with their specifications have
been provided in Table. 3.1

Table.3.1 Design specifications of basic components used in simulation

Component

Specifications Library
pMOS
Width w = 3 um
Length l = 180nm

gpdk 180
nMOS
Width w = 1.7um
Length l = 180nm

gpdk 180
V
pulse

Voltage V1 = 0 V
Voltage V2 = 1.8 V

analogLib
V
dc
Voltage V
dc
= 1.8 V
analogLib

3.2.2 Selecting P/N ratio
The circuit is designed using standard PMOS and CMOS feature size 180nm with the PMOS to
NMOS ratio being 2 because the mobility of the electrons is double compared to mobility of the
holes. Static CMOS gates are a ratio less circuit family; the gates will work correctly for any ratio
of PMOS sizes to NMOS sizes. However, the ratio does influence switching threshold and delay, so
it is important to optimize the P/N ratio for high speed designs. Using a higher or lower P/N ratio
favors rising or falling outputs, respectively. For example, with a P/N ratio of 4/1, the input does not
have to fall as far as V
dd
/2 before the output could switch. Such a circuit is called high skewed gate
and use it on paths where the critical transition is a rising output. Similarly, a 1/1 P/N ratio could be
used in a low skewed gate for critical falling outputs.


3.2.3 Creating schematic
The method for describing the transistor level or gate level design is via the schematic editor.
Schematic editors provide simple, intuitive means to draw, to place and to connect individual
components that make up the design. The resulting schematic drawings must accurately describe
the main electrical properties of all components and their interconnections. Power supply and
ground connections, as well as all pins for the input and output signals of the circuit. This
information is crucial for generating the corresponding netlist, which is used in later stages of the
design. The generation of a complete circuit schematic is therefore the first important step of the
transistor-level design flow. Usually, some properties of the components (e.g. transistor dimensions)
and/or the interconnections between the devices are subsequently modified as a result of iterative
optimization steps. These later modifications and improvements on the circuit structure must also
be accurately reflected in the most current version of the corresponding schematic. An example of a
TSPC schematic has been shown in Fig. 3.7.

Fig. 3.7 Schematic of TSPC circuit


3.2.4 Symbol creation
If a certain circuit design consists of smaller hierarchical components (or modules), it is usually
very beneficial to identify such modules early in the design process and to assign each such module
a corresponding symbol (or icon) to represent that circuit module. This step largely simplifies the
schematic representation of the overall system. The symbol view of a circuit module is an icon that
stands for the collection of all components within the module. A symbol view of the circuit is also
required for some of the subsequent simulation steps, thus, the schematic capture of the circuit
topology is usually followed by the creation of a symbol to represent the entire circuit. The shape of
the icon to be used for the symbol may suggest the function of the module (e.g. logic gates AND,
OR, NAND, NOR), but the default symbol icon is a simple rectangular box with input and output
pins. Note that this icon can now be used as the building block of another module, and so on,
allowing the circuit designer to create a system-level design consisting of multiple hierarchy levels.
3.2.5 Simulation of schematic
After the transistor level description of a circuit is completed using the schematic editor, the
electrical performance and the functionality of the circuit must be verified using a simulation tool.
The detailed transistor level simulation of the design will be the first in depth validation of its
operation; hence, it is extremely important to complete this step before proceeding with the
subsequent design optimization steps. Based on simulation results, some of the device properties
such as transistor width-to-length ratio are modified in order to optimize the performance.
As the first step, the symbol of the component created is inserted and the inputs are provided with
variable pulses to cover all combinations possible. V
dd
supply is provided using Vdc = 1.8 V. the
outputs are connected to output pins. Analog Design Environment (ADEL) is launched and
transient analysis is chosen. This analysis is performed for a desired period with moderate accuracy.
The outputs to be plotted are selected from schematic and the simulation is run for these
specifications. The delay is then calculated from the response obtained.
3.2.6 Mask layout
Physical layout design is very tightly linked to overall circuit performance (area, speed and power


dissipation) since the physical structure determines the transconductances of the transistors, the
parasitic capacitances and resistances, and the silicon area which is used to realize a certain
function. The physical (mask layout) design of CMOS logic gates is an iterative process which
starts with the circuit topology and the initial sizing of the transistors.
3.2.7 Design Rule Check (DRC)
The created mask layout must conform to a complex set of design rules, in order to ensure a lower
probability of fabrication defects. A tool built into the Layout Editor, called Design Rule Checker,
is used to detect any design rule violations during and after the mask layout design.
3.2.8 Extraction
The circuit extractor is capable of identifying the individual transistors and their interconnections
on various layers, as well as the parasitic resistances and capacitances that are inevitably present
between these layers. Thus, the extracted net-list can provide a very accurate estimation of the
actual device dimensions and device parasitic that ultimately determine the circuit performance.
3.2.9 Layout versus Schematic check (LVS)
The design called Layout-versus-Schematic (LVS) Check will compare the original network with
the one extracted from the mask layout, and prove that the two networks are indeed equivalent. The
LVS step provides an additional level of confidence for the integrity of the design, and ensures that
the mask layout is a correct realization of the intended circuit topology.
3.2.10 Post Layout Simulation
The electrical performance of a full-custom design can be best analyzed by performing a post-
layout simulation on the extracted circuit net-list. At this point, the designer should have a complete
mask layout of the intended circuit/system, and should have passed the DRC and LVS steps with no
violations. The detailed (transistor-level) simulation performed using the extracted net-list will
provide a clear assessment of the circuit speed, the influence of circuit parasitics


3.3 Summary
In this chapter, the implementation details of the various designs of Prescaler using Cadence has
been discussed, clearly outlining the specifications needed for every circuit design. Care was taken
to choose the P/N ratio as per the requirements, along with the other necessities. A comparison was
also provided regarding the number of gates and transistors used.



Chapter 4
Analysis of Ultra Low Power Prescaler
The prescaler is one of the most critical blocks in the synthesizer since it operates at the highest
frequency and consumes a large amount of power. Thus, the power reduction in the first stage of
the prescaler is important in realizing a low power frequency synthesizer. A dual-modulus
N N +1 prescaler such as divide-by-32/33, divide-by-64/65 and divide-by-128/129 usually
consists of a synchronous divide-by-2/3 or divide-by-4/5 circuit combined with several
asynchronous divide-by-2 circuits.
4.1 Prescaler
The high speed dual modulus prescaler is a critical functional block in frequency synthesizers
which uses pulse swallow frequency dividers which operates the prescaler at high frequencies and
consumes more power than the other circuit blocks of the frequency synthesizer. In a pulse swallow
frequency divider, the prescaler has two selectable division ratios N and N +1. It is combined with
programmable counters P and S as in Fig. 4.1 to perform a programmable division ratio of ( N
P +S ).
The prescaler is a synchronous circuit which is formed by D flip-flops and additional logic gates,
due to the incorporation of additional logic gates between the flip-flops to achieve the two different
division ratios, the speed of the prescaler is affected and the switching power increases. Various
flip-flops have been analyzed to improve the operating speed of dual-modulus prescalers. The
optimization of the D flip-flop in the synchronous stage is essential to increase the operating
frequency and reduce the power consumption. The high speed operation of MOS transistors is
limited by their low transconductance. Therefore, dynamic and sequential circuit techniques or
clocked logic gates such as, true single phase clocks must be used in designing synchronous circuits
to reduce circuit complexity, increase operating speed and reduce power dissipation. The state of
the art CMOS N N +1 prescalers have achieved maximum operating frequencies up to 2.4 GHz
using current mode logic (CML) architectures at the expense of power consumption. The fastest
frequency dividers were designed at fixed division ratios.


The power consumption and frequency of operation of TSPC and E-TSPC 2/3 prescalers are
analyzed and an ultra low power TSPC 2/3 prescaler is designed. Based on this Architecture a
32/33 prescaler and 47/48 prescaler is then simulated, which is highly suitable for high resolution
fully programmable frequency synthesizers.

Fig. 4.1 Topology of the Pulse Swallow frequency divider
4.1.1 Theory of operation
Prescaler divides the input frequency by N +1 or N based on the modulus control.
Program counter divides the prescaler output by P (fixed).
Swallow counter divides the prescaler output by S (fixed).
Start from reset, prescaler divides byN +1 until swallow counter is full.
After (N +1) S pulses at the input, the modulus control changes to N.
Continues to count until program counter is full.
Total pulses at the input = (N +1) S + N (P S) = NP +S
4.2 Synchronous 2/3 prescaler
An N N +1 DMP (dual modulus prescaler) consists of a synchronous prescaler and additional
logic gates to control the switching between the two different division ratios. Fig. 4.2 shows the
evolution of a simple 2/3 synchronous prescaler from divide-by-2 and divide-by-3 circuits. When
control MC goes high, the output of OR gate is equal to logic 1 and the output of AND gate is
always equal to the inverted output of DFF2 (Q2) such that the prescaler operates in the divide-by-2
mode as shown in Fig. 4.2 (a)


Fig. 4.2 a) Divide-by-2 circuit b) Divide-by-3 circuit c) Divide-by- 2 or 3 circuit
When control logic signal MC goes low, the output of OR gate is always equal to Q1, such that
prescaler operates in the divide-by-3 mode as shown in Fig. 3.1 (b). The output of the synchronous
2/3 prescaler is given by
out
= HC

]
in
3
+ HC
]
in
2
(4.1)
Frequency dividers designed based on digital counters cannot be implemented by standard digital
circuits. These digital counters cannot be synthesized directly using register transfer level (RTL)
description which relies on standard cells as high frequency of operation requires accurate
Architecture and optimization.
The main building block of the frequency dividers is D type edge-triggered flip-flop which are
constructed using level triggered latches. The most commonly used logic circuits for high frequency
dividers is either source-coupled logic (SCL) or current-mode logic (CML) circuits [4].



4.2.1 Current-mode logic (CML) dividers
The CML circuit is based on the use of differential stages with current steering topology. A divide-
by-2 circuit implemented using the CML logic type is shown in Fig. 4.3 along with its equivalent
transistor level schematic. A CML latch consists of NMOS differential pair transistors (M
n4
, M
n5
)
and a regenerative pair (M
n1
, M
n2
). The loads are PMOS transistors (M
p1
, M
p2
) which are always
operated in the triode region. When CLK is high, M
n6
turns-on and the differential pair transistors
compare the input amplitudes at gate terminals and pass the result to the output nodes. When CLK
is low, M
n3
turns-on and the regenerative pair transistors hold the output. The maximum operating
frequency is decided by the differential pair transistors since they decide how fast the input
amplitudes are sensed and transferred to the output nodes. The CML dividers have higher speed of
operation and higher power consumption compared to that of the dynamic logic dividers.

Fig. 4.3 CML divide-by-2 and gate level schematic of CML latch
One of the main advantages of CML logic circuits over dynamic logic circuits is the use of the
differential topology, which makes the current drained by the supply less variable. Moreover,


differential circuits reject disturbances coming from the substrate and power supply due to other
blocks. The current steering topology as shown in Fig. 4.3 helps in lowering the voltage head room.
However, the current of the clock transistors are not controllable which results in larger power
consumption [5]. The CML logic circuit is very sensitive to the input amplitude and also requires
buffers or level shifters at the output to drive the low frequency dynamic logic counters and hence,
dynamic logic dividers are preferred over CML logic dividers.
4.2.2 Dynamic logic dividers
The CMOS latches eliminate the static current consumption and use fewer transistors than the CML
latches do. They are slow due to the positive feedback (memory element) which introduces
additional delay to the switching time. The switching speed of the static circuits depends on two
factors namely, the current conduction level through a MOS transistor and parasitic capacitances.
Since the parasitic capacitances cannot be controlled, the switching speed is only improved by the
use of new and improved process. Alternatively, the memory element formed by a positive
feedback can be replaced by a charge storing capacitance, which is called as dynamic memory. The
dynamic logic circuit, instead of fighting the time constant limits induced by the RC parasitics,
accepts the presence of capacitances and uses them as integral parts of the circuit.

Fig. 4.4 Clocked-CMOS (C
2
MOS) logic latch


When CLK=1, both M
3
and M
2
are active IN=0 (1), the node S1 charges to 1 (0). When
CLK=0, the first stage goes into high-impedance state and the second stage accepts the data at
node S1 and passes it to the output node. Hence the output data is same as the input data. However,
the output voltage can only be maintained so long as the voltage across node S1 remains within an
appropriate range. Fig. 4.4 shows a clocked-CMOS (C
2
MOS) logic latch. The main drawback of
this topology is the requirement of complementary clock inputs for a single phase output. In an
asynchronous chain, when a divide-by-2 is implemented, an additional inverter is need at the output
to provide differential signals thus causing clock skew.

Fig. 4.5 Evolution of TSPC flip-flop from doubled p-C
2
MOS latch
For this reason, domino logic circuits also a part of the dynamic logic circuit family. The original
domino logic circuit requires a dual-phase clock, but a single-phase clock is developed using
doubled p-C
2
MOS latch as shown in Fig. 4.5 which avoids the need of the dual-phase clock and
clock skew problems. This architecture has higher speed and higher input sensitivity.


The TSPC flip-flop has two modes of operation namely; hold mode and evaluation mode as shown
in Fig. 4.6. In the hold mode (pre-charge phase), CLK=0and node S1 is pre-charged to a value
depending on the input signal IN and node S2 is pre-charged to VDD. As transistors M
7
and M
8

is turned-off, output node OUT becomes floating. In the evaluation mode, CLK=1 and if the
node S1 is pre-charged to VDD in the hold mode, node S2 is discharged and output node is
pulled up by the transistor M
7
. If the node S1 is pre-charged to 0 during the hold mode, node S2 is
not discharged, and output node is pulled down by the transistors M
8
and M
9
respectively.

Fig. 4.6 Operation of TSPC flip-flop a) hold mode b) evaluation mode

4.2.3 Propagation speed analysis of TSPC and E-TSPC flip-flops
In this section, the maximum operating frequency of the TSPC and E-TSPC flip-flops are analyzed.
In each stage, an E-TSPC flip-flop uses only two transistors while a TSPC flip-flop uses three
transistors. Of various dynamic logic CMOS circuits, TSPC and E-TSPC circuits operate with the
single-phase clock to avoid clock skew problems. To compare the speed performance of TSPC and
E-TSPC circuits, the first stage of both TSPC and E-TSPC circuits with their equivalent RC models
are analyzed as shown in Fig. 4.7.


(a) TSPC
Fig. 4.7 First stage and equivalent RC model of (a) TSPC (b) E
The charging and discharging time constants of the first stage
calculated using the RC ladder method, as follows

n1
= R
3
C
out

C
out
= C
db3
+2C
gd

p1
= (R1 +R2)C
C
x
= C
gs2
+C
gs1
+
C
p+
is the total depletion capacitance between the series PMOS transistors
capacitance. The propagation delay of the first stage TSPC flip
t
p_1SPC
=
0.69(:
p1
+
2
The charging and discharging time constants of the first sta

n2
= R
3
C
out

p2
= R
1
C
out

The propagation delay of the first stage TSPC flip
t
p_L1SPC
=
0.69(:
p2
2

(b) E-TSPC
First stage and equivalent RC model of (a) TSPC (b) E-TSPC flip
The charging and discharging time constants of the first stage of the TSPC flip
calculated using the RC ladder method, as follows

gd3
+C
db2
+2C
gd2
+ C
]o

)C
out
+ R
1
C
x

+C
p+

s the total depletion capacitance between the series PMOS transistors
capacitance. The propagation delay of the first stage TSPC flip-flops
+:
n1
)

The charging and discharging time constants of the first stage E-TSPC flip-

of the first stage TSPC flip-flop is given by
2
+:
n2
)

Page 25

TSPC
TSPC flip-flops
of the TSPC flip-flop are manually
(4.2)
(4.3)
(4.4)
(4.5)
s the total depletion capacitance between the series PMOS transistors and is the fan-out
(4.6)
-flop are given by
(4.7)
(4.8)
(4.9)


The output load capacitance of E-TSPC stage is lower than that of TSPC due to the reduced fan-out.
The charging time constant of E-TSPC is smaller than TSPC from (4.4) and (4.8), the propagation
delay of TSPC stage is higher than that of the E-TSPC stage and thus it proves TSPC flip-flop has a
lower operating frequency compared to that of the E-TSPC flip flop. If speed is the critical
parameter in the Architecture, E-TSPC logic circuits are chosen over other dynamic logic circuits.
However, it suffers from static power dissipation which is discussed in the next section.
4.2.4 Power consumption analysis of TSPC and E-TSPC flip-flops
In digital circuits, the power consumption is divided in to three parts namely; switching power,
short-circuit power and leakage power. The total power consumption of a digital circuit is given by

P
ug
= P
swtchng
+P
shot
circuit
+P
Icukugc

= o
01
C
L
I
dd
2
cIk
+(I
sc
+ I
Icuk
)I
dd
(4.10)
The first term represents the switching power consumption, where C
L
is the load capacitance; f
clk
is
the clock frequency and
01
is the node transition activity factor, the average number of
transitions in one clock period. The second term is due to conduction of current directly from the
supply to ground when PMOS and NMOS are active simultaneously. The third term is due to the
leakage current, which arises from the substrate injection and sub-threshold effects. Circuit
diagram, waveform, schematic and layout of TSPC and E-TSPC flip-flop are as shown in Fig. 4.8
and Fig. 4.9 respectively. The load capacitance at each output node of TSPC flip-flop in divide-by-2
mode is given by

C
S1
= C
dbM3
+2C
gdM3
+C
dbM2
+ 2C
gdM2
+C
gM5
(4.11)
C
S2
= C
dbM4
+2C
gdM4
+C
dbM5
+ 2C
gdM5
+C
gM7
+C
gM9
(4.12)
C
S3
= C
dbM7
+2C
gdM7
+C
dbM8
+ 2C
gdM8
+C
gM1
+C
gM3
(4.13)



(a) TSPC (b) E-TSPC
Fig. 4.8 (a) Divide-by-2 circuit (a) TSPC (b) E-TSPC

Fig. 4.8 (b) Waveform of TSPC flip-flop
Table.4.1 Delay and power consumption of TSPC flip-flop
Parameters With parasitics Without parasitic
Operating voltage (V) 1.8 1.8
Max. operating freq.(MHz) 500 500
Output frequency (MHz) 250 250
tp
HL
(ps) 37 27
tp
LH
(ps) 88 73
tp (ps) 62.5 50
Power consumption (uW) 64.71 45.93



Fig. 4.8 (c) Schematic diagram of TSPC flip-flop

Fig. 4.8 (d) Layout of TSPC flip-flop


Table.4.2 Circuit inventory of TSPC flip-flop
LIBRARY CELL VIEW TOTAL
analogLib Pcapacitor symbol 142
analogLib Presistor symbol 47
gpdk180 Nmos ivpcell 5
gpdk180 Pmos ivpcell 4

Fig. 4.9 (a) Schematic of E-TSPC flip-flop

Fig. 4.9 (b) Waveform of E-TSPC flip-flop


Table.4.3 Delay and power consumption of E-TSPC flip-flop
Parameters With parasitics Without parasitics
Max. operating freq.(MHz) 500 500
Output frequency (MHz) 250 250
tp
HL
(ps) 50 40
tp
LH
(ps) 20 15
tp (ps) 35 27.5
Power consumption (mW) 1.175 1.173

Fig. 4.9 (c) Layout of E-TSPC flip-flop


Table.4.4 Circuit inventory of E-TSPC flip-flop

The load capacitance at each output node of E-TSPC flip-flop in divide-by-2mode is given by
C
S1
= C
dbM1
+2C
gdM1
+C
dbM2
+ 2C
gdM2
+C
gM3
(4.14)
C
S2
= C
dbM4
+2C
gdM4
+C
dbM3
+ 2C
gdM3
+C
gM6
(4.15)
C
S3
= C
dbM5
+2C
gdM5
+C
dbM6
+ 2C
gdM6
+C
gM1
(4.16)
From the above equations it is clear that the capacitance at the each output node of the TSPC circuit
is higher than that of the E-TSPC circuit. Since the switching power is linearly related to the load
capacitance, TSPC circuits cause more switching power than E TSPC circuits. However, the
switching power can be reduced by optimization techniques such as reducing the number of
switching stages and the width of the transistors.
In TSPC circuits, one of the transistors in each stage is always off, hence there is no short-circuit
power consumption. The TSPC short-circuit power is smaller than the E-TSPC short circuit power.
The timing diagram of Fig. 4.10 illustrates the operation of a divide-by-2 E-TSPC circuit. The
shaded part shows the duration where the short-circuit current exists in the E-TSPC divide by-2
circuit. To analyze E-TSPC short-circuit, a single stage of an E-TSPC circuit is simulated with
PMOS and NMOS transistors active and the PMOS transistor width is increased for a constant
NMOS transistor width in 180nm technology.
The short circuit power consumption for different ratios of PMOS to NMOS transistor widths is
plotted in Fig. 4.11 for the values which are tabulated in Table 4.5. As the PMOS to NMOS width
ratio increases, both the short-circuit power and the output voltage increases. As a result power
consumption also increases since it is directly proportional to input voltage.


Fig. 4.10
Even though the propagation
short-circuit power and considerable amount of switching power makes the
suitable of low power applications compared to TSPC below 5GHz operation.
of TSPC and E-TSPC flip flop is shown in Fig. 4.12. Based on this analysis,
for the Architecture of low power divider.

Fig. 4.11 Short circuit power in a single stage of E
Fig. 4.10 Divide-by-2 operation of an E-TSPC circuit
though the propagation delay of E-TSPC logic is lower than that of TSPC logic, its
considerable amount of switching power makes the
applications compared to TSPC below 5GHz operation.
TSPC flip flop is shown in Fig. 4.12. Based on this analysis,
low power divider.
Short circuit power in a single stage of E-TSPC circuit

Page 32

TSPC circuit
TSPC logic is lower than that of TSPC logic, its large
considerable amount of switching power makes the E-TSPC logic less
applications compared to TSPC below 5GHz operation. Power consumption
TSPC flip flop is shown in Fig. 4.12. Based on this analysis, TSPC logic is chosen

TSPC circuit


Table.4.5 Short circuit power in a single stage E-TSPC

NMOS
width (um)
PMOS width
(um)
Amplitude
(V)

Current
(mA)
Power consumption
(mW)
1
1

2

3

4

5

1.8
0.234

0.448

0.587

0.605

0.610
0.421

0.807

1.057

1.089

1.090
2
2

4

6

8

10

1.8
0.459

0.854

1.132

1.160

1.170
0.827

1.538

2.037

2.088

2.106
3
3

6

9

12

15

1.8
0.684

1.321

1.678

1.724

1.753
1.232

2.370

3.020

3.103

3.155


Fig. 4.12 Power consumption of TSPC and E
4.2.5 Conventional E-
The control logic signal MC changes the operation between divide
MC =1, the 2/3 prescaler operates in the divide
participate in the operation. If
PMOS transistor M
2
is always
nodes S1, S2 and S3 remain at
in DFF1 during the divide-by
power in the first stage of the DFF1 and improper device sizing can still
activities in the DFF1 during the divide
layout of E-TSPC divide-by-2 and divid

Power consumption of TSPC and E-TSPC flip
-TSPC 2/3 prescaler
changes the operation between divide-by-2 and
=1, the 2/3 prescaler operates in the divide-by-3 mode where the two DFFs actively
participate in the operation. If MC =0, the 2/3 prescaler operates in the divide
is always turned-on suppressing the switching activities in DFF1 such that the
S3 remain at logic 1, 0 and 1 respectively. Thus the switching power is saved
by-2 operation. However, there always exists very high
power in the first stage of the DFF1 and improper device sizing can still
activities in the DFF1 during the divide-by-2 operation. Circuit diagram, waveform, schematic and
2 and divide-by-3 are as shown in Fig. 4.13 and Fig. 4
Fig. 4.13 (a) E-TSPC 2/3 prescaler
Page 34

TSPC flip-flop
2 and divide-by-3 modes. If
where the two DFFs actively
prescaler operates in the divide-by-2 mode, where
on suppressing the switching activities in DFF1 such that the
logic 1, 0 and 1 respectively. Thus the switching power is saved
2 operation. However, there always exists very high short-circuit
power in the first stage of the DFF1 and improper device sizing can still result in switching
Circuit diagram, waveform, schematic and
and Fig. 4.14 respectively.



Fig. 4.13 (b) Schematic diagram of E-TSPC divide-by-2 prescaler

Fig. 4.13 (c) Waveform of E-TSPC divide-by-2 prescaler


Table.4.6 Delay and power consumption of E-TSPC divide-by-2 prescaler
Max. operating freq.(GHz) 2.5 2.5
Output frequency (GHz) 1.25 1.25
tp
HL
(ps) 31 27
tp
LH
(ps) 72 60
tp (ps) 51.5 43.5

Fig. 4.13 (d) Layout of E-TSPC divide-by-2 prescaler

Table.4.7 Circuit inventory of E-TSPC 2/3 prescaler in divide-by-2 mode

gpdk180 nmos ivpcell 7
gpdk180 pmos ivpcell 9



Fig. 4.14 (a) Schematic diagram of E-TSPC divide-by-3 prescaler

Fig. 4.14 (b) Waveforms of E-TSPC divide-by-3 prescaler

Table.4.8 Delay and power consumption of E-TSPC divide-by-3 prescaler
tp
HL
(ps) 32 28
tp
LH
(ps) 78 66
tp (ps) 55 47


Fig. 4.14 (c) Layout of E-TSPC divide-by-3 prescaler

Table.4.9 Circuit inventory of E-TSPC 2/3 prescaler in divide-by-3 mode

4.3 Conventional synchronous TSPC 2/3 prescaler
The conventional TSPC 2/3 prescaler consists of two D flip-flops, an OR gate and an AND gate.
Due to the large load on DFF2 and difficulty to embed the OR and AND gates into the DFF which
introduces additional delay limits the speed of conventional 2/3 prescaler and also causes
substantial power dissipation. Circuit diagram, schematic, waveform and layout of Conventional
TSPC divide-by-2 and divide-by-3 prescaler are as shown in Fig. 4.15 and Fig. 4.16 respectively.
The total load capacitance at the output node Q
b
of the conventional 2/3 prescaler is given by
C
L
= C
dbM30
+C
dbM31
+2(C
gdM30
+C
gdM31
) +C
gM3
+C
gM1

+C
gM19
+C
gM20
(4.17)



Fig. 4.15 (a) Conventional TSPC 2/3 prescaler and its equivalent gate level schematic
Addition of an OR gate and an AND gate in the critical path introduces the additional delay and
limits the maximum operating speed of the circuit. The propagation delay of the TSPC 2/3 prescaler
is equal to the sum of propagation delay of DFF1, DFF2and logic gates, where the propagation
delay of each DFF is equal to the sum of delay of the each stage.
The total propagation delay is given by
t
p_1SPC
= t
p_PP1
+t
p_PP2
+t
p_0R
+t
p_AN
(4.18)
The propagation delay equations shows that the maximum operating frequency of the conventional
2/3 prescaler is limited due to the logic OR and logic AND gates. The conventional TSPC 2/3
prescaler has 12 stages and each stage has a switching output node. The switching power with 12
switching nodes is given by
P
swtchng
=
cIk
12
=1
C
L
I
dd
2
(4.19)


Where C
L
is the capacitance of the each output node of DFF1, DFF2 and logic gates. The short circuit
power of the conventional 2/3 prescaler is almost negligible and power consumption is mainly due to
the switching power due to large capacitance at the output of each stage [7].
One of the main advantages of domino logic is that the logic gates can be embedded into the flip-
flop, which can reduce the additional propagation delay.
4.3.1 Divide-by-2 operation

Fig. 4.15 (b) Schematic of conventional TSPC 2/3 prescaler

Fig. 4.15 (c) Waveforms of Conventional TSPC 2/3 prescaler in Divide by-2 mode


Table.4.10 Delay and power consumption of Conventional TSPC 2/3 in Divide by-2 mode
tp
HL
(ps) 41 30
tp
LH
(ps) 58 34
tp (ps) 49.5 32

Fig. 4.15 (d) Layout of Conventional TSPC 2/3 prescaler in Divide by-2 mode
Table.4.11 Circuit inventory of Conventional TSPC 2/3 prescaler in divide-by-2 mode




Fig. 4.16 (a) Schematic of Conventional TSPC 2/3 prescaler in Divide by-3 mode

Fig. 4.16 (b) Waveforms of Conventional TSPC 2/3 prescaler in Divide by-3 mode



Table.4.12 Delay and power consumption of Conventional TSPC in Divide-by-3 mode
tp
HL
(ps) 45 30
tp
LH
(ps) 66 35
tp (ps) 55.5 32.5

Fig. 4.16 (c) Layout of Conventional TSPC 2/3 prescaler in Divide by-3 mode
Table.4.13 Circuit inventory of Conventional TSPC 2/3 prescaler in divide-by-3 mode


4.4 TSPC 2/3 Prescaler: Architecture-I
The conventional TSPC 2/3 prescaler consumes large power and has low operating frequency due
to its large load capacitance. An improved speed and low power 2/3 prescaler consists of two D
flip-flops and two NOR gates embedded into the flip-flops as shown in Fig. 4.17. Circuit diagram,
schematic, waveform and layout of Architecture-I divide-by-2 and divide-by-3 prescaler are as
shown in Fig. 4.18 and Fig. 4.29 respectively.

Fig. 4.17 Architecture-I TSPC 2/3 prescaler circuit and equivalent gate level schematic

The first NOR gate is embedded into the third stage of DFF1 using a single NMOS transistor M
10
,
whose drain is connected to node S3 of DFF1 and the other NOR gate is embedded into the first
stage of DFF2. By doing so, an extra inverter driven by node S3 of DFF1 and additional stages
introduced by the logic gates between DFF1 and DFF2 of the conventional TSPC 2/3 prescaler is
eliminated, reducing the number of switching nodes to 7 in the improved architecture-I prescaler.
The load capacitance of the conventional TSPC 2/3 prescaler is given by

C
L_uch-I
= C
dbM19
+C
dbM20
+2(C
gdM19
+C
gdM20
) +C
gM15
+C
gM11
(4.20)


When MC=1, transistor M
10
turns-on and node S3 switches to logic 0 irrespective of the data at
node S2. The second NOR gate output is always equal to the inverted output of DFF2 as shown in
Fig. 4.19 (a), which is equivalent to simple DFF with its complimentary output connected to the
input as shown in Fig. 4.7 (a). Thus the prescaler act as divide-by-2 when MC=1. Here, even
though the output of DFF2 is connected in feedback to the input of DFF1, the switching data at
node S1 and S2 is blocked by the transistor M
10
to reach to the node S3. Thus the switching power
at the node S3 is always zero.

Fig. 4.18 (a) Divide-by-2 operation of 2/3 prescaler

Fig. 4.18 (b) Schematic of Architecture-I 2/3 prescaler in Divide-by-2 mode


Fig. 4.18 (c) Waveform of Architecture-I 2/3 prescaler in divide-by-2 mode
Table.4.14 Delay and power consumption of Architecture-I 2/3 prescaler in divide-by-2 mode
tp
HL
(ps) 49 48
tp
LH
(ps) 69 69
tp (ps) 59 58.5

Fig. 4.18 (d) layout of Architecture-I 2/3 prescaler in Divide-by-2 mode


Table.4.15 Circuit inventory of Architecture-I 2/3 prescaler in divide-by-2 mode

However, there exists switching power in the first two stages of the DFF at nodes S1 and S2 due to
the feedback action of the DFF2 output which switches continuously. The total power of the
prescaler in divide-by-2 mode of operation is equal to the sum of switching power of DFF2 and the
switching power of first two stages of DFF1which is less than the conventional 2/3 prescaler.
When MC=0, transistor M
10
turns-off and the inverted data at node S2 is passed to the node S3.
The second NOR gate output is always equal to the inverted output of DFF2. Fig. 4.20 shows the
circuit of the architecture-I 2/3 prescaler unit in divide-by-3 mode of operation. The combination of
inverter and NOR gate is equivalent to logic AND gate with the other input inverted as shown in
Fig. 4.20. Thus the prescaler act as divide-by-3 when MC=0. There is continuous switching
activity at each node and the switching power is given by the sum of switching power of both the
DFF1 and DFF2 respectively.

Fig. 4.19 (a) Divide-by-3 operation of the Architecture-I 2/3 prescaler


Fig. 4.19 (b) Schematic of Architecture-I 2/3 prescaler in Divide-by-3 mode

Fig. 4.19 (c) Waveforms of Architecture-I 2/3 prescaler in Divide-by-3 mode
Table.4.16 Delay and power consumption of Architecture-I 2/3 prescaler in divide-by-3 mode
tp
HL
(ps) 34 28
tp
LH
(ps) 45 32
tp (ps) 39.5 30


Fig. 4.19 (d) Layout of Divide-by-3 operation of Architecture-I 2/3 prescaler
Table.4.17 Circuit inventory of Architecture-I 2/3 prescaler in divide-by-3 mode

4.4.3 Propagation delay of TSPC 2/3 prescaler: Architecture-I
The propagation delay of the architecture-I 2/3 prescaler is calculated using the RC delay model
method which is used to calculate the propagation delay of the conventional 2/3 prescaler as
discussed in section 4.2. However, in divide-by-2 mode of operation, since the node S3 always
remains at logic 0 and blocks the data from DFF1 to propagate to the DFF2. The total propagation
delay of the architecture 2/3 prescaler individe-by-2 mode of operation is equal to the propagation
delay of DFF2 which is given by
t
p
diidc-bj-2
= t
p_PP2
(4.21)


The propagation delay of the remaining stages of the DFF2 is similar to the propagation delay of
the DFF2 in conventional 2/3 prescaler. In divide
DFF2 are active, the propagation delay is equal to the sum of propagation delay of embedded NOR
gate DFF1 and DFF2 respectively, which is given by

t
p
diidc
-b-3
= t
p_

Since the NOR gates are embedded in to the flip
is reduced by delay equal to 7 stages as proved by the RC delay model.
in the Architecture-I prescaler is reduced to 7, the

P
swtchng-uch-I
=

Where is the load capacitance at each output node of DFF1 and DFF2. The
switching power in the Architecture
circuits are designed with same transistor sizes

P
swtchng_sucd
=
In this analysis, both the conventional 2/3 prescaler and
same width of 3 um for PMOS and 1.7
output node for both circuits are assumed to be same, since al
The Architecture-I prescaler reduces the area since it uses only 23
2 and divide-by-3 compared to the conventional 2/3
output Q drives transistors M
loading on Q is reduced compared to conventional prescaler.
conventional TSPC 2/3 prescaler can operat
Architecture-I 2/3 prescaler has

the DFF2 in conventional 2/3 prescaler. In divide-by-3 mode of operation, si
gate DFF1 and DFF2 respectively, which is given by
_PP1
+ t
p_PP2

NOR gates are embedded in to the flip-flop, the propagation delay of entire
is reduced by delay equal to 7 stages as proved by the RC delay model. Since
I prescaler is reduced to 7, the switching power is given by
=
cIk
7
]=1
C
L
I
dd
2

is the load capacitance at each output node of DFF1 and DFF2. The
Architecture-I compared to that of the conventional 2/3 prescaler when both
ed with same transistor sizes is given by

cIk
12
=1
C
L
I
dd
2
-
cIk
7
]=1
C
L
I
dd
2

In this analysis, both the conventional 2/3 prescaler and Architecture-I prescaler are simulated
ame width of 3 um for PMOS and 1.7 um for NMOS transistors. The node capacitances at each
output node for both circuits are assumed to be same, since all the devices has same aspect ratio.
I prescaler reduces the area since it uses only 23 transistors to perform divide
3 compared to the conventional 2/3 which uses as many as 32 transistors. The
tors M
11
and M
14
of DFF2 and Q
b
drives transistors M
compared to conventional prescaler. The simulation results show that the
conventional TSPC 2/3 prescaler can operate up to maximum frequency of 2.5
I 2/3 prescaler has maximum operating frequency of 4.5 GHz
Page 50
3 mode of operation, since both DFF1 and
(4.22)
flop, the propagation delay of entire 2/3 prescaler
Since the number of stages
is given by
(4.23)
is the load capacitance at each output node of DFF1 and DFF2. The reduction of the
conventional 2/3 prescaler when both
(4.24)
I prescaler are simulated using
um for NMOS transistors. The node capacitances at each
devices has same aspect ratio.
transistors to perform divide-by-
which uses as many as 32 transistors. The
drives transistors M
1
and M
3
such that
The simulation results show that the
e up to maximum frequency of 2.5 GHz. The
.5 GHz.


4.4.4 Short-circuit power of the Architecture-I 2/3 prescaler
The short-circuit power in TSPC is almost negligible since one of the transistors in each stage is
always off. However, this is not true when a logic gate is embedded in to the TSPC logic. During
the divide-by-2 mode when control logic signal MC =1, the transistor M
10
turns-on as shown in
Fig. 4.17 and Fig. 4.19 (a) allowing a direct path from supply to ground when transistor M
7
turns-
on. This direct path results in the high short circuit power in the third stage of DFF1. In the Fig.
4.20, it is shown that node S2 goes low for half of the input clock period during which M
7
turns-on,
creating a direct path from supply to ground since M
10
is always turned-on during thedivide-by-2
operation. The shadow lines indicate the period during which short circuit power is exhibited in the
3
rd
stage of DFF1.

Fig. 4.20 Short circuit power analysis
In divide-by-2 mode, the power consumption of the prescaler is given by the sum of switching
power in DFF1 and DFF2, short circuit power in 3
rd
stage of DFF1 and short circuit power in DFF2.
Since short circuit power is very small in TSPC circuits.
The power consumption in divide-by-2 mode is given by
P
23_uch-I
= P
swtchng_PP1_uch-I
+P
swtchng_PP2_uch-I
+
P
shot_S3_PP1_uch-I
(4.25)
Where,
P
swtchng_PP1_uch-I
=
cIk
3
=1
C
L
I
dd
2
(4.26)


P
swtchng_PP2_uch-I
=
cIk
4
=1
C
L
I
dd
2
(4.27)
Based on the short-circuit power analysis of single stage discussed in the section 4.2.4, a
simple simulation is done to analyze the power consumption of DFF1 and DFF2. The simulation
results indicate that the Architecture-I prescaler saves nearly 60% power in divide-by-3 mode and
nearly 24% power in divide-by-2 mode compared to Conventional TSPC 2/3 prescaler respectively.
In order to overcome the short circuit power problem in 3rd stage of DFF1, an improved 2/3
prescaler is analyzed which is called as Architecture-II 2/3 prescaler.
4.5 TSPC 2/3 Prescaler: Architecture-II
A further improved version of Architecture-I prescaler is as shown in the Fig. 4.21. In the
Architecture-II prescaler, an extra PMOS transistor M
1a
is connected between the power supply and
DFF1 whose input is the controlled by the logic signal MC. As discussed in the section 4.2, during
the divide-by-2 operation, one of the inputs of second NOR gate is always zero since transistor M
10

blocks the data at the input of DFF1 to propagate to the output node [8]. Here, DFF1 is not actively
participating in the divide-by-2 operation however; it contributes to the power consumption due to
the continuous switching at the nodes S1and S2 respectively. Circuit diagram, schematic, waveform
and layout of Architecture-II divide-by-2 and divide-by-3 prescaler are as shown in Fig. 4.22 and
Fig. 4.23 respectively.

Fig. 4.21 Architecture-I TSPC 2/3 prescaler circuit



When the control logic signal MC=1 during the divide-by-2 mode, the PMOS transistor M
1a
is
turned-off and DFF1 is disconnected from the power supply. Fig. 4.23 shows the simplified
schematic of the Architecture-II prescaler in the divide-by-2 mode of operation. Even though M
10
is
always turned-on, the source of M
7
is at virtual ground and short-circuit power is completely
avoided. Even if the output Q
b
switches continuously, the nodes S1, S2 and S3 always remain at
logic0 and thus the switching activities are blocked in DFF1 resulting in zero switching power.

Fig. 4.22 (a) Architecture-II TSPC 2/3 prescaler: divide-by-2 operation

The total power consumption of the Architecture-II prescaler is equal to the switching power of
DFF2 which is given by

P
23uch_II
= P
swtchng_PP2_uchII
(4.28)

P
swtchng_PP2_uchII
=
cIk
4
=1
C
L
I
dd
2
(4.29)


Fig. 4.22 (b) Schematic of Architecture-II 2/3 prescaler in Divide-by-2 mode

Fig. 4.22 (c) Waveforms of Architecture-II 2/3 prescaler in Divide-by-2 mode



Table.4.18 Delay and power consumption of Architecture-II 2/3 prescaler in divide-by-2 mode
tp
HL
(ps) 34 26
tp
LH
(ps) 45 29
tp (ps) 39.5 27.5

Fig. 4.22 (d) Layout of Architecture-II 2/3 prescaler in Divide-by-2 mode
Table.4.19 Circuit inventory of Architecture-II 2/3 prescaler in divide-by-2 mode



Fig. 4.23 (a) Schematic of Architecture-II 2/3 prescaler in Divide-by-3 mode

Fig. 4.23 (b) Waveforms of Architecture-II 2/3 prescaler in Divide-by-3 mode


Table.4.20 Delay and power consumption of Architecture-II 2/3 prescaler in divide-by-3 mode
tp
HL
(ps) 34 26
tp
LH
(ps) 45 29
tp (ps) 39.5 27.5

Fig. 4.23 (c) Layout of Architecture-II 2/3 prescaler in Divide-by-3 mode
Table.4.21 Circuit inventory of Architecture-II 2/3 prescaler in divide-by-3 mode



4.5.3 Power saving analysis in Divide-by-2 operation
The percentage of power saved by the Architecture-II prescaler in the divide-by-2 mode is ratio of
the difference in power consumed by Architecture-I and Architecture-II prescalers to the power
consumed by Architecture-I prescaler given by

P
23_%sucd
=
P
23_crch-I
-P
23_crch-II
P
23_crch-I
1uu (4.30)

Since both circuits use same flip-flop DFF2, which consumes the same power in both the circuits
during divide-by-2 and divide-by-3 modes, the power saved by the Architecture-II prescaler is
given by subtracting (4.25) from (4.28).

P
23_uch-I
P
23_uch-II =
P
swtchng-PP1_uch-I
+
P
shot-S3-PP1_uch-I
(4.31)
The flip-flops DFF1, DFF2 of Architecture-I prescaler are simulated with separate power supply to
find out the approximate relation between the power consumption of both D flip-flops during the
divide-by-2 operation. From the theoretical analysis it is found that the power consumed by the
DFF1 during divide-by-2 operation is almost twice of the power consumed by DFF2. This
assumption makes (4.31) simplified and the power consumed in thedivide-by-2 mode is rewritten as
P
swtchng-PP1_uch-I
+ P
shot-S3-PP1_uch-I

= 2(P
swtchng-PP2_uch-I
+P
shot-PP2_uch-I
) (4.32)

Thus substituting (4.32) and (4.33) in (4.30), the amount of power saved by the Architecture-II 2/3
prescaler is 60% in divide-by-2 mode and 45% in divide-by-3 mode compared to Conventional
TSPC 2/3 prescaler. Thus the power consumed in the divide-by-2 mode by the Architecture-I
prescaler is rewritten as
P
23_uch-I
= S(P
swtchng-PP2_uch-I
+ P
shot-PP2_uch-I
) (4.33)



4.6 Analysis of TSPC 32/33 (N/N+1) Prescaler
To verify the advantages of ultra-low power prescaler of Architecture-II, a divide 32/33 dual
modulus unit [9] is simulated with the 2/3 prescaler of Architecture-II as shown in Fig. 4.24. In this
32/33 prescaler, the 2/3 prescaler unit is followed by four stages of the toggled TSPC divide-by-2
units. Schematic, waveform and layout of TSPC 32/33 prescaler are as shown in Fig. 4.25 and Fig.
4.26 respectively.

Fig. 4.24 TSPC 32/33 prescaler using Architecture-II 2/3 prescaler
When the control signal MOD is 1, the output of NOR2 always remains at logic 0 and forces the
output of NAND2 to logic 1 irrespective of data on Qb1. Since MC is always equal to logic 1,
the Architecture-II prescaler remains in divide-by-2. Thus the 32/33 prescaler acts as divide-by-32
circuit. Since control logic signal MC is logically high, DFF1 in the Architecture-II 2/3 prescaler is
completely turned-off for the entire 32 input clock cycles. The 32/33 prescaler consists of both the
synchronous (Architecture-II prescaler) and asynchronous (toggle divide-by-2) circuits and thus the
power and speed is traded-off as discussed in the Architecture of digital counters earlier.


Fig. 4.25 (a) Schematic of TSPC 32/33 prescaler in divide-by-32 mode

Fig. 4.25 (b) Waveforms of TSPC 32/33 prescaler in Divide-by-32 mode
Table.4.22 Delay and power consumption of TSPC 32/33 prescaler in Divide-by-32 mode

tp
HL
(ps) 160 170
tp
LH
(ps) 110 120
tp (ps) 135 145


Fig. 4.25 (c) Layout of TSPC 32/33 prescaler in Divide-by-32 mode
Table.4.23 Circuit inventory of TSPC 32/33 prescaler in divide-by-32 mode
If the synchronous 2/3 prescaler is denoted asHH+1 and the four asynchronous dividers whose
division ratio equal to 16 by AD, the division ratio in this mode (MOD=1) is given by

32
= (A H0
) H+ H0
(H+1) = S2 (4.34)
The total power consumed by the 32/33 prescaler using Architecture-I 2/3 prescaler during divide-
by-32 is equal to the sum of switching and short circuit power of the DFF1, DFF2 over 32 clock
cycles, power consumed by four asynchronous divide-by-2 circuits, and the power consumed by the
logic gates.
P
32_uch_I
= P
swtchng_PP2
+ P
swtchng_PP1
+
P
shot_s3_PP1
+ P
d_b_16
+ P
Iogc gutcs
(4.35)



The power consumed by the four asynchronous divide
P
d_b_16
=
Here,
p
is the frequency of the output signal from the 2/3 prescaler which can
of the input clock signal and
by-2 circuit. Each of the asynchronous divider
preceding divide-by-2 circuit. Similarly,
divide-by-32 operation using the
circuit power of DFF2 over 32 clock cycles (DFF1 turned
asynchronous dividers and logic gates. The power saved by the 32/33 prescaler during
mode using Architecture-II prescaler is equal to the amount of power
Architecture-I prescaler.
P
32_sucd
= P
swtch
The dual-modulus 32/33 prescaler operates as divide
combination of logic NOR and NAND gates, the asynchronous divide
count an extra input clock. The control signal
HC =
b4
+
b3
Fig. 4.26 (a) Schematic of TSPC 32/33

The power consumed by the four asynchronous divide-by-2 circuits is given by

]
p
C
Li
v
dd
2 4
i-1
2
i-1
+ I
sc
I
dd
4
-1

is the frequency of the output signal from the 2/3 prescaler which can
is the total short-circuit current of the each asynchronous divide
2 circuit. Each of the asynchronous divider toggles at half the operating frequency of the
2 circuit. Similarly, the power consumed by the 32/33 prescaler during the
the Architecture-II prescaler is equal to the sum of switching and short
DFF2 over 32 clock cycles (DFF1 turned-off) and the power consumed by the 4
asynchronous dividers and logic gates. The power saved by the 32/33 prescaler during
II prescaler is equal to the amount of power consumed
hng_PP1
+ P
shot_S3_PP1

33 operation
modulus 32/33 prescaler operates as divide-by-33 when MOD
combination of logic NOR and NAND gates, the asynchronous divide-by
count an extra input clock. The control signal MC is given by
+
b2
+
b1
+ H0
Fig. 4.26 (a) Schematic of TSPC 32/33 prescaler in Divide-by
Page 62
2 circuits is given by
(4.36)
is the frequency of the output signal from the 2/3 prescaler which can be half or one-third
circuit current of the each asynchronous divide-
toggles at half the operating frequency of the
the power consumed by the 32/33 prescaler during the
II prescaler is equal to the sum of switching and short
off) and the power consumed by the 4
asynchronous dividers and logic gates. The power saved by the 32/33 prescaler during divide-by-32
consumed by DFF1 of the
(4.37)
MOD=0. By using the
by-16 counter is made to
(4.38)

by-33 mode




tp
HL
(ps) 150 140
tp
LH
(ps) 130 110
tp (ps) 140 125


In the initial state, the Architecture-II 2/3 prescaler will be in divide-by-2 mode (MC=1) and the
asynchronous divide-by-16 starts counting the output pulses of 2/3 prescaler from 0000 to
1111. When the asynchronous counter value reaches 1110, the logic signal MC goes low
(MC=0) and the Architecture-II 2/3 prescaler operates in divide-by-3 mode, where the
asynchronous counter counts an extra input clock pulse. During this operation, the 2/3 prescaler
operates in divide-by-2 mode for 30 input clock cycles and for the remaining 3 input clock cycles it
operates in divide-by-3 mode. The division of the 32/33 prescaler in this mode is given by

32
= (A H0
) H+ H0
(H+1) = S2 (4.39)
where AD=16, MOD=0 and M=2. The total power consumed by the 32/33 prescaler using
Architecture-I prescaler during the divide-by-33 operation is equal to the sum of switching power of
the flip-flops DFF1, DFF2, short circuit power in the 3
rd
stage of DFF1 over 30 clock cycles, power
consumed by four asynchronous divide-by-2 circuits and the power consumed by the digital gates.
P
32
crch_1
= P
swtchng_PP2
+ P
swtchng_PP1
+
P
shot_s3_PP1
+P
d_b_16
+ P
Iogc gutcs
(4.40)


Similarly, the power consumed by the 32/33 prescaler using Architecture-II prescaler during the
divide-by-33 operation is equal to the sum of the switching of DFF2, switching power of DFF1
over 3 clock cycles; power consumed by the 4 asynchronous dividers and digital logic gates.
P
32_csgn1
=
3
33
(P
swtchng_PP1
) + P
swtchng_PP2
+ P
d_b_16
+ P
Logc gutcs

(4.41)
Since power consumed by DFF2, 4 asynchronous dividers and the logic gates are same in both
cases, the total amount of power saved by the 32/33 prescaler during the divide-by-33 using
Architecture-II prescaler is equal to 1.4 times the power consumed during divide-by-32.
4.7 TSPC 47/48 prescaler
The 47/48 prescaler circuit as shown in Fig. 4.27 is similar to the 32/33 prescaler except for an
additional inverter which is added between the output of the NAND2 gate and the control signal
(MC) input of the 2/3 prescaler. The 47/48 prescaler consists of Architecture-II 2/3 prescaler, four
asynchronous divide-by-2 circuits and additional logic gates to control the division ratio between 47
and 48. Schematic, waveform and layout of TSPC 47/48 prescaler are as shown in Fig. 4.28 and
Fig. 4.30 respectively.

Fig. 4.27 TSPC 47/48 prescaler using Architecture-II 2/3 prescaler


When MC=0, the 2/3 prescaler of the 32/33 prescaler operates in divide-by-3 mode whereas the
2/3 prescaler in the analyzed 47/48 prescaler operates in divide-by-2 mode. Thus the inverter swaps
the operation modes of the 2/3 prescaler.
The 47/48 prescaler operates as divide-by-47 when MOD=0. By using the combination of logic
NOR and NAND gates, the asynchronous divide-by-16 counter is made to count an extra input
clock. In the initial state, the 2/3 prescaler will be in divide-by-3 mode (MC=1) and the
asynchronous divide-by-16 starts counting the output pulses of 2/3 prescaler from 0000 to
1111. When the asynchronous counter value reaches 1110, the logic signal MC goes low
(MC=0) and 2/3 prescaler operates in divide-by-2 mode, where the asynchronous counter counts
an extra input clock pulse. During this operation, the 2/3 prescaler operates in the divide-by-3 mode
for 45 input clock cycles and in the divide-2 mode for 2 input clock cycles. The division ratio of the
47/48 prescaler in this mode is given by
48
= (A H0
) (H+1) + H0
(H)
= (16 1) (2 +1) +1 2 = 47 (4.42)

Fig. 4.28 (a) Schematic of TSPC 47/48 prescaler in Divide-by-47 mode




tp
HL
(ps) 240 140
tp
LH
(ps) 140 110
tp (ps) 190 125
analogLib Pcapacitor Symbol 1566
analogLib Presistor Symbol 469
gpdk180 Nmos Ivpcell 47
gpdk180 Pmos Ivpcell 38


Fig. 4.28 (c) Layout of TSPC 47/48 prescaler in Divide
When the control signal MOD
and forces the output of NAND2 to logic 1 irrespective of data on Qb1.
to logic 1 ( =0), the 2/3 prescaler remains in
inverter and the 2/3 prescaler is equal to
prescaler operates in divide-by
and the four asynchronous dividers whose division ratio equal to 16 by
the 47/48 prescaler in this mode (
48
= (A H0
) (H
= (16 -u) (2 +1)
Fig. 4.29
Fig. 4.28 (c) Layout of TSPC 47/48 prescaler in Divide-by
48 operation
MOD is 1, the output of NOR2 in Fig.4.28 always remains
and forces the output of NAND2 to logic 1 irrespective of data on Qb1. Since
2/3 prescaler remains in divide-by-3 mode. The equivalen
inverter and the 2/3 prescaler is equal to divide-by-3 counter as shown in Fig.
by-48 mode when MOD=1. If synchronous 2/3 prescaler
and the four asynchronous dividers whose division ratio equal to 16 by AD
the 47/48 prescaler in this mode (MOD=1) is given by
(H+1) + H0
(H)
) +u 2 = 48
Fig. 4.29 Divide-by-48 mode of operation
Page 68

by-47 mode
always remains at logic 0
Since MC is always equal
3 mode. The equivalent circuit of
3 counter as shown in Fig. 4.29. Thus the 47/48
If synchronous 2/3 prescaler denoted as
AD, the division ratio of
(4.43)



Fig. 4.30 (a) Schematic of TSPC 47/48 prescaler in Divide-by-48 mode


tp
HL
(ps) 230 140
tp
LH
(ps) 130 110
tp (ps) 180 125



4.8 Summary
A detailed analysis of digital dividers is performed. Of all the possible digital dividers, dynamic
logic dividers are chosen because of their low power and single phase clock. The propagation speed
and power consumption analysis between TSPC and E-TSPC is performed and based on this
analysis, an ultra-low power Architecture-I and Architecture-II TSPC 2/3 prescalers are analyzed.
The 32/33 and 47/48 prescaler is the critical block in the design of fully programmable divider
discussed in the next chapter.



Chapter 5
Ultra Low Power Fully Programmable Dividers
5.1 Introduction
Most of integer-N frequency synthesizers are implemented using the pulse-swallow divider
topology. The IEEE 802.15.4 and Zigbee standard has 16 channels, spaced 5 MHz apart from 2405
MHz to 2480 MHz. If direct conversion is used in both the TX and RX, then the 16 channel
selection frequencies would be from 2405 MHz to 2480 MHz in steps of 5 MHz. If a low IF
architecture is used for the RX, then the channel selection frequencies could be different for the
both TX and RX. In order to have more flexibility to accommodate channel selections for both kind
of architecture, the resolution of the divider and reference frequency chosen is 1 MHz which gives a
resolution of 1 MHz to the channel selection frequency. For example, if the IF frequency is chosen
to be 2 MHz, the divider is programmed to have the channel frequencies equal to 2403,
2408.2478 MHz or 2407, 2412.2482 MHz
5.2 Fully Programmable Divider: Architecture-I
For PLL synthesizers operating in the 2.4 GHz ISM band [10] with a resolution of 1MHz and
division ratios of 2400-2484 can be achieved with a 32/33 prescaler, a 7 bit P-counter and a 5 bit S-
counter. Fig. 5.1 shows the Architecture-I fully programmable divider with a division ratio from
2400 to 2484 in steps of 1. In this Architecture, only bits P1, P2 and P3 of the P-counter are used
programming and the bits P4, P5, P6 and P7 are fixed at 1, 0, 0 and 1 respectively to have P-
values between 74-77. Here all the bits of S-counter are used for programming. The P and S
counters programmable value for the division ratios between 2400-2484 is shown in Table.5.1.
Table.5.1 Programmable values of the programmable counters
Frequency division
Ratio
Prescaler (N/N+1)
Programmable
counter
Swallow
counter
2400-2431 N=32 P=75 S=0-31
2432-2463 N=32 P=76 S=0-31
2464-2484 N=32 P=77 S=0-20



Fig. 5.1 Fully programmable divider: Architecture-I
5.2.1 Prescaler (N/N+1)
A 32/33 prescaler is used in this Architecture-I of the fully programmable divider. To provide a 1
MHz resolution, the maximum programmable value of the swallow S-counter should be less than
the value of the prescaler (S<N) and the value of S-counter value should be always less than P-
counter value (S<P) to satisfy the conditions of pulse-swallow topology. So, a 64/65, 128/129
prescaler cannot be used for the implementation of 1 MHz resolution divider with division ratio
between 2400 and 2484. A 16/17 prescaler can be used, but this will increase the complexity of the
programmable P-counter and the input frequency at which the two counters operate. If a 32/33
prescaler, which is briefly discussed in the chapter 4 is used, the maximum programmable value of
swallow S-counter is equal to 31 (S=N-1).
5.2.2 Programmable P-counter
The 32/33 prescaler scales the input 2.4 GHz signal by a value of 32 or 33 such that the P and S
counters will be working in the frequency range of 72 - 78 MHz in order to obtain the 1 MHz
frequency output. The design requirements are as follows:
Operate at frequencies of up to several 100 MHz with low power consumption.
Able to program the desired P values from 74 to 77.
To generate full-swing output, which is fed to the phase frequency detector block.


Fig. 5.2 7-bit programmable P-counter

The programmable P-counter used in the Architecture of the fully programmable divider is a 7-bit
asynchronous down counter as shown in Fig. 5.2. The P-counter is designed with 7 reloadable
TSPC D flip-flops (DFF) and an end-of-count (EOC) detector which has reload circuit in it. Since
the counter is asynchronous and based on the ring topology, the output of the first DFF is fed as
clock to the input of next flip-flop. In the initial state, all the reloadable FFs are loaded by the
programmable pins P1-P7. As the counter is triggered by the output of the prescaler, the P-counter
starts down counting till the state 0000000 is reached. Once this state is detected by the EOC
logic circuit, the load (LD) signal goes high to reset all loadable FFs to the initial state.



5.2.2.1 Operation of EOC logic
The EOC logic circuit is used to detect when the P-counter reaches the state
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
=0000000, and preset the reloadable FFs to the initial state so that P-counter
starts down counting again from the loaded value to the final state. The EOC logic circuit is built
with a 2-input NOR, two 3-input NAND and an embedded NOR DFF as shown in Fig. 5.3 (a) and
the Fig. 5.3(b) shows the equivalent transistor level schematic of the embedded NOR-DFF. Here all
the complementary outputs of the reloadable FFs are given to EOC logic circuit to detect the state
Q
b1
Q
b2
Q
b3
Q
b4
Q
b5
Q
b6
Q
b7
=1111111 to simplify the EOC circuit. Fig. 4.4 shows the timing diagram
of the EOC logic circuit.

Fig. 5.3 a) EOC logic circuit for P-counter b) NOR embedded TSPC DFF
When the P-counter reaches the penultimate state (Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
=0000001), the following
events occur during the next rising edge of the clock:
The counter enters the final state 0000000 after a CLK-to-Q delay TCLK-Q where the
input to the EOC is 1111111.
The delay of EOC logic circuit is TEOC1 after which the EOC logic circuit output goes high
(LD=1) to reload the FFs with initial programmable values. In this case P=75 or
1001011.
There is a reloading delay time of TR for the P-counter to reload the initial state.


Fig. 5.4 Timing diagram of 7-bit P-counter

The output of EOC logic circuit goes low only after a delay of TEOC2 after the P-counter is
loaded with the preset value.
There exists a time delay of TEN where the LD goes low and the counter starts counting
from the loaded value. From the above timing diagram, it is found that all the delays must be
less than a single clock period for the counter to function correctly. The relation between all
the delays and clock period is given by
I
CLK
> I
CLK-
+ I
L0C1
+ I
L0C2
+ I
R
+ I
LN
(5.1)
From the above delay analysis, it is found that the counter speed can be increased by reducing the
CLK-to-Q (T
CLK-Q
) delay. For the counter to function correctly, instead of detecting all zeros state,
a previous state is made to detect by the EOC logic circuit to avoid the delays introduced by the
reloadable FFs and logic gates of the EOC circuit. The logic gates introduce glitches since all the
outputs from the reloadable FFs are not arrived at the same time. To avoid all the glitches passing
to the input of reloadable FFs, a TSPC DFF is introduced between the logic gates and the
reloadable FFs. The NOR gate is embedded in to the DFF to reduce the delay. By introducing
NOR-embedded DFF, the signals A and B are latched to output LD only at the rising edge of the
clock signal. This architecture chooses to detect the state 0000010. When the state 0000010 is
reached, the signals A and B go low after a delay introduced by the logic gates which is assumed to
be less than half of the input clock cycle. However, the output of the embedded-NOR gate is latched


to output only at the next rising edge of clock after the state 0000001 is reached. This output
LD signal will initialize the P and S counters and the counting process continues. If the state
0000001 is chosen to detect, then it results in the undercounting due to the delays.
5.2.2.2 Reloadable TSPC DFF for P-Counter

Fig. 5.5(a) Reloadable DFF for P-counter

Fig. 5.5(b) Schematic of Reloadable DFF for P-counter
Fig. 5.5 shows the schematic of reloadable TSPC DFF used in the Architecture of the 7-bit P-
counter. This reloadable FF is similar to the original nine transistors TSPC DFF with reloadable
functions added to it. The reloadable FF is programmed through the input PI. The signals LD
and LDB are used to reload the programmable state of the FF.


Operation of Reloadable DFF
Once the programmable input (PI) of the each reloadable FF is loaded with a value and LD signal
goes low, the P-counter begins to count down. Under this condition, the right hand side of the
reloadable DFF as highlighted in Fig. 5.5 is deactivated and transistor M
5
is turned-off such that the
FF acts as a divide-by-2 circuit where node S3 is complimentary of the divide-by-2 output. The FF
remains in the divide-by-2 mode until the counter reaches the state 0000010. When LD=1, the
first two stages of the reloadable FF is deactivated and node S1 always remains at logic 0 since the
transistor M
5
is turned-on. Since node S1 is at logic 0, node S2 should be at logic 1. However,
node S2 is overridden by the complimentary value of node S4. Under this condition (LD=1), if the
programmable input PI=0, nodes S4 and S2 switch to logic 1 and 0 respectively. The value at
node S2 is latched to the output node Q on the next rising edge of the clock. Similarly, if PI=1, the
output Q switches to 1 on the clock rising edge. However when LD=0, the bit-cell acts as a
divide-by-2 circuit irrespective of the PI value. Table 5.2 shows the operation of the reloadable FF.

Table 5.2 Operation of the Reloadable DFF of the P-counter

Load (LD) Programmable input (PI) Output (Q)
0 0 CLK/2
0 1 CLK/2
1 0 0
1 1 1

5.2.3 Swallow S-counter
The fully programmable divider also consists of a 5-bit swallow S-counter whose Architecture
requirements are as follows:
To operate at frequencies of up to several 100 MHz with low power consumption.
To load the programmable S values from 0 to 31 in steps of one and stop the operation when
S counting is finished.
To generate a full-swing output, this is given as feedback signal to phase frequency detector
block.
The swallow S-counter used in the Architecture of the fully programmable divider is a 5-bit
asynchronous down counter as shown in Fig. 5.6. The S-counter is designed with 5 reloadable
TSPC D flip-flops and an end-of-count (EOC) detector with the reload circuit. In the initial state, all


the reloadable FFs are loaded by the programmable value set by pins S1-S5. In the S-counter all
states from 0-31 are usable and adjustable in steps of 1 to obtain a resolution of 1MHz. Once the
counter is triggered by the output of the prescaler, the S-counter starts down counting till the final
state is reached, which is detected by the EOC logic circuit and the stop (SP) signal goes high until
the P-counter finishes its counting. Since the value of P is always greater than value of S in
pulse-swallow divider, the S-counter remains idle for a period of (P S) Nclock cycles. The
EOC logic circuit for the S-counter is shown in Fig. 5.7.

Fig. 5.6 A 5-bit Swallow S-counter

Fig. 5.7 EOC logic circuit for S-counter



As discussed earlier, the signal SP goes high only when the outputs of all the reloadable DFF in the S-
counter go low and remain in the same state until the LD signal from the P-counter goes high. The state
where SP remains at logic high indicates the S-counter has finished counting. The S-counter cannot use
the EOC logic circuit of the P-counter since SP has to remain high until the P-counter reaches the state
0000010 when the LD signal goes high for one clock cycle. Moreover in the S-counter, all zero state
is detected by EOC circuit unlike in the P-counter. Since the S-counter uses all available states from 0-
31 and the EOC circuit detects the state 00000, SP signal goes high only during the next clock cycle
which results in the counting of an extra clock cycle. In order to avoid to the counting of extra clock
cycle, state Q5Q4Q3Q2=0000 is detected and the least significant bit (Q1) is neglected. The output of
the NAND2 gate switches to logic 0 as soon as the S-counter reaches the state 0000. Since the other
input of the embedded NOR gate is always 0, SP goes high during the next rising edge of the clock
cycle and the S-counter remains idle until it is triggered by LD signal from the P-counter.
5.2.3.1 Reloadable TSPC DFF for S-Counter
Fig. 5.8 shows the schematic of an improved reloadable TSPC DFF used in the Architecture of 5-bit S-
counter. This reload DFF is similar to the reloadable DFF used in the Architecture of P-counter.
However, the reloadable DFF for the S-counter needs an extra logic function SP to be incorporated.

Fig. 5.8 (a) Reloadable DFF for S-counter


Fig. 5.8 (b) schematic of Reloadable DFF for S-counter
Operation of reloadable DFF for S-counter

When SP goes high, the S-counter remains idle for a period of N (P S) clock cycles and the
reloadable DFF of the S-counter consumes some switching power. In the improved Architecture,
transistors M
6
and M
7
are added to reduce the switching activities in the reloadable DFF. When the
state 0000 is reached, SP goes high, M
6
is turned-on and M
7
is turned-off such that node S1 and
S2 remain at logic 0 for the remaining N (P S) clock cycles until LD becomes high. During
this period, since LD=0, the right hand side portion of the circuit is de-activated similar to the
reloadable DFF of the P-counter. Thus there is no switching activity at any node during the idle
state of the S-counter and switching power is saved for a period of N (P S) clock cycles. In
other conditions, the operation of the improved reloadable DFF for S-counter is similar to the
operation of the reloadable DFF in P-counter described earlier. Table 5.3 shows the operation of
reloadable DFF used in the S-counter.
Table 5.3 Operation of the Reloadable DFF of the S-counter

Stop (sp) Load (LD) Programmable input (PI) Output (Q)
1 X X 1
0 0 0 CLK/2
0 0 1 CLK/2
0 1 0 0
0 1 1 1


5.3 Simulation and Measured results of the programmable divider:
Architecture-I
The simulations of the fully programmable divider with 1MHz resolution are performed using
Cadence SPECTRE RF for a 180nm CMOS process. Here the programmability of the divider is set
to 2400 and the results indicate that the output of the fully programmable divider is 1MHz with
duty cycle less than 25%. The low duty cycle is due to the large difference between
programmability P value, prescaler N value and the S-counter S value (P>>N and P>>S). Fig. 5.9
shows the output waveform of the analyzed fully programmable divider respectively.

Fig. 5.9 (a) Schematic of fully programmable frequency divider: Architecture-I


Fig. 5.9 (b) Output waveform of fully programmable divider: Architecture I
5.4 Fully programmable divider: Architecture-II

For the IEEE 802.15.4 standard, to obtain a 1 MHz resolution for division ratios between 2400-
2484 with a 47/48 prescaler, a 6-bit P-counter and a 6-bit S-counter is required as shown in Fig.
5.10. In this Architecture-II, the P-counter is programmable from 51 to 52 (P1 and P2 are only
programmable) and the S-counter is programmable from 0 to 47 (S1 to S6) in steps of 1 to
accommodate division ratios from 2400 to 2484. The frequency division (FD) performed by the
programmable divider is given
F = N S +((N +1) (P S)) = ((N +1) P) S (5.2)

Fig. 5.10 Fully programmable divider: Architecture-II


The frequency division (FD) in (5.2) is different to the conventional division ratio NP +S
performed by pulse-swallow divider discussed in the previous sections due to the dual-modulus
47/48 prescaler. When P1=1, P2=1 and P3=0, the P-counter is loaded to a value of 51 and S-
counter is programmed from 0 to 47 to accommodate division ratio from 2400 to 2448 in steps of
1. When P1=0, P2=0 and P3=1, the P-counter is loaded to a value of 52 and S-counter is
programmed from 14 to 47 to accommodate division ratio from 2448 to 2483 in steps of 1. The P
and S counters programmable value for the division ratios between 2400-2484 is shown in Table
5.4.
Table 5.4 Programmable values of the programmable counters

Frequency Division
Ratio
Prescaler (N/N+1)
Programmable
counter (P)
Swallow
counter (S)
2400-2448 N=47
51 0-47
2449-2484 N=47
52 41-47

5.4.1 Programmable P-counter and S-counters: 6-bit version

Fig. 5.11 (a) 6-bit Swallow S-counter with EOC logic circuit


The 6 bit swallow S-counter used in the fully programmable divider is shown in Fig. 5.11 which is
similar to the S-counter shown in Fig. 5.7 except an additional reloadable DFF. Here the state
Q6Q5Q4Q3Q2=000000 is detected by the EOC logic circuit. The S-counter in this programmable
divider can be programmed from 0-47 in steps of 1 for a fixed value of the P-counter.

Fig. 5.11 (b) Schematic of 6-bit Swallow S-counter with EOC logic circuit


Fig. 5.11 (c) Layout of 6-bit Swallow S-counter

Fig. 5.12 (a) 6-bit Programmable P-counter with EOC logic circuit


Fig. 5.12 (b) schematic of 6-bit Programmable P-counter with EOC logic circuit

Fig. 5.12 (c) Layout of 6-bit Programmable P-counter


The 6-bit programmable P-counter used in the Architecture-II programmable divider is shown in
Fig. 5.12 which is similar to the P-counter shown in Fig. 5.2 with a reduced number of reloadable
DFFs. The EOC logic circuit is modified according to the Architecture of the P-counter to detect the
state Q6Q5Q4Q3Q2Q1=000010. Here, bit P6 and P5 are always at logic '1' and bit P4 at logic '0'
to have a programmable values of 51 and 52. By choosing a fixed value of 51 and 52, the swallow
S-counter is programmed in steps of one-bit to provide a division ratio from 2400 to 2484 with 1
MHz resolution.
5.5 Simulation and Measured results of the programmable divider:
Architecture-II
The Architecture-II fully programmable divider at 2.4 GHz consumes a power of 0.6mW. The
results indicate that the output of the fully programmable divider is 1MHz with duty cycle of 45%.
The divider consumes a power of 0.934mW at 1.8V power supply and Fig. 5.13 shows the
measured 1 MHz output of the Architecture-II fully programmable divider.

Fig. 5.13 (a) schematic of fully programmable frequency divider: Architecture-II


Fig. 5.13 (b) Output waveform of fully programmable divider: Architecture-II

Fig. 5.13 (c) Layout of fully programmable frequency divider: Architecture-II


5.6 Summary
In this chapter, the fully programmable divider with 1 MHz resolution is simulated using
programmable P-counter and swallow S-counter. A 47/48 TSPC dual modulus prescaler is analyzed
which improves the output signal duty cycle of the fully programmable divider. An improved
reloadable TSPC DFF for the S-counter is introduced which reduces the switching power of the
counter during the idle state when the P-counter is still active. The Architecture-II fully
programmable divider consumes a power of 0.934mW at 1.8 V power supply.



Chapter 6
Results
6.1 Simulation Results and Future Scope
A complete analysis and comparison of the performance of the TSPC 2/3 prescalers, the
conventional TSPC 2/3 and E-TSPC based prescalers is carried out. The prescalers are simulated at
1.8 V to have driving capability for fair comparison. The simulations are performed using Cadence
SPECTRE RF for a 180nm CMOS process.

Table.6.1 (a) Simulation results
Design
parameters
TSPC E-TSPC
CONVENTIONAL
TSPC
CONVENTIONAL
E-TSPC
ARCH-I ARCH-II
Process (nm)
180

180 180 180 180 180
Max. Freq
(Hz)
500M 500M 2.5G 2.5G
4.5G
(2.5G)
4.5G
(2.5G)
Power (mW)
Divide-by-2
mode
(av_extracted)
0.064 1.175 1.421 2.722
1.412
(1.094)
1.039
(0.622)
Power (mW)
Divide-by-2
mode
(Schematic)
0.045 1.173 0.978 2.655
1.213
(0.791)
0.631
(0.398)
Power (mW)
Divide-by-3
mode
(av_extracted)
- - 1.433 2.569
1.341
(0.874)
1.338
(0.874)
Power (mW)
Divide-by-3
mode
(Schematic)
- - 1.138 2.541
0.895
(0.635)
0.893
(0.635)



Table.6.1 (b) Simulation results
Architecture
parameters
TSPC
Process (nm)
180

Max. Freq (Hz)

2.5G
Power (mW)
Divide-by-32 mode
0.733
Power (mW)
Divide-by-33 mode
0.894
Power (mW)
Divide-by-47 mode
0.887
Power (mW)
Divide-by-48mode
0.877

Table.6.1 (c) Simulation results
Architecture parameters
Fully programmable divider
ARCHITECTURE-I
Fully programmable divider
ARCHITECTURE-II
Process (nm) 180 180
Max. Freq (Hz) 2.5G 2.5G
Power (mW) 1.091 0.934

It can be seen that the analysis done using Cadence tools has achieved the desired aim of reducing
the power consumption and reducing the delay satisfying the provided specifications. This project is
concentrated on the analysis of fully programmable divider with reduced power consumption. The
future scope lies in analysing the frequency synthesizer.



Conclusion
A detailed study of different kinds of divider topologies is presented. The propagation speed and
power consumption of dynamic logic dividers such as TSPC and E-TSPC circuits are investigated.
Based on this study, a new low power and improved speed TSPC 2/3 prescaler is analyzed.
Compared with the existing TSPC architectures, the Architecture-II 2/3 prescaler is capable of
operating up to 4.5 GHz and the amount of power saved by the Architecture-II 2/3 prescaler is 60%
in divide-by-2 mode and 45% in divide-by-3 mode compared to Conventional TSPC 2/3 prescaler.

A fully programmable divider with 1 MHz resolution is simulated using 32/33 prescaler, a 7-bit P-
counter and a 5-bit S-counter. This divider suffers from low output duty cycle of 25% mainly due to
the large difference between P and S values. To overcome the low duty cycle problem, a low power
TSPC 47/48 is used whose maximum operating speed is 2.5 GHz with power consumption of 0.88
mW at a supply voltage of 1.8V. A new fully programmable divider using 47/48 prescaler, a 6-bit
P-counter and a 6-bit S-counter is simulated using 180nm technology in Cadence. The divider
consumes a power of 0.934mW at 1.8V power supply and the duty cycle of the output 1 MHz
signal is close to 47%.



Bibliography
[1] Jeff Beasley, William Hudson, Transistor Level Implementation of CMOS Combinational
Logic Circuits, proceedings of the IEEE International conferene on CMOS Combinational Logic
Circuits, June 2010, pp. 01-13
[2] Richard F. Tinder, Engineering Digital Architecture, Academic Press, Second Edition 2000, pp.
79-331.
[3] Dr. Jose Pineda de Gyvez, Cadence Architecture Manual, Revision 1.0, September 2008,
Eindhoven University of Technology (TU/e)
[4] Yanping Ding and Kenneth. K. O, A 21-GHz 8-Modulus Prescaler and a 20-GHz Phase-
Locked Loop Fabricated in 130-nm CMOS Process, IEEE J. Solid-State Circuits, vol. 42, no. 6,
pp. 1240-1249, June. 2007.
[5] Jan Craninckx and Michael S. J. Steyaert, A 1.75-GHz 3-V Dual-Modulus Divide-by-128/129
Prescaler in 0.7um Process, IEEE J. Solid-State Circuits, vol. 31, no. 7, pp. 890-897, July 1996.
[6] J. Navarro Soares and W. A. M. Van Noije, A 1.6 GHz dual modulus prescaler using the
extended true-single-phase-clock CMOS circuit technique (E-TSPC), IEEE J. Solid-State Circuits,
vol. 34, no. 1, pp. 97-102, Jan. 1999.
[7] P. Larsson, High speed architecture for a programmable frequency divider and a dual modulus
prescaler, IEEE J. Solid-State Circuits, vol. 31, no. 5, pp. 744-748, May 1996.
[8] F.P.H De Miranda, J.Navarro Soares, Jr., W.A.M.Van Noije, A 4GHz dual modulus divider-
by-32/33 prescaler I 0.35um CMOS technology IEEE 17th Symp. On Circuits and Sys.
Architecture, vol. 17, pp. 94-99, Sep. 2004.
[9] M.Vamshi Krishna et.al, Architecture and Analysis of Ultra-Low Power True-Single-Phase
Clock CMOS 2/3 Prescaler, IEEE Trans. On Circuits and Systems-I: Reg. Papers, Vol.57, no.1,
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2007.

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Analysis of Ultra Low Power Fully Programmable Frequency Divider 2012-13

Dept of Electronics & Communication, SIT Tumkur Page 1

Fig. 4.26 (a) Schematic of TSPC 32/33

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