Crystal Growth and Wafer Preparation

Advantages of Si over Ge
Si has a larger bandgap (1.1 eV for Si versus 0.66 eV for Ge) Si devices can operate at a higher temperature (150oC vs 100oC) Intrinsic resistivity is higher (2.3 x 105 -cm vs 47 cm) SiO2 is more stable than GeO2 which is also water soluble Si is less costly

The processing characteristics and some material properties of silicon wafers depend on its orientation. The <111> planes have the highest density of atoms on the surface, so crystals grow most easily on these planes and oxidation occurs at a higher pace when compared to other crystal planes. Traditionally, bipolar devices are fabricated in <111> oriented crystals whereas <100> materials are preferred for MOS devices.

Defects
Any non-silicon atoms incorporated into the lattice at either a substitutional or interstitial site are considered point defects Point defects are important in the kinetics of diffusion and oxidation. Moreover, to be electrically active, dopants must occupy substitutional sites in order to introduce an energy level in the bandgap.

Dislocations are line defects. Dislocations in a lattice are dynamic defects. That is, they can diffuse under applied stress, dissociate into two or more dislocations, or combine with other dislocations. Dislocations in devices are generally undesirable, because they act as sinks for metallic impurities and alter diffusion profiles.

Defects
Two typical area or planar defects are twins and grain boundaries Twinning represents a change in the crystal orientation across a twin plane, such that a mirror image exists across that plane Grain boundaries are more disordered than twins and separate grains of single crystals in polycrystalline silicon Planar defects appear during crystal growth, and crystals having such defects are not considered usable for IC manufacture and are discarded

Precipitates of impurity or dopant atoms constitute the fourth class of defects. The solubility of dopants varies with temperature, and so if an impurity is introduced at the maximum concentration allowed by its solubility, a supersaturated condition will exist upon cooling. The crystal achieves an equilibrium state by precipitating the impurity atoms in excess of the solubility level as a second phase. Precipitates are generally undesirable as they act as sites for dislocation generation. Dislocations result from the volume mismatch between the precipitate and the lattice, inducing a strain that is relieved by the formation of dislocations.

Electronic Grade Silicon

Electronic-grade silicon (EGS), a polycrystalline material of high purity, is the starting material for the preparation of single crystal silicon. EGS is made from metallurgical-grade silicon (MGS) which in turn is made from quartzite, which is a relatively pure form of sand. MGS is purified by the following reaction: Si (solid) + 3HCl (gas) SiHCl3 (gas) + H2 (gas) + heat The boiling point of trichlorosilane (SiHCl3) is 32oC and can be readily purified using fractional distillation. EGS is formed by reacting trichlorosilane with hydrogen: 2SiHCl3 (gas) + 2H2 (gas) 2Si (solid) + 6HCl (gas)

Czochralski Crystal Growth

The Czochralski (CZ) process, which accounts for 80% to 90% of worldwide silicon consumption, consists of dipping a small single-crystal seed into molten silicon and slowly withdrawing the seed while rotating it simultaneously. The crucible is usually made of quartz or graphite with a fused silica lining. After the seed is dipped into the EGS melt, the crystal is pulled at a rate that minimizes defects and yields a constant ingot diameter.

Impurity Segregation
Impurities, both intentional and unintentional, are introduced into the silicon ingot. Intentional dopants are mixed into the melt during crystal growth, while unintentional impurities originate from the crucible, ambient, etc. All common impurities have different solubilities in the solid and in the melt. An equilibrium segregation coefficient ko can be defined to be the ratio of the equilibrium concentration of the impurity in the solid to that in the liquid at the interface, i.e. ko = Cs/Cl. Note that all the values shown in the table are below unity, implying that the impurities preferentially segregate to the melt and the melt becomes progressively enriched with these impurities as the crystal is being pulled.
Impurity ko Al 0.002 As 0.3 B 0.8 C 0.07 Cu 4x10-6 Fe 8x10-6 O 0.25 P 0.35 Sb 0.023

Impurity Distribution
The distribution of an impurity in the grown crystal can be described mathematically by the normal freezing relation:

C s = k o C o (1 X )

k o 1

X is the fraction of the melt solidified Co is the initial melt concentration Cs is the solid concentration ko is the segregation coefficient

Weight = M

Ingot

Weight = dM Dopant conc. = Cs

Consider a crystal being grown from a melt having an initial weight Mo with an initial dopant concentration Co in the melt (i.e., the weight of the dopant per 1 gram melt). At a given point of growth when a crystal of weight M has been grown, the amount of the dopant remaining in the melt (by weight) is S.

Melt
S = dopant remaining in melt

For an incremental amount of the crystal with weight dM, the corresponding reduction of the dopant (-dS) from the melt is Cs dM, where Cs is the dopant concentration in the crystal (by weight): -dS = Cs dM

The remaining weight of the melt is Mo - M, and the dopant concentration in the liquid (by weight), Cl, is given by S

Cl =

Mo M

Combining the two equations and substituting Cs Cl = ko

dM dS = ko M M S o
Given the initial weight of the dopant, Co M o , we can integrate and obtain
M dS dM =k o o M M S o

Co M o

M Solving the equation gives C s = k o C o 1 M o

k o 1

Impurity concentration profiles along the silicon ingot (axially) for different ko with Co = 1

CZ-Si crystals are grown from a silicon melt contained in a fused silica (SiO2) crucible. Fused silica reacts with hot silicon and releases oxygen into the melt giving CZ-Si an indigenous oxygen concentration of about 1018 atoms/cm3. Although the segregation coefficient of oxygen is <1, the axial distribution of oxygen is governed by the amount of oxygen in the melt. Less dissolution of the crucible material occurs as the melt volume diminishes, and less oxygen is available for incorporation.

Oxygen in Silicon
Oxygen forms a thermal donor in silicon Oxygen increases the mechanical strength of silicon Oxygen precipitates provide gettering sites for unintentional impurities

Thermal Donors
Thermal donors are formed by the polymerization of Si and O into complexes such as SiO4 in interstitial sites at 400oC to 500oC Careful quenching of the crystal annihilates these donors

Internal Gettering
Under certain annealing cycles, oxygen atoms in the bulk of the crystal can be precipitated as SiOx clusters that act as trapping sites to impurities.

This process is called internal gettering and is one of the most effective means to remove unintentional impurities from the near surface region where devices are fabricated.

Float-Zone Process
The float-zone process has some advantages over the Czochralski process for the growth of certain types of silicon crystals. The molten silicon in the float-zone apparatus is not contained in a crucible, and is thus not subject to the oxygen contamination present in CZ-Si crystals. The float-zone process is also necessary to obtain crystals with a high resistivity (>> 25 W-cm).

Characterization
Routine evaluation of ingots or boules involves measuring the resistivity, evaluating their crystal perfection, and examining their mechanical properties, such as size and mass Other tests include the measurement of carbon, oxygen, and heavy metals

Resistivity Measurement

Resistivity measurements are made on the flat ends of the crystal by the four-point probe technique. A current, I, is passed through the outer probes and the voltage, V, is measured between the inner probes. The measured resistance (V/I) is converted to resistivity (W-cm) using the relationship: = (V/I)2S

The calculated resistivity can be correlated with dopant concentration using a dopant concentration versus resisitivity chart

Wafer Preparation
Gross crystalline imperfections are detected visually and defective crystals are cut from the boule. More subtle defects such as dislocations can be disclosed by preferential chemical etching Chemical information can be acquired employing wet analytical techniques or more sophisticated solid-state and surface analytical methods Silicon, albeit brittle, is a hard material. The most suitable material for shaping and cutting silicon is industrial-grade diamond. Conversion of silicon ingots into polished wafers requires several machining, chemical, and polishing operations

Grinding

After grinding to fix the diameter, one or more flats are grounded along the length of the ingot. The largest flat, called the "major" or "primary" flat, is usually relative to a specific crystal orientation. The flat is located by x-ray diffraction techniques. The primary flat serves as a mechanical locator in automated processing equipment to position the wafer, and also serves to orient the IC device relative to the crystal. Other smaller flats are called "secondary" flats that serve to identify the orientation and conductivity type of the wafer.
The drawback of these flats is the reduction of the usable area on the wafer. For some 200 mm and 300 mm diameter wafers, only a small notch is cut from the wafer to enable lithographic alignment but no dopant type or crystal orientation information is conveyed.

Slicing determines four wafer parameters:

Surface orientation (e.g., <111> or <100>) Thickness (e.g., 0.5 0.7 mm, depending on wafer diameter) Taper, which is the wafer thickness variations from one end to another Bow, which is the surface curvature of the wafer measured from the center of the wafer to its edge

Finished Wafers

The wafer as cut varies enough in thickness to warrant an additional lapping operation that is performed under pressure using a mixture of Al2O3 and glycerine. Subsequent chemical etching removes any remaining damaged and contaminated regions. Polishing is the final step. Its purpose is to provide a smooth, specular surface on which device features can be photoengraved.

Typical Specifications for Silicon Wafers

Parameter Diameter (mm) Thickness (mm) 125 mm 150 mm 200 mm 125+1 150+1 200+1 0.7150.735 30 10 +1o 300 mm 300+1 0.7550.775 <30 <10 +1o

0.6-0.65 0.65-0.7 70 65 +1o 60 50 +1o

Bow (m) Total thickness variation (m) Surface orientation

Chapter 3
Epitaxy

Epitaxy (epi means "upon" and taxis means "ordered") is a term applied to processes used to grow a thin crystalline layer on a crystalline substrate. The seed crystal in epitaxial processes is the substrate. Unlike the Czochralski process, crystalline thin films can be grown below the melting point using techniques such as chemical vapor deposition (CVD), molecular beam epitaxy (MBE), etc. When a material is grown epitaxially on a substrate of the same material, the process is called homoepitaxy. On the contrary, if the layer and substrate are of different materials, such as AlxGa1-xAs on GaAs, the process is termed heteroepitaxy. Naturally, in heteroepitaxy, the crystal structures of the layer and the substrate must be similar in order to achieve good crystalline integrity.

Advantages of epitaxy:
(1) Doping profiles that are not attainable through other conventional means such as diffusion or ion implantation (2) Physical and chemical properties of the epitaxial layers can be made different from the bulk materials.

256Mbit DRAM (buried strap trench)

Cross section of a trench DRAM

Alpha-particles originating from packaging materials and the environment can cause electronhole pairs in the bulk of the wafer. If these charges migrate to the storage cell of a DRAM (dynamic random access memory) structure, the data stored can be wiped out. A heavily doped substrate increases the rate of electron-hole pair recombination and the DRAM is less prone to alpha-particle soft errors.

Non-Volatile Flash Memory

Writing

Erasing

Vapor Phase Epitaxy

(1) Introduction of reactant species to substrate region

(7) Removal of residual reactants and by-products from the substrate region (6) Transfer of residual reactants and by-products from substrate surface (4) Surface diffusion, site accommodation, chemical reaction, and layer deposition (5) Desorption of residual reactants and by-products

(2) Transfer of reactant species to substrate surface

(3) Adsorption of reactant species on substrate surface

The Reynolds number, Re, characterizes the type of fluid flow in a reactor: Re = Drv/ where Dr denotes the diameter of the reaction tube, v is the gas velocity,

represents the gas density, and stands for the gas viscosity. Values
of Dr and v are generally several centimeters and tens of cm/s, respectively. The carrier gas is usually H2, and using typical values for

and , the value of Re is about 100. These parameters result in gas

flow in the laminar regime. That is, the gases flow in a regular, continuous, and non-turbulent mode and in a specific direction. Accordingly, a boundary layer of reduced gas velocity will form above the susceptor and at the walls of the reaction chamber. The thickness of 1/ 2 D x the boundary layer, y, is defined as: y = r where x is the distance R e along the reactor.

Boundary Layer Formation (Horizontal Reactor)

Reactants are transported to the substrate surface and reaction by-products diffuse back into the main gas stream across the boundary layer

The fluxes of species going to and coming from the wafer surface are complex functions of the temperature, pressure, reactant, concentration, layer thickness, etc. By convention, the flux, J, is defined to be the product of D and dn/dy, and is approximated as:
J= D(n g n s ) y

where ng and ns are the gas stream and surface reactant concentrations, respectively, D is the gas-phase diffusivity, which is function of pressure and temperature, y is the boundary layer thickness, and J is the reactant flux of molecules per unit area per unit time.

In steady state, the reactant flux across the boundary layer is equal to the chemical reaction rate, ks, at the specimen surface. Therefore, ng ns = k y J = ksns and 1+ s D The quantity D/y is called the gas phase mass-transfer coefficient, hg . In the limiting case when ks >> hg, ns approaches zero, thereby implying that the overall reaction is limited by transport of reactant across the boundary layer. Conversely, if ks << hg, ns is roughly equal to ng, and the growth process will be dominated by the surface chemical reaction rate.

Growth Chemistry
The most common starting chemical is silicon tetrachloride (SiCl4) as it has a lower reactivity with respect to oxidizers in the carrier gas than the other silicon hydrogen chloride compounds, such as SiH4, SiHCl3, etc. The overall reaction is:

SiCl4 (gas) + 2H2 (gas) Si (solid) + 4HCl (gas)

Experimental results indicate the presence of many intermediate chemical species. In particular, at a reaction temperature of 1200oC, four species have been observed using FTIR.

The detailed reaction mechanism is postulated to be: SiCl4 + H2 SiHCl3 + HCl SiHCl3 + H2 SiH2Cl2 + HCl SiH2Cl2 SiCl2 + H2 SiHCl3 SiCl2 + HCl SiCl2 + H2 Si + 2HCl These reactions are reversible and under certain conditions, the overall reaction rate can become negative. That is, etching occurs in lieu of deposition

Doping

Autodoping

Zone A is due to solid-state outdiffusion from the substrate, and can be approximated by the complementary error function if the growth velocity is less than 2(D/t)1/2, where D is the dopant diffusion constant and t denotes the deposition time. When autodoping diminishes, the intentional doping predominates and the profile becomes flat.

Zone B originates from gas-phase autodoping. Because the dopant evaporating from the wafer surface is supplied from the wafer interior by solid-state diffusion, the flux of dopant from an exposed surface decreases with time.

Autodoping thus limits the minimum layer thickness that can be grown with controlled doping as well as the minimum dopant level.

Reactors

Defects

(1) Line (or edge) dislocation initially present in the substrate and extending into the epitaxial layer (2) Epitaxial stacking fault nucleated by an impurity precipitate on the substrate surface (3) Impurity precipitate caused by epitaxial process contamination (4) Growth hillock (5) Bulk stacking faults, one of which intersects the substrate surface, thereby being extended into the layer

The crystal perfection of an epitaxial layer never exceeds that of the substrate and is frequently inferior. Generally, defects can be reduced by a higher growth temperature, reduced gas pressure, lower growth rate, and cleaner substrate surface. A typical pre-epitaxy substrate cleaning process consists of a wet clean followed by a dilute HF dip and an in-situ HCl, HF, or SF6 vapor etch.

Selective Epitaxy Growth (SEG)

Selective epitaxy is a technique by which singlecrystal silicon is fabricated in a small designated area
SEG is usually accomplished at reduced partial pressure of the reactant in order to suppress the nucleation of silicon on the dielectric film, thereby resulting in nucleation only on the exposed silicon surface

Low Temperature Epitaxy (LTE)

Low-temperature epitaxy (LTE) of Si produces epitaxial growth at temperature of 550oC or less, much lower than that in conventional epitaxial processes. A low temperature is required to minimize thermal diffusion and mass-transport-controlled processes. CVD and molecular beam epitaxy (MBE) are the most popular methods. The success of these techniques relies on both an ultra-clean growth environment and a unique Si surfacecleaning process.

Molecular Beam Epitaxy (MBE)

Molecular beam epitaxy, which utilizes evaporation, is a non-CVD epitaxial growth process. MBE is therefore not complicated by boundary-layer transport effects, nor are there chemical reactions to consider. The essence of the process is evaporation of silicon and one or more dopants.

 Silicon MBE is performed under ultra-high vacuum (UHV) conditions of 10-8 to 10-10 Torr, where the mean free path of the atom is given by 5x10-3/P where P is the system pressure in Torr. At a typical pressure of 10-9 Torr, L is 5x106 cm, transport velocity is dominated by thermal energy effects Lack of intermediate reactions and diffusion effects, coupled with relatively high thermal velocities, results in film properties changing rapidly with any change of the source Typical growth temperature is between 400oC and 800oC in order to reduce out-diffusion and autodoping. Growth rates are in the range of 0.01 to 0.3 m/minute

 Despite the slow growth rate and relatively expensive instrumentation, MBE offers several advantages over conventional CVD for VLSI MBE is a low-temperature process that minimizes dopant diffusion and autodoping MBE allows more precise control of doping and layer thickness, because CVD is limited by reactant introduction and pumping time constants These advantages are not exploited extensively in silicon IC technology, but MBE has found tremendous usages in microwave and photonic devices made of III-V semiconductors

Rapid Thermal Processing (RTP)

Chemical and physical processes applied to silicon wafers are generally thermally activated. Typical silicon-based processes use batch furnaces for thermal fabrication steps, where a batch consists of 20 to 100 wafers that are simultaneously processed in a single system Processing of wafers requires tight control of contamination, process parameters, and reduced manufacturing costs, and some producers are now using single-wafer processing in some steps Using transient lamp heating or a continuous heat source (vertical furnace), a single wafer can be heated very quickly to reduce the thermal cycle and mitigate undesirable effects such as dopant diffusion

Rapid thermal processing (RTP) system that is optically heated

Conventional batch-furnace that is resistively heated

Continuous heat source, vertical furnace RTP system

 The most important feature of a rapid thermal annealing processing system consisting of tungsten-halogen lamps is its generation and quick delivery of radiant energy to the wafer (large dT/dt) in a wavelength band of 0.3 to 4.0 m Because of the optical character and wavelength of the energy transfer, the quartz walls do not absorb light efficiently, whereas the silicon wafer does The wafer is not in thermal equilibrium with the cold walls of the system, allowing for short processing times (seconds to minutes) compared to minutes to hours for conventional furnaces. The reduction in temperature-time exposure afforded by RTP is dramatic

 Rapid heating with large temperature gradients can cause wafer damage in the form of slip dislocations induced by thermal stress and heating can be laterally non-uniform across the wafer Conventional furnace processes bring with them significant problems such as particle generation from the hot walls, limited ambient control in an open system, and a large thermal mass that restricts controlled heating times to tens of minutes Requirements on contamination, process control, cost, and space are driving a paradigm shift to RTP

RTP demands on the growth of high-purity epitaxial Si include ambient purity (oxygen and water concentrations in the parts per billion range), optimization of gas flow patterns, minimum wall deposition, and vacuum compatibility. The deposition process comprises a mass-transport process with a weak temperature dependence and a sequential surfacereaction process that is exponentially dependent on wafer temperature.

Silicon-on-Insulator (SOI)
Silicon device structures have inherent problems that are associated with parasitic circuit elements arising from junction capacitance. These effects become more severe as device dimensions shrink. A viable means to circumvent the problem is to fabricate devices in small islands of silicon on an insulating substrate.

SOI Fabrication Techniques

Traditional approach is to fabricate such a structure in a silicon epitaxial thin film grown on sapphire (Al2O3) The lattice parameters of silicon and sapphire are quite similar, high quality SOS (silicon-on-sapphire) epitaxial layers can be fabricated The high cost of sapphire substrates, low yield, and lack of commercially viable applications limit the use of SOS to primarily military applications

 SIMOX (separation by implantation of oxygen) utilizes high dose blanket oxygen ion implantation to form a sandwiched buried oxide layer to isolate devices from the wafer substrate Wafer bonding utilizes Van der Waals forces to bond two polished silicon wafers, at least one of which is covered with thermal oxide, in a very clean environment at about 1000oC. Mechanical or electrochemical thinning has achieved 1 m thickness with 0.1 m deviations More recent approaches include the combination of wafer bonding and layer cleavage using hydrogen or helium ion implantation (ion-cut) as well as epitaxial growth on porous silicon and wafer bonding

Oxidation

Roles of SiO2
Mask against implant or diffusion of dopant into silicon Surface passivation Device isolation Component in MOS structures (gate oxide) Electrical isolation of multi-level metallization systems

Oxide Growth
Si (solid) + O2 (gas) SiO2 (solid) Si (solid) + 2H2O (gas) SiO2 (solid) + 2H2 (gas)
During the oxidation process, oxygen or water molecules diffuse through the surface oxide into the silicon substrate, and the Si-SiO2 interface migrates into the silicon. Thermal oxidation of silicon results in a random three-dimensional network of silicon dioxide constructed from tetrahedral cells. Since the volume expands, the external SiO2 surface is not coplanar with the original silicon surface. For the growth of an oxide of thickness d, a layer of silicon equal to a thickness of 0.44d is consumed.

Deal - Grove Model

F1 - flux of oxidizing species transported from the gas phase to the gas-oxide interface) F2 - flux across the existing oxide toward the silicon substrate) F3 - flux reacting at the SiSiO2 interface) In steady state, the three fluxes F1, F2, and F3 are equal

F1 can be approximated to be proportional to the difference in concentration of the oxidizing species in the gas phase and on the oxide surface: F1 = hG (CG - CS) where hG is the gas-phase mass-transfer coefficient, CG is the oxidant concentration in the gas phase, and CS is the oxidant concentration adjacent to the oxide surface. Substituting C = P/kT, F1 = (hG/kT)(PG PS). Henry's Law states that, in equilibrium, the concentration of a species within a solid is proportional to the partial pressure of that species in the surrounding gas. Thus, Co = HPS , where Co is the equilibrium concentration of the oxidant in the oxide on the outer surface, H is the Henry's Law constant, and PS is the partial pressure of oxidant in the gas phase adjacent to the oxide surface.

We denote the equilibrium concentration in the oxide, that is, the concentration which would be in equilibrium with the partial pressure in the bulk of the gas PG by the symbol C*, and C* = HPG C* - Co = H (PG - PS) F1 = (hG/HkT)(C* - Co) = h (C* - Co) where h = hG/HkT is the gas-phase mass-transfer coefficient in terms of concentration in the solid. Oxidation is thus a non-equilibrium process with the driving force being the deviation of concentration from equilibrium. Henry's Law is valid only in the absence of dissociation effects at the gas-oxide interface, thereby implying that the species diffusing through the oxide is molecular.

The flux of the oxidizing species across the oxide is taken to follow Fick's Law at any point d in the oxide layer. Hence, F2 = D(Co - Ci)/do where D is the diffusion coefficient, Ci is the oxidizer concentration in the oxide adjacent to the SiO2 / Si interface, and do is the oxide thickness. The chemical reaction rate at the SiO2 / Si interface is assumed to be proportional to the reactant concentration. Therefore, F3 = kSCi where kS is the rate constant.

Under steady-state conditions, F1 = F2 = F3 h(C* - Co) = D(Co - Ci)/do = kSCi Ci = DCo/(kSdo + D) Ci = C*/[1 + kS/h + kSdo/D] Co = [(1 + kSdo/D)C*]/[1 + kS/h + kSdo/D] When D is large, the second equation becomes Ci = Co, implying that the oxidation rate is controlled by the reaction rate constant kS and by Ci (= Co), that is, a reaction-controlled case. When D is very small, h(C* - Co) = 0 = kSCi. Therefore, C* = Co and Ci = 0. The latter case is called diffusion-controlled case, as the oxidation rate depends on the supply of oxidant to the interface.

In order to calculate the oxide growth rate, we define N1 as the number of oxidant molecules incorporated into a unit volume of the oxide layer. If oxygen is the reactant, N1 = 2.2 x 1022 atoms/cm3 because the density of SiO2 is 2.2 x 1022 cm-3. If water is used, N1 becomes 4.4 x 1022 cm-3 as two H2O molecules are incorporated into each SiO2 molecule. The differential equation for oxide growth is given by
* ( ) d d k C o s = = N1 k C s i ks ksdo dt 1+ + h D

With an initial condition of do(t = 0) = di, the solution is do2 + Ado = B (t + ) where A 2D [1/kS + 1/h], B 2DC* / N1, and (di2 + Adi) / B. The quantity represents a shift in the time coordinate to account for the presence of the initial oxide layer di. Solving for do as a function of time gives

do t + = 1 + 2 A / 2 A / 4B

1/ 2

For long oxidation times, i.e., t >> and t >> A2/4B, do2 Bt. B is therefore called the parabolic rate constant. For short times, i.e., (t + ) << A2/4B, do [B/A](t + ), and B/A is referred to as the linear rate constant.

Rate constants for wet oxidation of silicon

Oxidation temperature (oC) 1200 1100 1000 920 A (m) Parabolic rate constant B (m2/h) 0.720 0.510 0.287 0.203 Linear rate constant B/A (m/h) 14.40 4.64 1.27 0.406

(h)

0.05 0.11 0.226 0.50

0 0 0 0

Rate constants for dry oxidation of silicon

Oxidation temperature (oC) 1200 1100 1000 920 800 A (m) Parabolic rate constant (m2/h) 0.045 0.027 0.0117 0.0049 0.0011 Linear rate constant B/A (m/h) 1.12 0.30 0.071 0.0208 0.0030

(h)

0.040 0.090 0.165 0.235 0.370

0.027 0.076 0.37 1.40 9.0

Oriental Dependence
The rate of oxidation depends on the availability of reaction sites on the silicon substrates. Hence, as the surface areal density of atoms is dependent on crystal orientation, oxidation rates are expected to be orientation dependent. Oxidation on the <111> crystal plane occurs at a higher rate because there are a higher number of surface atoms, i.e. reaction sites or chemical bonds, when compared to a <100> plane.
Orientation Area of unit cell (cm2)
2a 2
1 3a 2 2

Si atoms in area

Si bonds in area

Bonds available

Available N relative bonds, N to <110> (1014 cm-2) 9.59 11.76 6.77 1.000 1.227 0.707

<110> <111> <100>

4 2 2

8 4 4

4 3 2

a2

Rate constants for silicon oxidation in H2O (640 Torr)

Oxidation Temp (oC) 900 950 1000 1050 1100 Orientation A (m) Parabolic Linear rate B/A ratio rate constant constant <111>/<100> B (m2/h) B/A(m/h) 0.143 0.151 0.231 0.231 0.314 0.314 0.413 0.413 0.521 0.517 0.150 0.252 0.311 0.524 0.664 1.163 1.400 2.307 2.977 4.926 1.68 1.68 1.75 1.65 1.65 Average 1.68

<100> <111> <100> <111> <100> <111> <100> <111> <100> <111>

0.95 0.60 0.74 0.44 0.48 0.27 0.295 0.18 0.175 0.105

Oxide thickness versus oxidation time for silicon in H2O at 640 Torr

Effects of Impurities
Moisture much higher oxidation rate with traces of water in the ambient Boron (segregation into oxide) enhanced diffusion through the weakened bonds Phosphorus (segregation into silicon) - concentration dependence observed only at lower temperature, where the surface reaction becomes important. This dependence may be the result of phosphorus being segregated into the silicon

Oxidation of boron-doped silicon in wet oxygen as a function of temperature and boron concentration

Oxidation of phosphorus-doped silicon in wet oxygen as a function of temperature and phosphorus concentration

High Pressure Oxidation

Plasma Oxidation
Anodic plasma oxidation has all the advantages associated with the high-pressure technique and also offers the possibility of growing high-quality oxides at even lower temperatures. Plasma oxidation is a low-pressure process usually carried out in a pure oxygen discharge. The plasma is sustained either by a highfrequency or DC discharge. Placing the wafer in the uniform density region of the plasma and biasing it slightly negatively against the plasma potential allows it to collect active charged oxygen species. The oxidation rate typically increases with higher substrate temperature, plasma density, and substrate dopant concentration.

Rapid Thermal Oxidation

Rapid thermal oxidation (RTO) is increasingly used in the growth of thin, high-quality dielectric layers. The primary issues that differentiate RTO from conventional thermal oxidation are the more complex chamber design, radiation source, as well as temperature monitoring. From the point of view of oxide-growth kinetics, RTO may be influenced by both thermally activated processes and a non-thermal, photon-induced process involving monatomic O atoms generated by UV and creating a parallel oxidation reaction that dominates at lower temperature. RTO growth kinetics exhibit activation energies differing from those measured in conventionally grown oxides. In the initial stage (on the order of 20 seconds), the RTO growth rate is linear followed by nonlinear growth. The duration of the linear region is hardware dependent, particular the heating source.

Oxide Properties
A silicon dioxide layer can provide a selective mask against the diffusion of dopant atoms at elevated temperature, a very useful property in IC processing. For it to work, the dopant diffusion rate in the oxide must be slow with respect to that in silicon, so that the dopant does not diffuse through the oxide in the masked region into the silicon. The masking oxide thickness must also be large enough to prevent it from reaching the silicon substrate. The often used n-type impurities as well as boron have very small diffusion coefficients in oxide and are compatible with oxide masking. However, this is not true for gallium, indium, and aluminum.

Diffusion constants in SiO2

Dopants B Ga P As Sb Diffusion constants at 1100oC (cm2/s) 3.4 x 10-17 to 2.0 x 10-14 5.3 x 10-11 2.9 x 10-16 to 2.0 x 10-13 1.2 x 10-16 to 3.5 x 10-15 9.9 x 10-17

Oxide Charges
Various charges and traps exist in thermally grown oxide films. If a charge is present close to the Si/SiO2 interface, it can induce a charge of the opposite polarity in the underlying silicon, thereby affecting the ideal characteristics of the device, such as the threshold voltage of a MOS capacitor.

Oxide-trapped charges (Qot) may be positive or negative, due to holes or electrons being trapped in the bulk of the oxide. They can be annealed out by low-temperature treatment.

Mobile ion charges (Qm) are attributed to alkali ions such as Na, K, and Li, as well as negative ions and heavy metals. They originate from processing materials, chemicals, ambient, or handling. Common techniques employed to minimize Qm include cleaning the furnace tube in a chlorine ambient, gettering with phosphosilicate glass (PSG), and using masking layers such as silicon nitride. Fixed oxide charges (Qf) are located in the oxide within approximately 3 nm of the SiO2 / Si interface. Qf cannot be charged or discharged easily.

Interface-trapped charges (Qit) can interact with the underlying silicon. They originate from structural defects related to the oxidation process, metallic impurities, and bond-breaking processes. A low temperature hydrogen anneal at 450oC effectively neutralizes most interface-trapped charges.

Dopant Redistribution
During thermal oxidation, the interface advances into the silicon substrate, and doping impurities will redistribute at the interface until its chemical potential is the same on each side of the interface. The ratio of the equilibrium concentration of the impurity in silicon to that in SiO2 at the interface is called the equilibrium segregation coefficient. Two additional factors that influence the redistribution process are the diffusivity of the impurity in the oxide (if large, the dopant can diffuse through the oxide rapidly, thereby affecting the profile near the Si - SiO2 interface) and the rate at which the interface moves with respect to the diffusion rate.