NEURAL RECORDING AMPLIFIERS Case Study

Report
submitted in fulfillment of the requirements for

Research Attachment 1 by ANOOP C PATIL (A0107260U)

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE SINGAPORE MARCH, 2013

NEURAL RECORDING AMPLIFIERS Case Study

by

ANOOP C PATIL (A0107260U)

Under

Prof. Thakor
Director, SINAPSE Provost Chair Prof., Dept. of ECE, NUS

Xu Yong Ping
Assoc. Prof., Dept. of ECE, NUS

Report
submitted in fulfillment of the requirements for

Research Attachment 1

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING

NATIONAL UNIVERSITY OF SINGAPORE SINGAPORE MARCH, 2013

ACKNOWLEDGEMENT
I express my sincere thanks to my main supervisor Prof. Thakor, Director, SINAPSE & Professor, Dept. of ECE, NUS and co-supervisor Assoc. Prof. Yong Ping, Dept. of ECE, NUS for giving me an opportunity to carry out the research attachment under their guidance. I express my gratitude for their valuable suggestions while carrying out the attachment.

Anoop C Patil

ABSTRACT

The following report involves the study of neural recording amplifiers used to record neural signals. Neural recording amplifier forms a critical block in the neural signal recording and stimulation link as it is involves signal acquisition from the nerves. Neural signals are weak and hence need amplification. Low power operation is a must as these amplifiers are designed to be implantable. With many critical issues involved in the design of neural signal recording amplifiers, the study of designs is justified. The report includes study of some of the designs for amplifiers, their merits, analysis and comparison with other designs studied. The interplay between many design parameters/issues leading to trade-offs in the design is appreciated. The effect of noise on the quality of signals acquired and efforts to minimize the input referred noise is noted. Low power design and low noise design impose steep costs on each other; the criticality of which is given by the fact that power of the amplifier is proportional to inverse squared scaling of input referred noise. This write up includes salient points of each of the studied designs and concludes with a performance comparison between them. This report is towards fulfillment of the requirements for the research attachment - 1.

Contents
1 Introduction 2 Case studies 2.1
Analysis and Design of Tunable Amplifiers for Implantable Neural Recording Applications - review

6 7 7 9 9

2.1.1 Performance review 2.1.2 Design Key notes

2.2

Design of A Neural Recording Amplifier with Tunable Pseudo Resistors - review

2.2.1 Performance review 2.2.2 Design Key notes

10 11 11

2.3 A Low-Power Low-Noise CMOS Amplifier for Neural

Recording Applications - review 2.3.1 Performance review 2.3.2 Design Key notes 12 14 14

2.4 Design of a Micro Power Amplifier for Neural Recording

Applications - review 2.4.1 Performance review 2.4.2 Design Key notes 15 16 16

2.5 An Energy-Efficient Micro-power Neural Recording Amplifier

- review

2.5.1 Performance review 2.5.2 Design Key notes

17 19 19

2.6 A Differential Difference Amplifier for Neural Recording

system with tunable low frequency cut off review

2.6.1 Performance review 2.6.2 Design Key notes

20 21 21

2.7 A Compact, Low Input Capacitance Neural Recording

Amplifier with Cin/Gain of 20fF.V/V - review 2.7.1 Performance review 2.7.2 Design Key notes 22 23 23 24 25 26

3 Performance comparison 4 Conclusion 5 References

5

Chapter 1 Introduction

Neural recording amplifiers are the most critical blocks in neural recording systems. the nature of neural signals presents the challenge for the efficient design of the amplifier. Neural signals are weak and hence have a small amplitude[1]. The amplifier should have a low input referred noise to allow detection of neural signals (as low as tens of V). The gain of the amplifier needs to be programmable as the peak amplitude of the signals may vary due to differences in electrode type and conditions[3]. The electrode tissue interface introduces a DC offset which must be removed as it saturates the amplifier. The input impedance of the amplifier needs to be high to minimize attenuation of the input signal. This has to be higher than the electrode tissue interface impedance. the amplifier should also be characterized with a high CMRR and A high PSRR to ward off the common mode voltage at the input and the interference from the power supply[5]. The design should be of low power to avoid tissue heating. Bandwidth of the amplifier should be tunable.

Chapter 2 Case studies 2.1 [1] Analysis and Design of Tunable Amplifiers for Implantable Neural Recording Applications
Hamidreza Rezaee-Dehsorkh, Student Member, IEEE, Nassim Ravanshad, Student Member, IEEE, Reza Lotfi, Member, IEEE, Khalil Mafinezhad, and Amir M. Sodagar, Senior Member, IEEE IEEE Journal on Emerging and Selected Topics in Circuits and Systems, VOL1, NO. 4, December 2011.

An integrated tunable neural recording amplifier is presented in this paper. The structure of the front end amplifier includes a low noise amplifier, a tunable band pass filter and a variable gain amplifier. The FEA amplifies the neural signals in two frequency modes: 300Hz 10kHz for neural spikes and 4Hz 10kHz to amplify Local Field Potentials. A three stage circuit is proposed as shown in figure below in fig. 1:

Fig. 1 : Schematic of proposed three stage amplifier

Stage 1: At the input of first stage, a differential input signal is capacitively coupled to the amplifier. DC polarization of signals are rejected. The gain of this stage is C11/C12 involving a negative feedback path. The low cut off frequency and the high cut off frequency of this stage are lower and higher than that of the overall system. A single stage amplifier is used as first stage OTA. OTA and pseudo resistors contribute to overall input referred noise of the amplifier. OTA noise is minimized by increasing OTA trans-conductance and proper transistor sizing. PMOS transistors with large gate areas are used as input devices. Stage 2:
7

This is the tunable band pass filter. It removes the low and high frequency content of the input neural signal. The pass band is determined by this stage. Stage 3: The third stage is a Variable Gain amplifier loaded by the large input capacitance of the ADC to which its connected to. Gain of this stage is given by C31/C32 where C32 is the equivalent feedback capacitance. A two stage high trans-conductance OTA is used. The optimum distribution of gain over the three stages is as given: G1=50, G2=2, G3=5. The first stage consumes most of the power, the second stage uses least power and the third stage lies between the first two in power consumption. Discussion of Pseudo resistor implementation is important in context of design. Current controlled pseudo resistors are used in the design. The structure of the implemented resistor and its variations with voltage across the resistor are as shown below in fig. 2 and fig. 3:

Fig. 2 : Cross coupled pseudo resistor structure

Fig. 3: Resistance variations with voltage applied across the resistor

A linear pseudo resistor with wide range of tunability is implemented in the second stage using the above structure. Its as shown in fig 4. A pseudo cross coupled structure in series with voltage controlled MOSFET structure is used. The MOSFET structure (shown
8

in red) is used as switch for coarse tuning of low cut off frequency. VCTL-BW is set to 0 to set the low cut off frequency to 300Hz and when its 1, the low cut off is at 4Hz.

Fig. 4: Proposed pseudo resistor structure in design

2.1.1 Performance review Technology : 0.18m Supply voltage: 1.8V Gain: 52.5 57.5dB Tunable BW: 4/300 10kHz Tunable Power consumption: 21W Input referred noise: 2.6/2.38Vrms (0.5Hz 50kHz) NEF: 3.38/3.07 CMRR: 88dB PSRR: 85dB Total capacitance: 24.1pF

2.1.2 Design Key notes 1. 2. 3. 4. 5. Divide and conquer approach 3 stages Tunable feature for resistors, low cut off frequency, Gain Fine tuning and coarse tuning for fL Three stage amplifier - Total capacitance and total area is less High CMRR & PSRR

2.2 [2] Design of A Neural Recording Amplifier with Tunable Pseudo Resistors
Kai-Wen Yao, Cihun-Siyong Alex Gong, Shan-Ci Yang and Muh-Tian Shiue 2011 IEEE

This paper presents a neural recording amplifier using a tunable pseudo resistor with wide operating voltage range. The resistor structure is voltage controlled and consists of a serial connected PMOS device and an auto tuning circuit. The proposed structure provides ultrahigh resistance to cancel Dc offset from electrode electrolyte interface. A low noise low power neural recording amplifier with pseudo resistors is designed. The architecture is as given below in fig. 5:

Fig. 5 : Neural amplifier with proposed pseudo resistor

The amplifier uses operational trans-conductance amplifier with cross coupled loads to enhance open loop gain due to the negative trans-conductance values and to reduce noise. the input pair is biased in threshold region with large W/L ratio to reduce the total power consumption. The adder illustrated in the design above is implemented a shown in fig. 6.

10

Fig. 6: Adder Block diagram

2.2.1 Performance review Technology: 0.18m Supply voltage: +/- 0.9V Supply current: 1.72A Gain: 40dB BW: 7kHz Power consumption: 3.1W Input referred noise: 5.98Vrms (0.4Hz 7kHz) NEF: 7.2 CMRR: 67dB Low frequency cut off: 0.4-300Hz

2.2.2 Design Key notes 1. 2. 3. 4. Low power design Voltage controlled pseudo resistors Target design to replace MOS bipolar pseudo resistor Pseudo-resistor robust against voltage offset and process variations

11

2.3 [3] Low-Power Low-Noise CMOS Amplifier for Neural Recording Applications
Reid R. Harrison, Member, IEEE, and Cameron Charles, Student Member, IEEE
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 6, JUNE 2003

This paper presents a neural recording amplifier structure suitable for recording biopotentials from milli-hertz range to 7kHz. The schematic of the neural amplifier is as shown in fig. 7:

Fig. 7: Schematic of neural amplifier

The neural amplifier design is based on the structure shown above where the mid band gain AM is set at C1/C2 and the BW is set by gm/(AM*CL) where gm is the trans-conductance of the OTA used in the design. Two MOS bipolar devices are used in series to reduce distortion for large output signals. Transistors Ma to Md are MOS bipolar resistors acting as a diode connected pMOS transistor for negative VGS and as parasitic p-n-p bipolar junction transistor for positive VGS. For small voltage across this device, the resistance offered by the structure is very high as shown in the fig. 8.

12

Fig. 8: Incremental resistance of single MOS-bipolar element Low power low noise OTA design uses current mirror OTA, the schematic of which is a shown in fig 9. The input transistors are made large to minimize 1/f noise. Flicker noise is of major concern for a low noise circuit. PMOS devices contribute less noise compared to their NMOS counterparts at the same current level and as the device is scaled to a large size, 1/f noise decreases. The operating point of the transistors in the OTA design are given in fig. 10 which gives the scaling of all the transistors used in the design with the currents flowing through them. The Inversion co-efficient of a transistor is calculated as the ratio of drain current to the inversion characteristic current and gives an idea on as to which kind of inversion the transistor is operating in. A device with IC>10 operates in strong inversion and with IC<0.1 in weak inversion.

Fig. 9: Schematic of current mirror OTA

13

Fig. 10: Operating point of transistors in OTA design 2.3.1 Performance review Supply voltage: +/-2.5V Gain tunable 40dB BW tunable 7.2k Power consumption: 80W Input referred noise: 2.2Vrms (0.5-50k Hz) CMRR >=83dB PSRR >=85dB NEF 4 (Theoretical value for the topology used: 2.9) .This factor signifies the powernoise trade-off for a design and the value for the implemented design should be closer to the theoretical value for the particular topology used. 2.3.2 Design Key notes 1. 2. 3. 4. 5. 6. Amplifies signals down to millihertz range passes signals from 0.025Hz-7.2kHz Crosstalk at f=1kHz : -64dB Wastes lot of current hence power in the mirror leg of the OTA Power consumption on the higher side High CMRR PSRR No off chip components used to pass low frequency signals

14

2.4 [4] Design of a Micro Power Amplifier for Neural Recording Applications
Ghazi BEN HMIDA, Abdennaceur KACHOURI and Hamadi GHARIANI
2009 6th International Multi-Conference on Systems, Signals and Devices

This paper presents a micro power amplifier for neural signal recording using a differential pair as input stage. This design achieves a high CMRR relative to other designs studied. Fig. 11 gives the schematic of the input differential stage used in the design.

Fig. 11: Circuit differential stage In order to reduce the flicker noise dominated at low frequencies, the input transistors are made large and PMOS devices are used. M1 and M2 have a W/L ratio equal to 100 with L=1m. The sizes of the transistors for the design is as given in Fig. 12.

Fig. 12: Neural amplifier parameter values

15

The current design achieves a high CMRR but at a cost. The noise efficiency factor and the input referred noise for this design is quite high in comparison to other designs. Refer the performance comparison at the end of the report for comparative values.

2.4.1 Performance review Supply voltage: +/-1V Gain 44dB Power consumption: 9.22W Input referred noise: 14.8Vrms (100-10k Hz) CMRR =113dB CMRR > 92dB for f<10kHz PSRR = 73dB / 75.3dB (Vss/Vdd) NEF 13.22 DC offset 0.2mV 2.4.2 Key notes of the design 1. 2. 3. 4. 5. Amplifier achieves a high CMRR (in comparison to other designs studied) High CMRR with low power consumption NEF is large; Input referred noise is more Good PSRR achieved Use of NMOS gates as input MOS pair is questioned.

16

2.5 [5] An Energy-Efficient Micropower Neural Recording Amplifier

Woradorn Wattanapanitch, Student Member, IEEE, Michale Fee, and Rahul Sarpeshkar, Senior Member, IEEE
IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 1, NO. 2, JUNE 2007

This paper describes an ultra-low power design and is the lowest power and the most energy efficient among all designs studied. Another highlight of the design is that it achieves input referred noise which is close to the theoretical limit for the topology used. The design offers robust rejection of common mode signal and power supply noise. The bandwidth of the amplifier can be adjusted for recording both neural spikes or local field potentials. It consumes 7.6W of power and offers a NEF of 2.67. A very efficient power noise trade-off is achieved by the use of a low power low noise OTA topology that makes efficient use of the supply current. Fig. 13 gives the overall schematic of the neural amplifier.

Fig. 13: Overall circuit design schematic

The design has two stages: Gain stage and the band pass filter stage to shape the pass band. The operation of the amplifier can be easily understood by the block diagram of the neural amplifier as in fig. 14. Cp,in is included to model the input parasitic capacitances at input terminals of the gain stage. the input referred noise of the OTA is modeled as vn2 term added to the system at the input. The gain stage is a high gain amplifier and is modeled by
17

Gm and Ro where Gm and Ro represent the trans-conductance and output resistance of the gain stage OTA respectively. In band pass stage, Rp is the resistance of the series PMOS transistors operating in triode region. The value of Rp is set by Vtune. The combination of C and Rp realizes the high pass cut off frequency for the amplifier. The schematic of the low power OTA is given in fig 15. The schematic uses a modified version of a standard folded cascade topology. The modified topology is designed in such a way that the current in folded branch M7-M12 is only a small fraction of the current in the input differential pair transistors. M1 and M2; the fraction being 1/16. This makes the noise contributed by the folded branch to the input referred noise, very small. To achieve such severe current scaling, the transistors M5 and m^ are biased carefully using the bias circuits formed by Mb2, Mc2 and Mc3. The current sources are cascoded to improve their output impedances and thereby ensure accurate current scaling. Power in bias circuit is saved by the current scaling ratio between Mb1 and Mb2 (16:1). For an amplifier to have a low input referred noise, the trans-conductance of the OTA needs to be maximal for a given current level. With the extreme current scaling technique used in this design, Gm is significantly less than gm1. Gm is increased up to gm1 by the use of source degenerated transistors M5 and M6; another low power design technique. Device sizing is another critical factor of any design. To achieve low input referred noise, the overall trans-conductance of the OTA needs to be maximized and is nearly equal to the trans-conductance of the input transistor. M1 and M2 are operated in sub-threshold region and they have large W/L ratios. The NE of the design is 2.47 which means that there are 2.47 sub threshold devices which contribute noise. This design minimizes almost all sources of noise except that of M1 and M2. The actual NEF is 2.47 which is very close to the theoretical value for the topology used 2.02. The key techniques for achieving good power noise trade-off are the use of source degenerated current mirrors and the severe current scaling ratio between the input differential pair transistors and the folded branch transistors.

Fig 14: Functional block diagram of neural amplifier

18

Fig 15. Schematic of the low noise OTA M1-M10 are operated in sub threshold region and transistors M11 and M12 are operated in above threshold region. 2.5.1 Performance review Supply voltage: 2.8V ; total current 2.7A Gain 41dB Power consumption: 7.6W Input referred noise: 3.06Vrms (10-98k Hz) CMRR =66dB (45Hz 5.32kHz) PSRR = 75dB NEF 2.67 (Theoretical NEF limit : 2.02 ; close to this value ) BW : 45Hz 5.32kHz Dynamic range 1% THD : 58dB

2.5.2 Design Key notes 1. 2. 3. 4. 5. 6.

19

Lowest power consumption Most energy efficient NEF closer to theoretical limit Good PSRR and CMRR achieved Tunable bandwidth for recording neural spikes and LFP All mosfets in sub threshold region to reduce noise

2.6 [6] A Differential Difference Amplifier for Neural Recording system with tunable low frequency cut off
Kai-Wen Yao, Wei-Chih Lin, Cihun-Siyong Alex Gong, Yu-Ying Lin, and Muh-Tian Shiue
2008 IEEE

This paper presents a low noise low power architecture of difference differential amplifier for neural recording applications. the design combines DC offset rejection and low frequency cut off tuning; the former is achieved by ac coupling using a capacitor and a MOS bipolar pseudo resistor in series and the latter depends on feedback capacitor and floating tunable resistor which contributes a low frequency pole. Fig 16 gives the schematic of the neural amplifier and Fig 17 its block diagram. In principle, making the transistors to work in sub threshold region is the popular way to decrease power consumption. To add to this, large area of the input stage reduces flicker noise of the circuit. When transistors are operated in sub threshold region, large gm values are obtained for the same scale of current and hence larger gain is achieved. A floating tunable resistor is achieved which offers large resistance and good tuning capability. The structure of the resistor is as shown in fig 18. The symmetric structure makes sure stable resistance in spite of current direction and hence becomes convenient to adjust resistance for frequency tuning.

Fig 16 : Schematic of neural amplifier

20

Fig 17. Block diagram of the neural amplifier

Fig 18. Schematic of tunable resistor

2.6.1 Performance review Supply voltage: +/- 0.9V ; total current 14.4A Gain 41dB BW : 10.3kHz (Pass band : 107Hz to 10.3kHz) Power consumption: 26W Input referred noise: 4.83Vrms CMRR =78dB PSRR = 75dB NEF 7.0 (a large value in comparison) 2.6.2 Design Key notes 1. 2. 3. 4. 5. 6. 7.
21

concentrates on DC offset rejection Low frequency tuning NEF large Good CMRR achieved Tunable bandwidth for recording neural spikes and LFP All mosfets in sub threshold region to reduce noise and power consumption Larger gm values in sub threshold region for same current levels -> larger gain for small current consumption ; 1/f noise reduced

2.7 [7] A Compact, Low Input Capacitance Neural Recording Amplifier with Cin/Gain of 20fF.V/V
Kian Ann Ng and Yong Ping Xu
BioCAS 2012

This paper presents a novel approach to reduce input capacitance and hence the overall area of the amplifier without sacrificing the mid band gain. Same value of mid band gain is achieved with less input capacitance by realizing the feedback path with a T capacitor network instead of a single feedback capacitor. The lowered input capacitance also offers increased input impedance. The design addresses the direct tradeoff between input capacitance and chip area versus amplifier gain. To get a good mid band gain, either input capacitance has to be increased or the feedback capacitor has to be lowered. However the lower value of the feedback capacitor is dictated by the parasitic capacitance and hence can be lowered much. Increasing input capacitance increases area and also lowers input impedance. This constraint is relaxed by the use of T capacitor network which reduces the feedback capacitance by a factor 2(N+1) and hence paving way for either reducing the input capacitance for the same value of mid band gain or for an enhanced gain value for the same value of input capacitance. Fig 19. gives the schematic of the neural amplifier.

Fig 19 : Schematic of the neural amplifier with T capacitor network

22

2.7.1 Performance review Supply voltage: 3V ; total current 2A Gain 38dB BW : 1.4k 8.5k Hz Power consumption: 6W (good) Input referred noise: 6.72Vrms (8.4kHz) CMRR =74dB PSRR = 55dB NEF 4.0 (a large value in comparison)

2.7.2 Design Key notes 1. 2. 3. 4. 5. 6. concentrates on reducing input capacitance; hence area novel approach : use of T capacitor network to reduce overall feedback capacitance NEF good Good CMRR and PSRR achieved Same mid band gain with reduced input capacitance Relaxed input capacitance and area versus gain constraint

23

3 Performance comparison The following table gives a comparison between different design cases studied. The performance parameters are compared for all the designs. [1,2,3,4,5,6,7]

Dehsorkh et. al.

Kai-Wen Yao et.al.

Harrison

Ghazi BEN HMIDA et. al. +/- 1V / 4.61A / 9.22W

Wattanapa nitch et. al.

Kai-Wen Yao et.al. DDA +/- 0.9V / 14.4A

Kian Ann & Yong Ping

Supply voltage / current / Power consumption Gain

1.8V / 20.8W

+/- 0.9V / 1.72A

+/- 2.5V / 16A

2.8V / 2.7A

3V/ 2A

52.5-57.5 dB tunable

40dB

39.5dB

44dB

41dB

41dB

38.1dB

BW

4/300 10k tunable

7kHz

7.2kHz

8kHz

45Hz 5.32kHz

10.3kHz

1.4-8.5k

Input referred noise NEF

2.6/2.38Vr ms(0.5Hz 50kHz) 3.38/3.07

5.98Vr ms

2.2Vrms

14.8Vrms (10010kHz) 13.22

3.06Vrms

4.83Vrm s

6.72Vrms (8.4kHz BW)

7.2

2.67

CMRR PSRR

88dB / 85dB

67dB / -

>= 83dB / >=85dB

113dB / >73dB

66dB / 75dB

78dB / -

74dB / 55dB

Area / Cin

24.1pF (C total) (0.18 CMOS)

(0.18 CMOS)

0.16sq.mm (1.5 CMOS)

(0.35 CMOS)

0.16 sq.mm (0.5m CMOS)

0.084sq.m m (0.18m CMOS)

0.056sq.mm (0.35m)

24

4 Conclusion The report discusses the design facts and issues for each design. Performance review is summarized and some key notes regarding each design is presented. The design study was carried out to get familiar with the design issues and various design topologies and modifications / tweaks to the existing standard design topologies to achieve low power and low noise features. This report is towards the fulfillment of research attachment 1.

25

5 References 1. Dehsorkh et. al. , Analysis and Design of Tunable Amplifiers for Implantable Neural Recording Applications," IEEE Journal on Emerging and selected topics in circuits and systems, vol. 1, no.4 December 2011. 2. Kai-Wen Yao, Cihun-Siyong Alex Gong, Shan-Ci Yang and Muh-Tian Shiue , Design of A Neural Recording Amplifier with Tunable Pseudo Resistors, 2011 IEEE 3. R. R. Harrison and C. Charles, A low-power low-noise CMOS amplifier for neural recording applications, IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 958965, Jun. 2003. 4. Ghazi BEN HMIDA, Abdennaceur KACHOURI and Hamadi GHARIANI, Design of a Micro Power Amplifier for Neural signal recording, 6th International MultiConference on Systems, Signals and Devices, 2009 5. Woradorn Wattanapanitch, Michale Fee and Rahul Sarpeshkar, An EnergyEfficient Micropower Neural recording Amplifier, IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 1, NO. 2, JUNE 2007 6. Kai-Wen Yao, Wei-Chih Lin, Cihun-Siyong Alex Gong, Yu-Ying Lin, and MuhTian Shiue, Differential Difference Amplifier for Neural Recording System with Tunable Low-Frequency Cutoff, @2008 IEEE 7. Kian Ann Ng and Yong Ping Xu, Compact, Low Input Capacitance Neural Recording Amplifier with Cin/Gain of 20fF.V/V, BioCas 2011.

26