M5621

Acer Laboratories Inc.
--Preliminary, Confidential, Proprietary--
M5621 : High-Speed USB2.0 IDE Device Controller
Data Sheet
Section 1 : Introduction
1.1 Overview ALi's M5621 USB2.0 IDE Device controller provides a cost-effective solution for high-speed USB2.0 based application, such as USB-to-IDE bridge interface, scanner, printer, digital still camera or multi-function peripheral /communication /networking systems. With built-in USB2.0 transceiver and related high-speed circuitry, M5621 also integrates four user-configurable endpoints with bi-directional ping-pong buffers for maximized USB2.0 throughput operation. With extended design flexibility, M5621 can be configured for three different operation modes, including working as a USBto-IDE bridge interface, as a PIO/DMA based device controller, or as a UTMI-compliant USB2.0 standalone transceiver device. Through these highly flexible features and capabilities to work with embedded controller, external microcontroller or ISA-based Device CPU, M5621 is fully capable of achieving a most compact and yet cost-effective solution for varieties of high-speed-oriented peripheral system applications. 1.2 Features ! ! ! USB Specification revision 2.0 Compliant Support High-speed(HS) & Full-speed(FS) Operation with on-chip USB transceiver, SIE & UBL Supports 4 User-Configurable Endpoints for bulk, interrupt, control transfers to allow bulk-transfer-based device operation for IDE device, scanner, printer, camera or multi-function-peripheral application - Endpoint 0 : 64-byte FIFO support for Control transfer - Endpoint A : 512-byte Ping-Pong buffers for Bulk-In transfer - Endpoint B : 512-byte Ping-Pong buffers for Bulk-Out transfer - Endpoint C : 8-byte FIFO support for Interrupt transfer or Supplementary Bulk-In Transfer Endpoint ! ! Built-in High-performance Micro-controller Engine for interface, flow & multi-functional control Built-in USB2.0-to-IDE Interface Controller with general IDE interface & bulk-only transport of USB mass storage class support upto UDMA66 for storage devices as DVD/CD-ROM, CD-R/W, Harddisk and Compact Flash device, etc. ! ! ! ! ! Built-in PIO/DMA-based Device Controller with industry-standard 8/16-bit PIO/DMA & Multi-word DMA supported for standard MCU/DCPU operation Configurable Standalone UTMI-compliant USB2.0 PHY Operation Supported Optional External USB ID EEPROM, External Program ROM Interface & GPIOs Control Supported Built-in Clock Synthesizer for using low-cost 12Mhz crystal or external 12Mhz clock sources 100-pin TQFP or 64-pin TQFP package
DEC. 12, 2001 Document no. : 5621IDEda03.doc Acer Labs : 2F, 246, NeiHu Rd., Sec 1, Taipei, 114, R.O.C. Tel: 886-2-8752-2000, Fax: 886-2-8751-1001 Homepage : www.ali.com.tw
Page 1
Data Sheet
1.3 Functional Block Diagram
USB2.0 SIE/Txcvr USB Host System USB I/F USB2.0 Interface Controller
Configurable EndPoint FIFOs
8/16-bit PIO /DMA /IDE Interface
IDE /PIO /DMA Bus
IDE Device or Peripheral ASIC / DCPU
DMA Controller
Configuration Registers
Program ROM
Optional Program ROM
Clock Synthesizer
Embedded MCU Engine
GPIOs Optional USB ID EEPROM
1.4 System Application Diagram USB2.0 /1.1 I/F
(1) USB-to-IDE Operating Mode
USB2.0/1.1 Host System
IDE
M5621
Bus
IDE Devices (ATA/ATAPI Interface)
(2) USB Device Operating Mode
USB2.0 /1.1 I/F
8/16-bit PIO/DMA
M5621
or UTMI Bus
Peripheral Device ASIC System
(3) Multi-functional Control Operating Mode
USB2.0 /1.1 I/F
M5621
(100-pin package only)
8/16-bit PIO/DMA or GPIO Control
Peripheral Device ASIC System
External ROM
Page 2 DEC. 12, 2001 Document no. : 5621IDEda03.doc Acer Labs : 2F, 246, NeiHu Rd., Sec 1, Taipei, 114, R.O.C. Tel: 886-2-8752-2000, Fax: 886-2-8751-1001 Homepage : www.ali.com.tw
Data Sheet
Section 2 : Pin Description As shown below is the pin configuration for USB2.0-to-IDE interface operation. For the pin configuration of USB2.0 PIO/DMA device operation, please refer to ALI supplementary technical documentation. 2.1 Pinout Diagram TQFP100 pin description for USB2.0-to-IDE Interface configuration
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
ROMD4 ROMD3 ROMD2 ROMD1 ROMD0 VBUS GPIO<0>/EEPROMCLK/IDSEL0 GPIO<1>/EEPROMDAT/IDSEL1 GPIO<2>/USBPNP MCUCLKSEL HWSEL0(L) HWSEL1(L) HWSEL2(L) M5621 VCC (TQFP100) GND ROMOEJ ROMWRJ ROMA14 ROMA13 ROMA12 ROMA11 GND ROMA10 ROMA9 ROMA8
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
ROMA7 ROMA6 ROMA5 ROMA4 ROMA3 ROMA2 ROMA1 ROMA0 IDERESETJ VDD GND VDD5 IDED8 IDED9 IDED10 IDED11 IDED12 IDED13 IDED14 IDED15 IDEDRQ IDEIOWJ IDED7 IDED6 IDED5
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 GPIO<6> GPIO<7> GND ROMSEL CLKOUT USBAVDD USBAVSS DMF USBAVSS USBAVDD DMH DPH USBAVSS USBAVDD DPF USBRREF XTALI XTALO GND VDD RESETJ ROMA15 ROMD7 ROMD6 ROMD5 GPIO<5> GPIO<4> IDEDASP IDECS3FXJ IDECS1FXJ IDEA2 IDEA1 VCC GND IDEA0 VDD GND IDEPDIAGJ IDEIRQ IDEDACKJ GPO/USBSPEED IDEIORDY IDEIORJ IDED0 IDED1 IDED2 VDD GND IDED3 IDED4 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
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Data Sheet
TQFP64 pin description for USB2.0-to-IDE Interface configuration 49 50 51 52 53 54 55 56 67 68 69 60 61 62 63 64 USBAVDD USBAVSS DMF USBAVSS USBAVDD DMH DPH USBAVSS USBAVDD DPF USBRREF XTALI XTALO GND VDD RESETJ
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17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
IDED6 IDED7 IDERESETJ VDD GND VDD5 IDED8 IDED9 IDED10 IDED11 IDED12 IDED13 IDED14 IDED15 IDEDRQ IDEIOWJ
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VBUS GPIO<0>/EEPROMCLK/IDSEL0 GPIO<1>/EEPROMDAT/IDSEL1 GPIO<2>/USBPNP MCUCLKSEL HWSEL0(L) HWSEL1(L) HWSEL2(L) M5621 VCC (TQFP64) GND IDED0 IDED1 IDED2 IDED3 IDED4 IDED5
IDEDASP IDECS3FXJ IDECS1FXJ IDEA2 IDEA1 VCC GND IDEA0 VDD GND IDEPDIAGJ IDEIRQ IDEDACKJ GPO/USBSPEED IDEIORDY IDEIORJ
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
Data Sheet
2.2 Pin Description As shown below is the pin configuration for USB2.0-to-IDE interface operation. For the pin configuration of USB2.0 PIO/DMA device operation, please refer to ALI supplementary technical documentation.
Pin Number TQFP100 TQFP64 System Signal (6 pins) 92 60 XTALI 93 61 XTALO 96 64 RESETJ 80 CLKOUT 13 8 HWSEL2 12 7 HWSEL1 11 6 HWSEL0 IDE Interface (31 pins) 45 30 IDED15 44 29 IDED14 43 28 IDED13 42 27 IDED12 41 26 IDED11 40 25 IDED10 39 24 IDED9 38 23 IDED8 48 18 IDED7 49 17 IDED6 50 16 IDED5 51 15 IDED4 52 14 IDED3 55 13 IDED2 56 12 IDED1 57 11 IDED0 46 31 IDEDRQ 61 36 IDEDACKJ 47 32 IDEIOWJ 58 33 IDEIORJ 62 37 IDEIRQ 70 45 IDEA2 69 44 IDEA1 66 41 IDEA0 71 46 IDECS1FXJ 72 47 IDECS3FXJ 63 38 IDEPDIAGJ 73 48 IDEDASP 34 19 IDERESETJ 59 34 IDEIORDY USB Interface Signal (11 pins) 87 55 DPH 86 54 DMH 90 58 DPF 83 51 DMF Pin Name
I/O
Description
ICLK OCLK IS O4 IS IS IS IO10U IO10U IO10U IO10U IO10U IO10U IO10U IO10U IO10U IO10U IO10U IO10U IO10U IO10U IO10U IO10U IS O10 O10 O10 IS O10 O10 O10 O10 O10 IS IS O8 IS USB USB USB USB
XTAL/OSC In XTAL Out System Reset, active low Programmable Clock Output Hardware Operation mode selection <2:0> 000: IDE 100 pin 001: IDE 64 pin IDE data <15:0>
IDE DMA Request IDE DMA Acknowledge IDE I/O Write IDE I/O Read IDE Interrupt IDE address <2:0>
IDE address 1FX chip select IDE address 3FX chip select IDE Pass Diagnostics: Cable assembly type identifier IDE bus slave device define IDE Device Reset IDE IO Channel Ready High-speed USB D+ High-speed USB DFull-speed USB D+ Full-speed USB DPage 5
Data Sheet
USBRREF VBUS Flash ROM interface ROMD7 ROMD6 ROMD5 ROMD4 ROMD4 ROMD2 ROMD1 ROMD0 ROMA15 ROMA14 ROMA13 ROMA12 ROMA11 ROMA10 ROMA9 ROMA8 ROMA7 ROMA6 ROMA5 ROMA4 ROMA3 ROMA2 ROMA1 ROMA0 ROMSEL ROMOEJ ROMWRJ MISC GPIO0 EEPROMCLK IDSEL0 GPIO1 EEPROMDAT IDSEL1 GPIO2 USBPNP GPO USBSPEED GPIO4 GPIO5 GPIO6 GPIO7 MCUCLKSEL Power pin VDD5 VDD VCC
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91 6 98 99 100 1 2 3 4 5 18 19 20 21 23 24 25 26 27 28 29 30 31 32 33 79 16 17 7 2 59 1 IS IS IS IS IS IS IS IS IS IS O4 O4 O4 O4 O4 O4 O4 O4 O4 O4 O4 O4 O4 O4 O4 O4 IS O4 O4 IO4 External Reference. Requires 15K ohm resistor connected to ground. USB bus power detection. ROM data bus
ROM address bus
Select MCU booting from External ROM ROM output enable Flash ROM write strobe General purpose IO pin 0. EEPROM Clock USB ID selection 0 General purpose IO pin 1. EEPROM Data USB ID selection 1 General purpose IO pin 2 Indicate USB Plug & Play, active low for LED IDE cable select Indicate USB operation speed, low for high speed, high for full speed. General purpose IO pin 3 General purpose IO pin 3 General purpose IO pin 3 General purpose IO pin 3 General purpose IO <2> 5V Power for 5V input tolerance. If there is not any 5V input signal, this pin could be connected to 3.3V. 3.3V Power for IO pad 3.3V Power for core
IO4
9 60 74 75 76 77 10 37 35,54,65 14,68
4 35
IO4 O4 IO4 IO4 IO4 IO4 IO4 P P P
5 21 20,40 9,43

USBAVDD GND USBAVSS 81,85,89 49,53,57 15,22,36,53 10,21,39,42 ,64,67,78 82,84,88 50,52,56 P P P
Data Sheet
3.3V Power for USB transceiver Ground for IO and core Ground for USB transceiver
Type Descriptions: IS ISU O4 O10 IO4 IO10U ICLK OCLK USB Input with Schmidt Trigger Input with Schmidt Trigger, internal pull-up. Output with sink 4 mA, source 4 mA Output with sink 10 mA, source 10 mA Input with Schmidt Trigger/Output with sink 4 mA, source 4 mA Input with Schmidt Trigger, internal pull-up/Output with sink 10 mA, source 10 mA CLK input at 12 MHz CLK output at 12 MHz USB transceiver
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Data Sheet
Section 3 : Functional Description 3.1 General IDE Interfaces and DMA Controller (IDEC)
M5621 provides general IDE interface to connect with most IDE devices with ATA or ATAPI compliant interface. M5621's IDE interface unit supports PIO and 16-bit DMA, UltraDMA (support up to UltraDMA/66) transfer. And its DMA controller is designed to transfer mass storage data through IDE interface and uses M5621's on-chip ping-pong FIFOs of Endpoint A & Endpoint B for pass data to USB bus. 3.2 Embedded Micro-Controller Unit M5621 embeds a high-performance MCU to enable an exceptional data transfer performance through USB bus. The embedded MCU unit also provides flexible programmability and capable performance horsepower to ease the operations for systematic control, USB Plug-N-Play operation and optimize the data transfer operation for IDE device control/application. M5621 can utilize external ROM/EEPROM interface to provide a future upgrade path for improving performance and interface compatibility as necessary. 3.3 USB Interface with Proven Low-Power CMOS Design M5621 builds in USB2.0-compliant transceiver, Serial Interface Engine (SIE) and Command Decoder (UBL) to be fully compliant with high-speed USB specifications revision 2.0 at operation rate up to 480Mb/s. The compliance-proven USB2.0 transceiver design provides two standard differential single-ended connection for data transmission and reception. With existed functional support to USB suspend and resume operation, M5621 also utilizes ALi proven low-power CMOS technology to further reduce the actual operating and suspend-mode power consumption for the USB-based peripheral system. 3.4 Built-in On-Chip Clock Synthesizer With on-chip clock synthesizer, M5621 is allowed to use nominal low-cost 12MHz crystal (or oscillator) by connecting to XTALI and XTALO, and generates standard internal high-frequency clock for USB interface. If the external 12MHz clock source is available, the XTALI input pin can be used as the clock input to provide more cost-saving in the clock circuitry. 3.5 User-Configurable End-Point Control M5621 supports four user-configurable USB end-point control units with standard USB command decoder, automatic CRC-checking and handshaking to fully meet USB specification. The associated command decoding and operational descriptions are described below. 3.5.1 Endpoint 0 This Endpoint is designed for USB command transfer including standard, class, vendor commands. The built-in UBL decodes the following standard commands, checks CRC and handshakes automatically. SET_FEATURE, CLEAR_FEATURE, SET_CONFIGURATION, GET_CONFIGURATION, SET_INTERFACE, GET_INTERFACE SET_ADDRESS, GET_STATUS Other UBL un-decoding commands are transferred to the micro-controller to service. 3.5.2 Endpoint A (BULK IN with DMA)
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Data Sheet
This Endpoint is designed for USB general data transfer with DMA support to link to IDE controller (IDEC). The maximum data transfer rate is 60 Mbytes/Sec from IDEC to Endpoint A. And the supported package size is 512 bytes for HS transfer, 64 bytes for FS transfer. 3.5.3 Endpoint B (BULK OUT with DMA) This Endpoint is designed for USB general data transfer with DMA support to link to IDE controller (IDEC). The maximum data transfer rate is 60 Mbytes/Sec from Endpoint B to ICEC. And the supported package size is 512 bytes for HS transfer, 64 bytes for FS transfer 3.5.4 Endpoint C (Interrupt or BULK IN) This endpoint is designed for interrupt transaction, be used only for CBI (Control, Bulk, Interrupt) transport.
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Data Sheet
Section 4 : Application Description
As shown below is the application description for USB2.0-to-IDE interface operation. For applying the USB2.0 PIO/DMA device operation, please refer to ALI supplementary technical documentation. 4.1 Firmware support Through the embedded MCU control, M5621 operates with internal ROM if ROMSEL is set to low. The embedded MCU firmware is designed to perform direct interface conversion between USB interface and the target IDE device. This conversion operation includes handling USB commands, processing USB device descriptors, and performing data transfer between USB and IDE bus. However, if its required to modify commands or revise different control behaviors for the interface conversion process, setting ROMSEL to high will allow an external programmed ROM be activated and provide command/instruction access from the external firmware. For 100-pin package of M5621, it is optional to use external firmware ROM, since the internal ROM should be sufficient for most USB2IDE application needs. However, M5621's 64-pin package can only allow internal firmware ROM to be used for USB2.0-to-IDE operation, due to pincount limitation.
4.2 Programming for the External USB ID E PROM M5621's USB ID can be modified by adding an external PnP E PROM. If the external E PROM exists after system power-up, M5621 will access the serial interface through the EEPROMCLK and EEPROMDAT pins. The serial data 2 (LSB first for all resource data) can be written to or read from the E PROM by sequentially writing or reading the mapping registers as to be further described in M5621 register definition.
2 2
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Data Sheet
Section 5 : Configuration Registers Address FF60: EEPROM Control/Status Register Bit Bit-Name RW Default Description 7 NONE r 0 None 6 EEPROM_RST rw 0 Reset EEPROM hardware, Self clear after complete 5 EEPROM_START rw 0 Request EEPROM_START timing, Self clear after complete 4 EEPROM_STOP rw 0 Request EEPROM_STOP timing, Self clear after complete 3 EEPROM_ACK rw 0 Request EEPROM_ACK timing, Read to check SLAVE_ACK 2 EEPRON_NOACK rw 0 Request EEPROM_NOACK timing, Self clear after complete 1 EEPROM_READ 0 Request EEPROM_READ timing, Self clear after complete, data will put in rw EEPROM_READ_DAT register 0 EEPROM_WRITE rw 0 Request EEPROM_WRITE timing, Self clear after complete, write data fro EEPROM_WRITE_DAT register Address FF61: EEPROM_WRITE_DAT register Bit Bit-Name RW Default 7-0 EEPROM_WRITE_DAT rw 00000000 Address FF62: EEPROM_READ_DAT register Bit Bit-Name RW Default 7-0 EEPROM_READ_DAT rw 00000000 Address FF63: EEPROM_TIMER register Bit Bit-Name RW Default 7-0 EEPROM_TIMER rw 00000010
Description Data write to SDAT bus
Description Data read from SDAT bus
Description SCLK Divider, EEPROM_TIMER*132.8ns
Address FFC0: DEVICE SETTING REGISTER Bit Bit-Name R/W Default Description 7 USBON rw 0 0 - the pull-up resistor on USB DP is turn-off initially. 1- Turn on the pull-up resistor on USB DP 6 RES_SPEED r 0 Check current speed mode on USB bus 0 HS 1 FS 5 EXP_SPEED rw 0 USB Support 0 Support USB2.0, HS & FS modes. 1 Support USB1.1, FS mode only. 4 RMT_WKUP_FEAT r 0 This bit reflects the host set/clear feature of remote wakeup 0 the device is currently disabled to request remote wakeup 1 the device is currently enabled to request remote wakeup 3 SUSPEND_STATUS r 0 This bit reflects if the USB bus is in suspend mode 0 normal 1 suspend 2 RESUME_WAKEUP rw 0 In suspend mode, the MCU asserts this bit to wake-up the USB bus and host system 0 normal 1 wake-up the USB 1 RMT_WKUP_SUPP rw 0 This bit set the data of Remote-Wake-up in GET_STATUS command 0 don't support remote wake-up 1 support remote wake-up 0 SELF_POWERED rw 0 This bit set the data of Self-Powered in GET_STATUS command 0 bus powered 1 self powered
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Data Sheet
Address FFC1: ENDPOINT 0 FIFO CONTROL REGISTER (EP0FCTR) Bit Bit-Name R/W Default Description 7 EP0EMP r 1 Endpoint 0 FIFO 0 not empty 1 empty 6 EP0FUL r 0 Endpoint 0 FIFO 0 not full 1 full 5 EP0FRC rw 0 Force Endpoint 0's current packet output to the USB host (available when the EP0DIR is 1, this bit is self-clear after sending the packet) 0 normal 1 force sending 4 EP0INI rw 0 Clear Endpoint 0's FIFO 0 normal 1 reset the Endpoint 0's FIFO 3 EP0OVF r 0 For EP0DIR=1, EP0FIFO is over-written. (MCU write to full FIFO) 0 normal 1 over-run For EP0DIR=0, EP0FIFO is over-read (MCU read from empty FIFO) EP0UNF 0 normal 1 under-run 2 SETUP rw 0 Indicate the setup stage 0 not in setup stage 1 in setup stage 1 EP0DIR rw 0 Select the Endpoint 0 transfer direction 0 SETUP/OUT (MCU receive) 1 IN (MCU transmit) 0 EP0STALL rw 0 Set the STALL condition 0 normal 1 STALL (after receiving next setup token, SIU resets this bit) Address FFC2: ENDPOINT 0 FIFO REGISTER (EP0FIFO) Bit Bit-Name R/W Default 0 EP0FIFO<7:0> r/w 0 Endpoint 0 FIFO data port
Description
Address FFC3: ENDPOINT A SETTING REGISTER (EPASETR) Bit Bit-Name R/W Default Description 7-6 EPATYP rw 00 Type of endpoint A 00 Reserved 01 Isochronous 10 Bulk 11 Interrupt 5-3 EPANUM rw 000 Logical endpoint A number 000 disable 001 Endpoint 1 010 Endpoint 2 011 Endpoint 3 100 Endpoint 4 101 Endpoint 5 110 Endpoint 6 111 Reserved ( disable ) 2 EPAINTF rw 0 This bit indicates interface number to which Endpoint A belongs 0 Interface 0 1 Interface 1 1-0 EPAFFTYP rw 00 This two bits are used to define Endpoint A FIFO type 00 ping-pong 01 single 10 extend ping-pong

11 Reserved
Data Sheet
Address FFC4: ENDPOINT A FIFO CONTROL REGISTER2 (EPAFCTR) Bit Bit-Name R/W Default Description 7 EPAEMP r 1 The FIFO of EPADS is 0 not empty 1 empty 6 EPAFUL r 0 The FIFO of EPADS is 0 not full 1 full 5 EPAFRC rw 0 Force Endpoint A current packet output to the USB host (The bit is selfclear after sending the packet) 0 normal 1 force sending This bit is available only for BULK_IN transfer,. 4 EPAINI rw 0 Initialize Endpoint A's FIFO (Both the two dataset FIFO) 0 normal 1 initialize FIFO 3 EPAOVF r 0 EPAFIFO is over-written. (MCU write to full FIFO) 0 normal 1 over-run 2 EPAALLEMP r 1 The FIFO (dual dataset FIFO) is 0 not all empty 1 all empty, i.e. there is no data in Endpoint A FIFO for transmission. 1 EPADS r 0 MCU interface points to Endpoint A 0 dataset 0 FIFO 1 dataset 1 FIFO 0 EPASTALL rw 1 Set the STALL condition 0 normal 1 STALL Address FFC5: ENDPOINT A FIFO REGISTER (EPAFIFO) Bit Bit-Name R/W Default 0 EPAFIFO<7:0> w 0 Endpoint A FIFO data port.
Description
Address FFC6: ENDPOINT B SETTING REGISTER (EPBSETR) Bit Bit-Name R/W Default Description 7-6 EPBTYP rw 00 Type of endpoint B 00 Reserved 01 Isochronous 10 Bulk 11 Interrupt 5-3 EPBNUM rw 000 Logical endpoint B number 000 disable 001 Endpoint 1 010 Endpoint 2 011 Endpoint 3 100 Endpoint 4 101 Endpoint 5 110 Endpoint 6 111 Reserved ( disable ) 2 EPBINTF rw 0 This bit indicates interface number to which Endpoint B belongs 0 Interface 0 1 Interface 1 1-0 EPBFFTYP rw 00 This two bits are used to define Endpoint B FIFO type
DEC. 12, 2001 Document no. : 5621IDEda03.doc Acer Labs : 2F, 246, NeiHu Rd., Sec 1, Taipei, 114, R.O.C. Tel: 886-2-8752-2000, Fax: 886-2-8751-1001 Homepage : www.ali.com.tw Page 13
Data Sheet

00 ping-pong 01 single 10 extend ping-pong 11 Reserved
Address FFC7: ENDPOINT B FIFO CONTROL REGISTER (EPBFCTR) Bit Bit-Name R/W Default Description 7 EPBEMP r 1 The FIFO of EPBDS is 0 not empty 1 empty 6 EPBFUL r 0 The FIFO of EPBDS is 0 not full 1 full 5 (Reserved) rw 0 4 EPBINI rw 0 Initialize Endpoint B's FIFO (Both the two dataset FIFO) 0 normal 1 initialize FIFO 3 EPBOVF r 0 EPBFIFO is over-read. (MCU read from empty FIFO) 0 normal 1 over-run 2 EPBALLEMP r 1 The FIFO (dual dataset FIFO) is 0 not all empty 1 all empty, i.e. there is no data in Endpoint A FIFO for transmission. 1 EPBDS r 0 MCU interface points to Endpoint B 0 dataset 0 FIFO 1 dataset 1 FIFO 0 EPBSTALL rw 1 Set the STALL condition 0 normal 1 STALL
Address FFC8: ENDPOINT B FIFO REGISTER (EPBFIFO) Bit Bit-Name R/W Default 0 EPBFIFO<7:0> r 0 Endpoint B FIFO data port
Description
Address FFC9: ENDPOINT C SETTING REGISTER (EPCSETR) Bit Bit-Name R/W Default Description 7-6 EPCTYP rw 00 Type of endpoint C 00 Reserved 01 Isochronous 10 Bulk 11 Interrupt 5-3 EPCNUM rw 000 Logical endpoint C number 000 disable 001 Endpoint 1 010 Endpoint 2 011 Endpoint 3 100 Endpoint 4 101 Endpoint 5 110 Endpoint 6 111 Reserved ( disable ) 2 EPCINTF rw 0 This bit indicates interface number to which Endpoint C belongs 0 Interface 0
Data Sheet
1-0 EPCFFTYP
rw
00
1 Interface 1 This two bits are used to define Endpoint C FIFO type 00 ping-pong 01 single 1x Reserved
Address FFCA: ENDPOINT C FIFO CONTROL REGISTER (EPCFCTR) Bit Bit-Name R/W Default Description 7 EPCEMP r 1 The FIFO of EPCDS is 0 not empty 1 empty 6 EPCFUL r 0 The FIFO of EPCDS is 0 not full 1 full 5 EPCFRC rw 0 Force Endpoint C current packet output to the USB host (The bit is selfclear after sending the packet) 0 normal 1 force sending This bit is available only for BULK_IN transfer,. 4 EPCINI rw 0 Initialize Endpoint C's FIFO (Both the two dataset FIFO) 0 normal 1 initialize FIFO 3 EPCOVF r 0 EPCFIFO is over-written. (MCU write to full FIFO) 0 normal 1 over-run 2 EPCALLEMP r 1 The FIFO (dual dataset FIFO) is 0 not all empty 1 all empty, i.e. there is no data in Endpoint C FIFO for transmission. 1 EPCDS r 0 MCU interface points to Endpoint C 0 dataset 0 FIFO 1 dataset 1 FIFO 0 EPCSTALL rw 1 Set the STALL condition 0 normal 1 STALL
Address FFCB: ENDPOINT C FIFO REGISTER (EPCFIFO) Bit Bit-Name R/W Default 0 EPCFIFO<7:0> w 0 Endpoint C FIFO data port
Description
Address FFCC: CLKOUT SELECT REGISTER(CLKSELR) Bit Bit-Name R/W Default Description 7:6 (Reserved) rw 00 5 EOTPOL rw 0 EOT polarity 0 high active 1 low active 4 DMAVLDH_ENJ rw 0 When DMA read, force validh or not 0 output dmavalidh enable 1 output dmavalidh disable 3 (Reserved) rw 0 2:0 CLKSELR<2:0> rw 000 Clkout frequency select 000 12MHz 001 24MHz 010 30MHz
Data Sheet

011 48MHz 100 60MHz 101 force High 110 force Low 111 tri-state
Address FFCD: GPIO REGISTER (GPIOR) Bit Bit-Name R/W Default 7 (Reserved) rw 0 6:4 GPIO_DIR[2:0] rw 000 GPIO direction 0 input direction 1 output direction 3 (Reserved) rw 0 2:0 GPIO_DATA[2:0] w 000 GPIO data
Description
Address FFD5: INTERRUPT ENABLE REGISTER 1 (INTENR1) Bit Bit-Name R/W Default Description 7 ResetIE rw 1 Enable USB Reset signal interrupt 0 disable 1 enable 6 SuspendIE/ rw 1 Enable Suspend/Resume/VBUS signal interrupt ResumeIE/VBusIE 0 disable 1 enable 5 EOTIE rw 0 Enable EOTInt 0 disable 1 enable 4 EPCTxIE rw 0 Enable Tx done interrupt for Endpoint C 0 disable 1 enable 3 EPBRxIE rw 0 Enable Rx done interrupt for Endpoint B 0 disable 1 enable 2 EPATxIE rw 0 Enable Tx done interrupt for Endpoint A 0 disable 1 enable 1 EP0RxIE rw 0 Enable Rx done interrupt for Endpoint 0 0 disable 1 enable 0 EP0TxIE rw 0 Enable Tx done interrupt for Endpoint 0 0 disable 1 enable Address FFD7: INTERRUPT FLAG REGISTER 1 (INTFLR1) Bit Bit-Name R/W Default Description 7 ResetInt r 0 SIU receives a reset signal 6 SuspendInt/ r 0 SIU receives a suspend/ resume interrupt ResumeInt/VBUSInt 5 EOTInt / DMARInt r 0 Either an "end-of-transfer active signal" or "DMAR down-count from 1 to 0", the interrupt status is asserted and the DMA cycle is stopped. 4 EPCTxD r 0 Tx done flag for Endpoint C 3 EPBRxD r 0 Rx done flag for Endpoint B 2 EPATxD r 0 Tx done flag for Endpoint A 1 EP0RxD r 0 Rx done flag for Endpoint 0 0 EP0TxD r 0 Tx done flag for Endpoint 0 Note : This is a Read-Cleared register, and the flag always reflect the event even if the interrupt is disabled.
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Address FFD8: PHY test Bit Bit-Name 7:6 Phy_thd
Data Sheet
R/W Default Description r/w 01 Phy current source test mode 01 normal o.w. test mode 5:4 Phy_sync_len r/w 11 Phy sync. Bit length test mode 00 4 bits 01 6 bits 10 8 bits 11 2 bits 3:0 Resvered r/w 0000 Note : This is a Read-Cleared register, and the flag always reflect the event even if the interrupt is disabled. Address FFD9: DMA CONTROL REGISTER (DMACTR) Bit Bit-Name R/W Default Description 7 DMA_INI rw 0 0 disable. 1 initial DMA controller. 6 DMA_SYNC rw 0 0 async. 1 sync. 5 DMA_CLK rw 0 0 30 Mhz 1 60 Mhz 4 DMA_BUS rw 0 0 16 bits 1 8 bits 3 BURST_MODE rw 0 Select DMA operation mode 0 burst mode 1 non-burst mode 2 DMA_DIR rw 1 Select DMA operation direction 0 Out 1 In 1 DMA_MODE rw 0 Select DMA operation mode 0 quick mode 1 ISA compatible mode 0 DMA_ENABLE rw 0 The MCU uses this bit to enable/disable DMA operation 0 disable 1 enable DMA transfer This bit is auto-cleared when the EOT active or DMA counter down-count From 1 to 0. Address FFDA: DMA COUNTER LOW BYTE REGISTER (DMACLR) Bit Bit-Name R/W Default Description 0 DMAR<7:0> rw 0 DMA operation counter DMAR's low byte register Address FFDB: DMA COUNTER MIDDLE BYTE REGISTER (DMACMR) Bit Bit-Name R/W Default Description 0 DMAR<15:8> rw 0 DMA operation counter DMAR's middle byte register Address FFDC: DMA COUNTER HIGH BYTE REGISTER(DMACHR) Bit Bit-Name R/W Default Description 0 DMAR<23:16> rw 0 DMA operation counter DMAR's high byte register Note: When DMAR countdown from 1 to 0, a terminate-count interrupt is generated. Address FFDD: ENDPOINT SIZE REGISTER (EPSIZE) Bit Bit-Name R/W Default 7 EPB_TEST rw 0 Reserved 3-4 EPB_SIZE rw 000 Select EPB package size Description
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Data Sheet

000 8 byte 001 16 byte 010 32 byte 011 64 byte 100 128 byte 101 256 byte 110 512 byte 111 1024 byte (for Interrupt transfer only) Note that this registers are designed for Bulk and Interrupt transfer in FS, and Interrupt transfer in HS. Its fixed in 512-byte maximum package for Bulk transfer in HS. Reserved Select EPA package size 000 8 byte 001 16 byte 010 32 byte 011 64 byte 100 128 byte 101 256 byte 110 512 byte 111 1024 byte (for Interrupt transfer only) Note that this registers are designed for Bulk and Interrupt transfer in FS, and Interrupt transfer in HS. Its fixed in 512-byte maximum package for Bulk transfer in HS.
3 EPA_TEST 2-0 EPA_SIZE
rw rw
0 000
Address FFDE: TEST1 Bit Bit-Name 7 FFTEST 6 TIMERTEST 5 SETUPDATALOCKEN 4 3 POWERDOWN EPAEOTFORCE
2 1 0
IRQ_OPENDRAIN DRQ_POL IRQ_POL
R/W Default Description r/w 0 FIFO test r/w 0 USB IP timer test mode r/w 0 Setup data lock enable 0 not lock 1 lock enable R/w Power down the DPLL 0 normal operation 1 power down R/w Endpoint A auto force enable when DMA counter down form 1 to 0, or EOT event. 0 disable 1 enable R/w IRQ open drain enable 0 force driving 1 opendrain R/w DRQ polarity 0 active high 1 active low R/w IRQ polarity 0 low active 1 high active
Address FFDF: TEST2 Bit Bit-Name 7 DMAEOT 6 ISODMYEN
R/W Default Description rw 0 For DMA eot test 0 normal 1 dma eot test rw 0 EPA ISO pipe insert dummy bytes enable 0 disable
Page 18
Data Sheet
5:4 ISOHBW
rw
00
3:0 CHIPVERSION
0001
1 enable EPA ISO high bandwidth requirement 0x 1 transfer per uSOF 10 2 transfer per uSOF 11 3 transfer per uSOF Chip version
Address FFE0: Mode Register Bit Bit-Name RW 7 NONE r 6 DMA_PIO rw 5-3 DMA_MODE rw 2-0 PIO_MODE rw
Default Description 0 None 0 1: BULK path use DMA mode / 0: BULK path use PIO mode 111 0~4: UDMA mode 0~4, 7~5: Multiword DMA mode 0~2 000 0~4: PIO mode 0~4
Address FFE1: DMA Control/Status Register Bit Bit-Name RW Default 7 BULK_EN rw 0 6 BULK_DIR rw 0 5 HOST_STOP rw 0 4 FIFO_CLRJ rw 0 3 FRC_EOT rw 0 2 BUF_EMPTY r 1 1-0 NONE r 00
Description 1: BULK DMA access FIFO (BULK path enable) / 0: Bulk path disable 1: BULK out dir / 0: BULK in dir TOP UDMA or PIO, not self cleared, auto set when UDMA, PIO mode Clear FIFO, low active, not self cleared uP force EOT, will check all buffer empty, and self-clear sdram buffer and fifos are empty None
Address FFE2: uP PIO Status Register Bit Bit-Name RW Default Description 7 NONE r 0 NONE 1-0 SUCCESS rw 0 When uP access ATA, use this to signal this PIO command is successed. Address FFE3: ATA Control/Status Register Bit Bit-Name RW Default 7 ATA_RESETJ rw 1 6 DASPJ r x 5 PDIAGJ r x 4 DMARQ r 0 3 IDE_CSEL rw 0 2 ATA_CS_OEJ rw 0 2 ATA_CTL_OEJ rw 0 1-0 SOFT_RSTJ rw 0
Description Reset ATA device ATA bus DASPJ ATA bus PDIAGJ ATA DMA request is asserted IDE_CSEL ATA CSJ output enable ATA DIORJ/DIOWJ output enable All state machine software reset
Address FFE4: DMA counter high Register Bit Bit-Name RW Default Description 7-0 DMAR<23:16> rw 00000000 DMA counter high Register, the unit is BYTE, and decrease 2 each time moving. Only ATA PIO / UDMA is needed to write this register
Address FFE5: DMA counter middle Register, (the unit is BYTE, and decrease 2 each time moving...) Bit Bit-Name RW Default Description 7-0 DMAR<15:8> rw 00000000 DMA counter middle Register, the unit is BYTE, and decrease 2 each time moving. Only ATA PIO / UDMA is needed to write this register Address FFE6: DMA mode counter low Register, (the unit is BYTE, and decrease 2 each time moving...) Bit Bit-Name RW Default Description
Data Sheet
7-0 DMAR<7:0> Address FFE7: Interrupt MASK Bit Bit-Name 7 EOTINT_EN 6 DEVTERM_EN 5 ATAINT_EN 4-2 NONE 1 GPIO2INT_EN 0 NONE rw

00000000 DMA counter low Register, the unit is BYTE, and decrease 2 each time moving. Only ATA PIO / UDMA is needed to write this register
RW rw rw rw rw rw rw
Default 0 0 1 000 0 0
Description EOTINT enable DEVICE terminate interrupt enable ATAINT enable None GPIO bit 2 interrupt enable NONE
Address FFE8: Interrupt FLAG register Bit Bit-Name RW Default 7 EOTINT r 0 6 DEV_TERMINT r 0 5 ATAINT r 0 4 NONE r 000 1 GPIO2_INT r 0 0 NONE r 0 Address FFE9: GPIO_DIR, bit-wise Bit Bit-Name RW 7-0 GPIO_DIR rw Address FFEA: GPIO_DAT Bit Bit-Name 7-0 GPIO_DAT
Description When PIO counter count from 2/1 to 0, trigger this interrupt DEVICE terminate interrupt When ATA interrupt post edge/high level, trigger this interrupt None When GPIO2 was transition, trigger this interrupt NONE
Default Description 00000000 GPIO direction, 0:input only / 1:output enable
RW rw
Default Description 00000000 GPIO Data, when write, it output to GPIO, when read, read for GPIO(not register)
Address FFEB: Misc control register 0, Specialized by ASYNC Reset Bit Bit-Name RW Default Description 7 IFM_DRV_OE rw 0 IFM DRQ, DACKJ, EOT, DBWRJ, DBRDJ Output Enable 6-3 IFM_COUNT rw 0000 IFM master mode timng counter 2 ATA_INT_TYPE rw 1 ATA interrupt type, 0: edge / 1: level 1 EEPROM_EN rw 0 Enable EEPROM hardware 0: GPIO[1:0] as GPIO / 1: GPIO[1:0] as EEPROM SDAT,SCLK 0 IFM_MODE rw 0 IFM master/slave mode, 0: Slave mode / 1: Master mode Address FFEC: Misc control register 1 Bit Bit-Name RW Default 7~3 NONE r 00000 2 IRQ_POL rw 0 1 DRQ_POL rw 0 0 EOT_POL rw 0
Description NONE 0: EXT_IRQ high active, 1: EXI_IRQ low active(include ICE mode) 0: IFM_DRQ high active, 1: IFM_DRQ low active 0: IFM_EOT high active, 1: IFM_EOT low active
Address FFED: Hardware Setting register Bit Bit-Name RW Default 7-0 HWSET r xxxxxxxx Hardware Setting Register
Description
Address FFF0~FFFF: 16 ports ATA register. Note : For detailed description of the ATA register and their related operation details, please refer to standard ATA specifications.

Section 6 : Electrical Characteristics 6.1 Absolute Maximum Ratings
Data Sheet
Absolute maximum ratings are those values beyond which damage to the device may occur. Continuous operation at these limits is not intended and should be limited to those conditions specified under DC electrical characteristics. Unless otherwise specified, all voltages are reference to ground. Table 6-1 Absolute Maximum Ratings Item Supply voltage Operating supply voltage (VDD5) Operating supply voltage (VCC, VDD, USBAVDD) All input and output voltages Storage temperature range (TSTG) Operating temperature (TA) 6.2 DC Characteristics VDD5=5.5 ~ 3.15 V, Vss=0V, unless otherwise specified. These values are measured under static conditions, and not under dynamic condition. Table 6-2 DC Characteristics Symbol Parameter VIL Low level input voltage VIH High Level Input voltage VOL Low level output voltage VOH High level output voltage IIN Input Current IOZ Output tri-state leakage Current IPD Suspend Mode Current
Ratings -0.5V to +7V 4.5V to 5.5V 3.15V to 3.6V -0.5V to VDD+0.5V o o -60 C to 150 C o o 0 C to 70 C
Min -0.5 2.0 2.4
Max 0.8 VDD5+0.5 0.4 1.0 1.0
Units V V V V mA mA mA
Test Conditions
VIN = Vdd or GND VIN = Vdd or GND
Page 21
Data Sheet
Section 7 : Timing Diagram
tras
trdw
trah
ADDR valid
IDEIORJ
IDED<15:0>
trdz
trds
trdh trz
PIO read from device
twas
twrw
twah
ADDR valid
IDEIOWJ
IDED<15:0>
twds
twdh
PIO write to device
tras twas trdw twrw trah twah trds twds trdh twdh trdz trz
PIO timing parameter ADDR setup to IDEIORJ falling ADDR setup to IDEIOWJ falling IDEIORJ pulse width IDEIOWJ pulse width ADDR hold from IDEIORJ rising ADDR hold from IDEIOWJ rising IDEIORJ data setup IDEIOWJ data setup IDEIORJ data hold IDEIOWJ data hold IDEIORJ data access IDEIORJ data disable
min.
typ. 47 126 166 126 124 84 84
max.
20 5 42 38 82 (ns.)
Page 22
Data Sheet
IDEDRQ
tCr tDr
IDEDACKJ
IDEIORJ
IDED<15:0>
tI
tS
tFr
tJr
Multiword DMA read data
IDEDRQ tCw IDEDACKJ tDw
IDEIORJ
IDED<15:0>
tI
tE
tFw
tJw
Multiword DMA write data
tCr tCw tDr tDw tS tE tFr TFw TI TJr TJw
DMA timing parameter Read cycle time Write cycle time IDEIORJ pulse width IDEIOWJ pulse width IDEIORJ data setup IDEIOWJ data access IDEIORJ data hold IDEIOWJ data hold IDEDACKJ to IDEIORJ/IDEIOWJ setup IDEDACKJ from IDEIORJ hold IDEDACKJ from IDEIOWJ hold
min. 210
typ. 420 504 126 126 84
max.
20 5 84 42 210 84
(ns.)
Page 23
Data Sheet
Section 8 : Packaging Information 100-pin TQFP Packaging Dimension
E1
pin 1 indicator
D1
e
A
seating plane
A1
A2
W L1 L
DIM A A1 A2 D D1 E E1 L L1 e W
MIN 1.50 0.05 (0.002) 1.35 (0.053) 15.85 (0.624) 13.90 (0.547) 15.85 (0.624) 13.90 (0.547) 0.45 (0.018) 1.0 0 0.17 (0.007)
o
NOM. 1.40 (0.055) 16.00 (0.630) 14.00 (0.551) 16.00 (0.630) 14.00 (0.551) 0.60 (0.024) 0.50 BSC o 3.5 0.22 (0.009)
MAX 1.60 (0.063) 0.15 1.45 (0.057) 16.15 (0.636) 14.10 (0.555) 16.15 (0.636) 14.10 (0.555) 0.75 (0.030) 1.0 (0.039) 7 0.27 (0.011)
o
Note : 1) Coplanarity is 2.70 mils maximum from the seating plane. 2) Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm per side. 3) Controlling dimension : millimeter (inch).
Page 24

64-pin TQFP Packaging Dimension
Data Sheet
Page 25
Data Sheet
Section 9 : Revision History As listed is the brief history for the ASIC development. VERSION TAPEOUT DATE TAPEOUT LAYERS A 2001, Full layer tapeout
DESCRIPTION
Page 26
Acer Laboratories Inc. --Preliminary, Confidential, Proprietary-M5621 : High-Speed USB2.0 IDE Device Controller Worldwide Distributors and Sales Office
Taiwan Acer Laboratories Inc. 2F, No. 246 NeiHu Road, Sec 1, Taipei 114, Taiwan, R.O.C. Tel: 886 (2) 8752 -2000 Fax: 886 (2) 8752 -1001 Acer Sertek 11-15F, 135, Sec. 2 Chien Kuo North Road, Taipei 10479,Taiwan, R.O.C. Tel: 886 (2) 2501-0055 Fax: 886 (2) 2501- 2521 Arrow / Ally, Inc. 11F, 678, Sec. 4, Pa Teh Road, Taipei, Taiwan, R.O.C. Tel: 886 (2) 2768 - 6399 Fax: 886 (2) 2768 - 6390 Asec International Inc. 4F, 223 Chung Yang Road, Nan Kang, Taipei, Taiwan, R.O.C. Tel: 886 (2) 2786-6677 Fax: 886 (2) 2786 - 5257 Hong Kong Lestina International Ltd. 14/F, Park Tower 15 Austin Road, Tsimshatsui, Hong Kong Tel: 852-2735 -1736 Fax: 852-2730 - 5260 Texny Glorytact (HK) Ltd. Unit M, 6/F, Kaiser Estate Phase 3, 11 Hok Yuen Street, Hunghom, Kowloon, Hong Kong Tel: 852 - 2765 - 0118 Fax: 852 - 2765 - 0557 Singapore Electronic Resources Ltd. 205 Kallang Bahru, # 04-00, Singapore 339341 Tel: 65 - 298 - 0888 Fax: 65 - 298 - 1111 Japan ASCII Corporation 8-1, Inarimae, Tsukuba-shi Ibaraki, 305, Japan Tel: 81 - 298 - 55 - 4004 Fax: 81 - 298 - 55 - 1985 Kanematsu Electronic Comp. Corp. 11F Shin-Ohsaki Kangyo Bldg., 6-4, Ohsaki 1-Chome, Shinagawa-Ku, Tokyo, Japan 141 Tel: 81 (3) 3779 - 7850 Fax: 81 (3) 3779 - 7898 Macnica Inc. Hakusan High-Tech Park, 1-22-2 Hakusan, Midori-Ku, Yokohama City, Japan 226 Tel: 81 (45) 939 - 6116 Fax: 81 (45) 939 - 6117 Technova Inc. 9F Daiichi-Seimei Daini Bldg., 2-14-27, Shin-Yokohama, Kouhoku-ku, Yokohama-Shi, Kanagawa, 222 Tel: 81 (45) 472-7800 Fax: 81 (45) 472-7830 Korea I&C Microsystems Co., Ltd. 801, 8/F, Bethel Bldg., 324-1, Yangjae-Dong, Seocho-Ku, Seoul, Korea Tel: 82 (2) 577 - 9131 Fax: 82 (2) 577 - 9130 Italy EL.CO.MI. SRL Via Cassanese, 27 20090 Segrate - (MI), Italy Tel: 39-2-26927430 Fax: 39-2-26927410 Germany KaMa GmbH Haupstrasse 19, Maxdorf 67133, Germany Tel: 49-62-37-60678 Fax : 49-62-37-59336 Denmark C-88 101 Kokkedai Industripark Kokkedai, Denmark DK-2980 Tel: 45-49-14-48-88 Fax: 45-49-14-48-89
Data Sheet
Page27
--Preliminary, Confidential, Proprietary--Acer Laboratories Inc.
Data Sheet
United Kingdom Sabre Advanced Microelectronics Sussex House, Unit 11, The Pines Trading Estate, Broad Street Guilford, Surrey GU3 3BH, England Tel: 44-1-483-35444 Fax: 44-1-483-35888 France Microel Les Fjords- Inneuble OSLO -19 Ave de Norvege ZA de Courtaboeuf -BP3 Les Ullis, Cedex 91941, France Tel: 33-1-69-07-08-24 Fax: 33-1-69-07-17-23 ALi U. S. Office/European Operations 1830-B Bering Drive San Jose, CA 95112 USA Tel: 1 (408) 467 - 7456 Fax: 1 (408) 467 - 7474
This material is recyclable.
Acer Labs products are not licensed for use in medical applications, including, but not limited to, use in life support devices without proper authorization from medical officers. Buyers are requested to inform ALi sales office when planning to use the products for medical applications. Product names used in this publication are for identification purposes only and may be registered trademarks of their respective companies. Acer Laboratories Inc. makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein. Acer Laboratories Inc. retains the right to make changes to these specifications at any time, without notice. Contact your local sales office to obtain the latest specifications before placing your order. ALi is a registered trademark of Acer Laboratories Incorporated and may only be used to identify ALi products. ACER LABORATORIES INCORPORATED 2001
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Acer Laboratories Inc.

--Preliminary, Confidential, Proprietary--

M5621 : High-Speed USB2.0 IDE Device Controller

M5621 : High-Speed USB2.0 IDE Device Controller

--Preliminary, Confidential, Proprietary--

Acer Laboratories Inc.

M5621 : High-Speed USB2.0 IDE Device Controller

Configurable EndPoint FIFOs

8/16-bit PIO /DMA /IDE Interface

IDE /PIO /DMA Bus

IDE Device or Peripheral ASIC / DCPU

Optional Program ROM

Embedded MCU Engine

GPIOs Optional USB ID EEPROM

1.4 System Application Diagram USB2.0 /1.1 I/F

(1) USB-to-IDE Operating Mode

USB2.0/1.1 Host System

IDE Devices (ATA/ATAPI Interface)

(2) USB Device Operating Mode

USB2.0/1.1 Host System

USB2.0 /1.1 I/F

Peripheral Device ASIC System

(3) Multi-functional Control Operating Mode

USB2.0/1.1 Host System

USB2.0 /1.1 I/F

8/16-bit PIO/DMA or GPIO Control

Peripheral Device ASIC System

Acer Laboratories Inc.

--Preliminary, Confidential, Proprietary--

M5621 : High-Speed USB2.0 IDE Device Controller

--Preliminary, Confidential, Proprietary--

Acer Laboratories Inc.

M5621 : High-Speed USB2.0 IDE Device Controller

Acer Laboratories Inc.

--Preliminary, Confidential, Proprietary--

M5621 : High-Speed USB2.0 IDE Device Controller

--Preliminary, Confidential, Proprietary--

Acer Laboratories Inc.

M5621 : High-Speed USB2.0 IDE Device Controller

ROM address bus

IO4 O4 IO4 IO4 IO4 IO4 IO4 P P P

Acer Laboratories Inc.

--Preliminary, Confidential, Proprietary--

M5621 : High-Speed USB2.0 IDE Device Controller

--Preliminary, Confidential, Proprietary--

Acer Laboratories Inc.

M5621 : High-Speed USB2.0 IDE Device Controller

Acer Laboratories Inc.

--Preliminary, Confidential, Proprietary--

M5621 : High-Speed USB2.0 IDE Device Controller

--Preliminary, Confidential, Proprietary--

Acer Laboratories Inc.

M5621 : High-Speed USB2.0 IDE Device Controller

Acer Laboratories Inc.

--Preliminary, Confidential, Proprietary--

M5621 : High-Speed USB2.0 IDE Device Controller

Description Data write to SDAT bus

Description Data read from SDAT bus

Description SCLK Divider, EEPROM_TIMER*132.8ns

--Preliminary, Confidential, Proprietary--

Acer Laboratories Inc.

M5621 : High-Speed USB2.0 IDE Device Controller

Acer Laboratories Inc.