1) Pan101b

PAN101B
PAN101B
PAN101B CMOS OPTICAL NAVIGATION SENSOR General Description
The PAN101B is a low cost CMOS process optical navigation sensor with DSP integration chip that serves as a non-mechanical motion estimation engine for implementing a computer mouse.
Features
Single 3.0 volt power supply Optical motion estimation technology Complete 2-D motion sensor No mechanical parts
Key Specification
Power Supply Optical Lens Wide operating supply range 2.7V~3.6V 1:1 18.432 MHz 16+ inches/sec 400/800 cpi 3000 frames/sec <15mA @Mouse moving (Normal) < 5mA @Mouse not moving (sleep1) < 2mA @Mouse not moving (sleep2) < 100uA @Shutdown mode Package Shrunk DIP20
Accurate motion estimation over a wide System Clock range of surfaces High speed motion detection up to 16+ Speed inches/sec Resolution High resolution up to 800cpi Shutdown pin for low power dissipation. Power saving mode during times of no movement Serial Interface for programming and data Operating Current transfer I/O pin 5.0 volt tolerance Frame Rate
Ordering Information Order number PAN101BOI-204 PAN101BOI-208 PAN101BSI-204 PAN101BSI-208 I/O Open-drain output Open-drain output CMOS output CMOS output Resolution 400 cpi 800 cpi 400 cpi 800 cpi
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw
V1.4, FEB. 2003
PixArt Imaging Inc. PAN101B CMOS Optical Navigation Sensor
1. Pin Description
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name VSS_LED LED OSCOUT OSCIN VSSD VSSA VDDD VDDA VRB VRT VAY XA NC XB YA NC YB SCLK SDIO PD Type GND I/O OUT IN GND GND PWR PWR BYPASS BYPASS BYPASS Open-drain OUT (PAN101BOI) CMOS OUT (PAN101BSI) Open-drain OUT (PAN101BOI) CMOS OUT (PAN101BSI) Open-drain OUT (PAN101BOI) CMOS OUT (PAN101BSI) Open-drain OUT (PAN101BOI) CMOS OUT (PAN101BSI) IN Open-drain I/O (PAN101BOI) CMOS I/O (PAN101BSI) IN Definition LED ground LED control Resonator output Resonator input Chip digital ground Chip analog ground Chip digital power VDD, 3.0V Chip analog power VDD, 3.0V Analog voltage reference Analog voltage reference Analog voltage reference XA quadrature output No connection XB quadrature output YA quadrature output No connection YB quadrature output Serial interface clock Serial interface bi-direction data Power down pin, active high
20
LB
RB
+Y
20
10
11
10
Figure 1. Top View Pinout
11
+X Figure 2. Top View of Mouse
2 V1.4, FEB. 2003
2. Block Diagram and Operation

LED VSS_LED LED DRIVE POWER ON RESET CMOS IMAGE SENSOR QUADRATURE OUTPUT QUADRATURE OUTPUTS XA XB YA YB VOLTAGE REGULATOR AND POWER CONTROL
VDDD VDDA VSSD VSSA PD
3V POWER
DIGITAL SIGNAL PROCESSOR
VRB VRT VAY
VOLTAGE REFERENCE
SERIAL INTERFACE
SCLK SDIO
SERIAL INTERFACE
CONTROL REGISTER
OSCILLATOR
OSCIN OSCOUT
RESONATOR
Figure 3. Block Diagram

The PAN101B is a low cost CMOS-process optical navigation sensor with DSP integration chip that serves as a non-mechanical motion estimation engine for implementing a computer mouse. It is based on optical navigation technology, which measures changes in position by optically acquiring sequential surface images (frames) and mathematically determining the direction and magnitude of movement. The sensor is in a 20 pin optical package. The output format is two-channel quadrature (X and Y direction), which emulates encoder phototransistors. The current X and Y information are also available in registers accessed via a serial port.
3 V1.4, FEB. 2003
3. Registers and Operation

The PAN101B can be programmed through registers, via the serial port, and DSP configuration and motion data can be read from these registers. All registers not listed are reserved, and should never be written by firmware.
3.1 Registers
Address 0x00 0x01 0x02 0x03 0x04 0x05 Name Product_ID Reserved Motion_Status Delta_X Delta_Y Operation_Mode R/W R R R R R/W Default 0x02 Data Type Eight bits number with the product identifier. Reserved for future. Bit field Eight bits 2s complement number. Eight bits 2s complement number. Bit field
3.2 Register descriptions

0x00 Bit Field Usage 0x01 Bit Field Usage Reserved for future 7 6 5 4 Reserved 7 PID7 6 PID6 5 PID5 Product_ID 4 PID4 3 PID3 2 PID2 1 PID1 0 PID0
The value in this register can not change, it can be used to verify that the serial communications link is OK. Reserved 3 2 1 0
4 V1.4, FEB. 2003
0x02 Bit Field Usage 7 Motion 6 Reserved 5 Reserved
Motion_Status 4 DYOVF 3 DXOVF 2 Reserved 1 Reserved 0 RES
Register 0x02 allows the user to determine if motion has occurred since the last time it was read. If so, then the user should read registers 0x03 and 0x04 to get the accumulated motion. It also tells if the motion buffers have overflowed since the last reading. The current resolution is also shown. Reading this register freezes the Delta_X and Delta_Y register values. Read this register before reading the Delta_X and Delta_Y registers. If Delta_X and Delta_Y are not read before the motion register is read a second time, the data in Delta_X and Delta_Y will be lost.
Notes
Field Name Motion Reserved Reserved DYOVF DXOVF Reserved Reserved RES
Description Motion since last report or PD 0 = No motion (Default) 1 = Motion occurred, data ready for reading in Delta_X and Delta_Y registers Reserved for future Reserved for future Motion Delta Y overflow, Y buffer has overflowed since last report 0 = no overflow (Default) 1 = Overflow has occurred Motion Delta X overflow, X buffer has overflowed since last report 0 = no overflow (Default) 1 = Overflow has occurred Reserved for future Reserved for future Resolution in counts per inch 0 = 800 (Default @ PAN101BXX-208) 1 = 400 (Default @ PAN101BXX-204) Delta_X 6 X6 5 X5 4 X4 3 X3 2 X2 1 X1 0 X0
0x03 Bit Field Usage 0x04 Bit Field Usage 7 Y7 6 Y6 5 Y5 4 Y4 7 X7
X movement is counts since last report. Absolute value is determined by resolution. Reading clears the register. Report range 128~+127. Delta_Y 3 Y3 2 Y2 1 Y1 0 Y0
Y movement is counts since last report. Absolute value is determined by resolution. Reading clears the register. Report range 128~+127.
5 V1.4, FEB. 2003
0x05 Bit Field Usage 7 Reserved 6 XY_enh 5 RES
Operation_Mode 4 Slp_enh 3 Slp2au 2 Slp2mu 1 Slp1mu 0 Wakeup
Register 0x05 allows the user to change the operation of the sensor. Shown below are the bits, their default values, and optional values. Operation_Mode[4:0] 0xxxx=Disable sleep mode 10xxx=Enable sleep mode1 11xxx=Enable sleep mode2 1x100=Force enter sleep23 1x010=Force enter sleep13 1x001=Force wakeup from sleep mode3 Notes: 1. Enable sleep mode, but disable automatic entering sleep2 mode, that is, only 2 modes will be used, normal mode and sleep1 mode. After 1 sec not moving during normal mode, the chip will enter sleep1 mode, and keep on sleep1 mode until moving is detected or wakeup is asserted. 2. Enable sleep mode full function, that is 3 modes will be used, normal mode, sleep1 mode and sleep2 mode. After 1 sec not moving during normal mode, chip will enter sleep1 mode, and keep on sleep1 mode until moving is detected or wakeup is asserted. And after 90 sec not moving during sleep1 mode, the chip will enter sleep2 mode, and keep on sleep2 mode until detect moving or force wakeup to normal mode. Mode Sleep1 Sleep2 Sampling rate @3000frame/sec 30/sec 3/sec Active duty cycle @3000frame/sec 20% 2%
3. Only one of these three bits slp2mu_enh, slp1mu_enh, and wakeup can be set to 1 at the same time, others have to be set to 0. After a period of time, the bits, which was set to 1, will be reset to 0 by internal signal. Notes Field Name
Reserved
Description Reserved for future, Please set Reserved= 0 (Default) XY quadrature output enable/disable 0=disable 1= enable (Default) Resolution in counts per inch 0 = 800 (Default @ PAN101BXX-208) 1 = 400 (Default @ PAN101BXX-204) Sleep mode enable/disable 0 = Disable 1 = Enable (Default) Automatic enter sleep2 mode enable/disable 0 = Disable 1 = Enable (Default) Manual enter sleep2 mode, set 1 will enter sleep2 and this bit will be reset to 0 Manual enter sleep1 mode, set 1 will enter sleep2 and this bit will be reset to 0 Manual wake up from sleep mode, set 1 will enter wakeup and this bit will be reset to 0 6 V1.4, FEB. 2003
XY_enh RES Slp_enh Slp2au Slp2mu Slp1mu Wakeup
4. Specifications
Absolute Maximum Ratings Symbol TSTG TA Parameter Storage temperature Operating Temperature Lead Solder Temp VDD ESD VIN DC input voltage -0.5 DC supply voltage -0.5 Min -40 -15 Max 85 55 260 4.0 2 5.5 Unit C C V kV V All pins, human body model MIL 883 Method 3015 PD, SDIO, SCLK, XA, XB, YA, YB For 10 seconds, 1.6mm below seating plane. Notes
Recommend Operating Condition Symbol Parameter Min. Operating 0 TA Temperature VDD Power supply voltage 2.7 VN FCLK FR SCLK Z S A R Supply noise Clock Frequency Frame Rate Serial Port Clock Frequency Distance from lens reference plane to surface Speed Acceleration Resolution
Typ.
Max. 40
Unit C V mV MHz MHz mm in/sec
Notes
3.0 18.432 3000
3.6 100 24.576 4000 FCLK /4
Peak to peak within 0-100 MHz Set by ceramic resonator
Frames/s 4000Frames/s @ FCLK=24.567MHz
2.1 0
2.2 16
2.3
Refer to Figure 4.
3.9 400 800
g cpi
Package Lid Lens
Z OBJECT SURFACE Figure 4. Distance from Lens Reference Plane to Surface

7 V1.4, FEB. 2003
AC Operating Condition Electrical Characteristics over recommended operating conditions. Typical values at 25 C, VDD =3.0 V Symbol Parameter Min. Typ. Notes Max. Unit tPD tPDW tPUPD tPU tHOLD Power Down PD Pulse Width Power Up from PD Power Up from VDD SDIO read hold time 3 1 42.8 41.7 0.5 From PD. (Refer to Figure 5.) Pulse width to reset the serial interface. us (Refer to Figure 5.) From PD to valid quad signals ms 200usec + 128frames. (Refer to Figure 5.) From VDD to valid quad signals. ms 400usec + 124frames. Minimum hold time for valid data. (Refer to us Figure 14.) After tCOMPUTE, all registers contain valid data from first image after PD. Note that an additional 128 frames for Auto-Exposure ms (AE) stabilization may be required if mouse movement occurred while PD was high. (Refer to Figure 8.) ns Pull-up 10Kohm (PAN101BOI) ns ns ns ns CL = 30pf CL = 30pf (PAN101BSI) (PAN101BSI) Pull-up 10Kohm (PAN101BOI) LED bin:N ; R1=100ohm us
tCOMPUTE
Data delay after PD
tr,tf tr,tf tr,tf
Rise and Fall Times: SDIO Rise and Fall Times: XA, XB, YA, YB Rise and Fall Times: ILED
500, 5 25, 20 500, 5 25, 20 10, 10
8 V1.4, FEB. 2003
DC Electrical Characteristics
Electrical Characteristics over recommended operating conditions. Typical values at 25 C, V DD =3.0 V
Symbol
Parameter
Min.
Typ. 15 5 2 100
Max.
Unit mA XA, XB, YA, YB, SCLK, SDIO = no load mA mA uA PD, SCLK, SDIO = high
Type: PWR Supply Current IDD Mouse moving (Normal) Supply Current IDD Mouse not moving (sleep1) Supply Current IDD Mouse not moving (sleep2) Supply Current IDDPD (Power Down) Type: SCLK, SDIO, PD VIH VIL VOH VOL VIH VIL VOL VOH VOL Input voltage HIGH Input voltage LOW Output voltage HIGH Output voltage LOW Input voltage HIGH Input voltage LOW Output voltage LOW Output voltage HIGH Output voltage LOW 0.8 VDD 2 0.8 VDD 2
0.8 0.2VDD
V V V V @I OH = 3mA (SDIO only) @I OL = 3mA (SDIO only) When driving from an external source When driving from an external source
Type: OSCIN 0.8 150 V
Type: LED mV @I OL = 25mA V 0.2VDD V @I OH = 3mA @I OL = 3mA Type: XA, XB, YA, YB
9 V1.4, FEB. 2003
5. PD Pin Timing
PD IDD tPD 0.5us 200us tCOMPUTE 4ms,min tPUPD 42.8ms 128frames tPDW 1us,min
Figure 5. PD minimum pulse width
PD SCLK SDIO
tPDW 1us,min
1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6
Hi-Z
ADDRESS(R/W)
DATA
Figure 6. Forcing PAN101B SDIO line to the Hi-Z state

tPDW 1us,min PD SCLK SDIO Hi-Z
1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6
ADDRESS(R/W)
DATA
Figure 7. Forcing PAN101B full chip reset and SDIO line to the Hi-Z state
PD SCLK
1 2 3 4 5 6 7 8 9 1 1 0 1 1 2 1 3 1 1 4 5 1 6
tPDW 1us,min
1 2 3 4 5 6 7 8 9 1 1 0 1 1 2 1 3 1 4 1 5 1 6
Address=0x04 SDIO
Data=0xFF
Address=0x02
Data=0x80
tCOMPUTE 4ms,min
Figure 8. Read the motion data from PAN101B

10 V1.4, FEB. 2003
6. Quadrature Mode
The quadrature state of the PAN101B tells mouse controller which direction the mouse is moving in. The output format is two channels quadrature (X and Y direction), which emulates encoder phototransistors. The DSP generates the x and y relative displacement values that are converted into two channel quadrature signals. PAN101B support 400cpi, 800cpi, two types of resolution. The following diagrams show the timing for positive X motion, to the right or positive Y motion, up.
6.1 Quadrature Output Timing

X motion to the right Y motion up XA/YA
FOUR
XB/YB
83.3us
83.3us
83.3us
83.3us
XA/YA
THREE
XB/YB
83.3us
83.3us
166.7us
XA/YA
TWO
XB/YB
83.3us
250us
XA/YA
ONE
XB/YB
333.3us
333.3us @ 3000frames/second
Figure 9. Quadrature Output Timing
11 V1.4, FEB. 2003
6.2 Quadrature Output State Machine

The following state machine shows the states of the quadrature output pins. The three things to note are that state 0 is entered after a power on reset. While the PD pin is asserted, the state machine is halted. Once PD is de-asserted, the state machine picks up from where it left off. During times of mouse no movement will entry power saving mode, until mouse was moved.
PD POWER ON RESET STATE 0 (0,0)
D IR EC -D TI IR O N EC TI O N
N O TI EC N IR O D TI + EC IR -D
X/Y output STATE XA/YA XB/YB 0 PD 1 2 3 0 1 1 1 1 0 0 0
PD
STATE 1 (0,1)
STATE 3 (1,0)
STATE 2 (1,1) PD
Figure 10. State Machine 6.3 Quadrature Output Waveform

The following diagrams show the waveform of the two channel quadrature outputs. If the X, Y is motionless, the (XA, XB), (YA, YB) will keep in final state. Each state change (ex. STATE2 STATE3) is one count.
X MOTION TO THE RIGHT Y MOTION UP ( + DIRECTION )
XA/YA
XB/YB STATE3 (1,0) STATE0 (0,0) STATE1 (0,1) STATE2 (1,1) STATE3 (1,0) STATE0 (0,0)
-D IR EC + TI D O IR N EC TI O N
N O TI EC IR N O -D TI EC IR D
+ 1
+
+ 1
+ 1
+ 1
+ 1
MOTION COUNT
XA/YA
X MOTION TO THE LEFT Y MOTION DOWN ( - DIRECTION )
XB/YB STATE1 (0,1) STATE0 (0,0) STATE3 (1,0) STATE2 (1,1) STATE1 (0,1) STATE0 (0,0)
MOTION COUNT
Figure 11. Quadrature Output Waveform

12 V1.4, FEB. 2003
7. Serial Interface
The synchronous serial port is used to set and read parameters in the PAN101B, and can be used to read out the motion information instead of the quadrature data pins. SCLK: The serial clock line. It is always generated by the host micro-controller. SDIO: The serial data line used for write and read data. PD: A third line is sometimes involved. PD (Power Down pin) is usually used to place the PAN101B in a low power mode to meet USB suspend specification. PD can also be used to force resynchronization between the micro-controller and the PAN101B in case of an error.
7.1 Transmission Protocol

The transmission protocol is a two-wire link, half duplex protocol between the micro-controller and PAN101B. All data changes on SDIO are initiated by the falling edge on SCLK. The host microcontroller always initiates communication; the PAN101B never initiates data transfers. The transmission protocol consists of the two operation modes: - Write Operation. - Read Operation. Both of the two operation modes consist of two bytes. The first byte contains the address (seven bits) and has a bit7 as its MSB to indicate data direction. The second byte contains the data.
FIRST BYTE R /W (1 BIT) ADDRESS (7 BIT) SECOND BYTE DATA (8 BIT)
MSB
LSB
MSB
LSB
Figure 12. Transmission Protocol 7.1.1 Write Operation

A write operation, which means that data is going from the micro-controller to the PAN101B, is always initiated by the micro-controller and consists of two bytes. The first byte contains the address (seven bits) and has a 1 as its MSB to indicate data direction. The second byte contains the data. The transfer is synchronized by SCLK. The micro-controller changes SDIO on falling edges of SCLK. The PAN101B reads SDIO on rising edges of SCLK.
SCLK SDIO
DON'T CARE
1 1
2 A6
3 A5
4 A4
5 A3
6 A2
7 A1
8 A0
9 D7
10 D6
11 D5
12 D4
13 D3
14 D2
15 D1
16 D0
DON'T CARE
SDIO driven by Micro-controller
Figure 13. Write Operation 7.1.2 Read Operation

A read operation, which means that data is going from the PAN101B to the micro-controller, is always initiated by the micro-controller and consists of two bytes. The first byte contains the address, is written by the micro-controller, and has a 0 as its MSB to indicate data direction. The second byte contains the data and is driven by the PAN101B. The transfer is synchronized by SCLK. SDIO is changed on falling edges of SCLK and read on every rising edge of SCLK. The micro-controller must go to a high Z state after the last address data bit. The PAN101B will go to the high Z state after the last data bit.
13 V1.4, FEB. 2003
PixArt Imaging Inc. PAN101B

SCLK SDIO
DON'T CARE
CMOS Optical Navigation Sensor

1 0 2 A6 3 A5 4 A4 5 A3 6 A2 7 8
Hi-z
9 D7
10 D6
11 D5
12 D4
13 D3
14 D2
15 D1
16 D0
Hi-z R/W bit of next address
A1 A0
SDIO driven by Micro-controller Note "A"
SDIO driven by PAN101B Note "B"
Note "A"
SCLK SDIO
1. Micro-controller send address to PAN101B. 2. Micro-controller release and set SDIO to Hi-Z after the last address bit. 7 A1 A0 t HOLD 3us,min 8 Hi-Z 9 D7
Note "B"
1. PAN101B send data to Micro-controller . 2. PAN101B release and set SDIO to Hi-Z after the last data bit. 16 Hi-Z D0
SCLK SDIO
1 R/W bit of next address SDIO driven by micro-controller
Figure 14. Read Operation 7.2 Re-Synchronous Serial Interface

There are times when the SDIO line from the PAN101B should be in the Hi-Z state. If the microprocessor has completed a write to the PAN101B, the SDIO line is Hi-Z, since the SDIO pin is still configured as an input. However, if the last operation from the microprocessor was a read, the PAN101B will hold the D0 state on SDIO until a rising edge of SCLK. To place the SDIO pin into the Hi-Z state, first raise the PD pin, and then toggle the SCLK line from high to low to high. The SDIO line will now be in the Hi-Z state. The PAN101B and the micro-controller might get out of synchronization due to following condition.
7.2.1 USB suspend

Termination of a transmission by the micro-controller may sometimes be required (for example, due to a USB suspend interrupt during a read operation). To accomplish this the micro-controller should raise PD. The PAN101B will not write to any register and will reset the serial port (but nothing else) and be prepared for the beginning of future transmissions after PD goes low.
7.2.2 Firmware flaws error, or others error

The PAN101B and the micro-controller might get out of synchronization due to micro-controller firmware flaws. The PD pin can stay high, with the PAN101B in the shutdown state, or the PD pin can be lowered, returning the PAN101B to normal operation. If the microprocessor and the PAN101B get out of sync, then the data either written or read from the registers will be incorrect. In such a case, an easy way to solve this is to raise PD to re-sync the parts after an incorrect read. The PAN101B will reset the serial port but will not reset the registers and be prepared for the beginning of a new transmission
14 V1.4, FEB. 2003
7.2.3 Power on problem

The problem occurs if the PAN101B powers up before the microprocessor sets the SCLK and SDIO lines to be output.
7.2.4 ESD events

The PAN101B and the micro-controller might get out of synchronization due to ESD events. If the PAN101B and the micro-controller might get out of synchronization due to power on problem or ESD events. An easy way to solve this is to reset PAN101B.
Power on reset to resync PAN101B => Reset full chip and SDIO line set to Hi-Z state)
VDD PD SCLK SDIO Hi-Z
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1us,min
ADDRESS(R/W)
DATA
Figure 15. Power on reset to resync. PAN101B 7.3 Collision detection on SDIO
The only time that the PAN101B drives the SDIO line is during a READ operation. To avoid data collisions, the micro-controller should release SDIO before the falling edge of SCLK after the last address bit. The PAN101B begins to drive SDIO after the next falling edge of SCLK. The PAN101B release SDIO of the rising SCLK edge after the last data bit. The micro-controller can begin driving SDIO any time after that. In order to maintain low power consumption in normal operation or when the PD pin is pulled high, the micro-controller should not leave SDIO floating until the next transmission (although that will not cause any communication difficulties).
7.4 Error detection and recovery

1.The micro-controller can verify success of write operations by issuing a read command to the same address and comparing written data to read data. 2. The micro-controller can verify the synchronization of the serial port by periodically reading the product ID register.
15 V1.4, FEB. 2003
R1
U1
DGND
1 VSS_LED LED OSCOUT OSCIN + VSSD VSSA D+/SCLK 2 3 4 7 VDDD VDDA VPP 9 VRB VRT VAY P0.7 A COM P1.0 P1.1 B 9 XTALIN XTALOUT 10 14 5 15 11 P0.0 1 XA VSS 12 6 7 NC 13 VREG 8 XB D-/SDATA 14 12 13 YA 15 VCC 1 11 NC 16 YB 17 SCLK 18 P0.3 P0.4 4 18 SDIO 19 P0.2 P0.5 3 17 PD P0.1 P0.6 2 3 20 2 16
R2 300K SW1 SW2 SW3 DGND C9 10uF VCC_5V D+/SCLK D-/SDATA GND R6 1.3K C8 0.1uF R M L
U2
PAN101B
D1
C1
LED
4 5
C2
10pF
X1 18.432MHz
VIN PAD
DGND
10pF
JP1
PixArt Imaging Inc.
VIN
GND
VOUT
Q1(AIC1722)
6
DGND AGND C3
8
DGND DGND
3.3V REGULATOR
C7 0.1uF
+
C4
VIN
GND
VOUT
AGND
VRT VAY
C6
AGND
V1.4, FEB. 2003

+

HEADER 4
ENSW1 C5
10
1uF 1uF
10uF
AGND C6 0.1uF
8. Referencing application circuit
PAN101BOI
ENCODER
AGND
DGND AGND
CY7C63723-PC
Figure 16. Application circuit using serial interface with PAN101BOI
R1
U1
DGND
1 VSS_LED LED OSCOUT OSCIN VSSD VSSA VDDD VDDA VRB 11 XA 12 1 5 NC 13 XB 14 YA 15 NC 16 YB 17 SCLK 18 4 SDIO 19 3 P0.2 P0.3 PD P0.1 2 3 4 5 20 2
U2
P0.6 P0.5 P0.4 16 17 18
SW1 SW2 SW3
L M R C8 0.1uF
VCC D+/SCLK 11 13 D-/SDATA VREG VPP 12 8 7 VSS 6
D1
8.1 Recommended typical application using serial interface
C1
LED
C2
10pF
DGND
+
X1 18.432MHz
C9 10uF DGND DGND VCC_5V D+/SCLK D-/SDATA GND R6 1.3K
VIN PAD
DGND DGND
6 7 8 9
10pF
JP1
1 2 3 4
Q1(AIC1722) AGND C3 0.1uF C5

10
3.3V REGULATOR
C7
C4
1uF 1uF
10uF
HEADER 4
ENSW1
P0.0 P0.7 P1.0 P1.1 9 XTALIN XTALOUT 15 14 10 A COM B
0.1uF
PAN101BSI
ENCODER
DGND AGND
CY7C63723-PC
16
Figure 17. Application circuit using serial interface with PAN101BSI
Figure 18. Example printed circuit board layout. (PAN101BOI V.S CY7C63723-PC)
17 V1.4, FEB. 2003
R1
U1 U2
PD 20 5
DGND
1 VSS_LED
PAN101B
D1
2 LED OSCOUT OSCIN + VSSD VSSA D+/SCLK 7 VDDD VDDA VPP 9 VRB XA VAY P0.7 A COM B 15 14 10 11 P0.3 VSS 12 4 6 7 NC 13 VREG 8 XB P0.2 D-/SDATA 14 3 12 13 YA 15 P0.1 2 VCC 11 NC 16 YB 17 P0.0 SCLK 18 SDIO P0.5 19 17 18
VCC_5V SW2 SW3 DGND C9 10uF VCC_5V

1 2 3 4
P1.0 P0.6
16
SW1 M R C8 0.1uF
C1 LED
3
C2
4 5 1
10pF X1 18.432MHz 300K 300K 300K 300K
R2
P0.4
R3
R5
R4
PixArt Imaging Inc.
VIN PAD
DGND
10pF
JP1
VIN
GND
VOUT
Q1(AIC1722)
6
DGND D+/SCLK D-/SDATA GND R6 1.3K AGND C3

8
DGND DGND
3.3V REGULATOR
C7 0.1uF
+
C4
VIN
GND
VOUT
AGND
VRT VAY
C6 AGND
V1.4, FEB. 2003

+ 10 11

HEADER 4
ENSW 1 C5
10 VRT
1uF 1uF
10uF
AGND C6 0.1uF
PAN101BOI
P1.1 9 XTALIN XTALOUT
AGND
ENCODER
DGND AGND
CY7C63723-PC
Figure 19. Application circuit using quadrature output pins with PAN101BOI
8.2 Application circuit using quadrature output pins
R1
U1
DGND
1 VSS_LED PD 20 5
U2
VCC_5V
19 18 17 16 15 14 13 12 4 2 3 VCC P0.1 D+/SCLK P0.2 D-/SDATA VREG VPP 11 13 12 8 7 P0.3 VSS 6 1 P1.0 P0.6 P0.5 P0.4 P0.0 16 17 18
SW1 SW2 SW3
L M R C8 0.1uF DGND
+
D1
2 LED OSCOUT OSCIN VSSD VSSA YA XB NC XA VDDD VDDA VRB NC YB SCLK SDIO
C1 LED
3 4 5
C2
10pF X1 18.432MHz
C9 10uF DGND DGND VCC_5V D+/SCLK D-/SDATA GND R6 1.3K
VIN PAD
DGND DGND
6 7 8 9
10pF
JP1
1 2 3 4
Q1(AIC1722) AGND C3 0.1uF C5 1uF
3.3V REGULATOR
C7
C4
1uF
10uF
HEADER 4
ENSW 1
P0.7 15 14 P1.1 9 XTALIN XTALOUT 10 A COM B
0.1uF
PAN101BSI
ENCODER
DGND AGND
CY7C63723-PC
Figure 20. Application circuit using quadrature output pins with PAN101BSI
18
Figure 21. Example printed circuit board layout. (PAN101BOI V.S CY7C63723-PC)
19 V1.4, FEB. 2003
R1
DGND
1 VSS_LED PD 20
U1
D1 10K 10K 10K 10K
2 LED SDIO 19
PAN101B
R2 R3 R5 R4
LED
3 OSCOUT OSCIN VSSD R 6 VSSA VDDD XB VDD 8 VDDA VRB XA VAY 7 OPT OSCR VSS 8 11 OSC.OUT 2 Z1 B 3 X2 12 COM + 13 Z2 A 4 NC 13 1 14 X1 12 CLK 5 YA Y2 DATA 15 15 6 9 NC 16 M 10 YB 17 Y1 L 14 11 SCLK 18
DGND
DGND
4
C1 10pF SW1 SW2 SW3 DATA CLK ENSW1 C8 0.1uF 10uF C9 VCC_5V GND
1 2 3 4
X1 18.432MHz L M R JP1
5
U2
PixArt Imaging Inc.
VIN PAD
C2 10pF DGND AGND

7
VIN
GND
VOUT
Q1(AIC1722)
3.3V REGULATOR C3 0.1uF

9 +
C7
C4
VIN
GND
VOUT
AGND C6 AGND 0.1uF PAN101BSI
V1.4, FEB. 2003

+ 10 VRT VAY 11

HEADER 4 C5
10 VRT
1uF 1uF ENCODER
10uF
AGND C6 AGND 51K R6 0.1uF PAN101BOI

16
8.3 Typical application for PS/2 interface
EM84510FP
DGND
AGND
Figure 22. Application circuit using PS/2 interface with PAN101BOI
DGND
R1
DGND
1 VSS_LED LED SDIO 19 PD 2 20
U1
D1 LED
3 OSCOUT OSCIN VSSD VSSA YA XB NC XA 12 13 13 2 7 16 Z2 X2 Z1 OSC.OUT OPT OSCR VSS 8 3 B 4 14 VDDD VDDA VRB 15 NC 16 15 12 YB 17 14 Y1 SCLK 4 5 18
DGND
DGND
C1 10pF
X1 18.432MHz
U2
L M R 11 10 9 Y2 X1 VDD DATA CLK 6 5 1
SW1 SW2 SW3
L M R DATA CLK ENSW1

A COM
VIN PAD
C2 10pF DGND
6 7 8 9
Q1(AIC1722) AGND C3 0.1uF C5 1uF
JP1
1 2
3.3V REGULATOR
C7
C4
VCC_5V GND C8 0.1uF ENCODER

+
3 4
1uF
10uF
C9 10uF HEADER 4 R6 51K DGND
EM84510FP
DGND
AGND
igure 23. Application circuit using PS/2 interface with PAN101BSI
20
Figure 24. Example printed circuit board layout. (PAN101BOI V.S EM84510FP)
21 V1.4, FEB. 2003
8.4 PCB layout consideration

1. Caps for pins 9, 10 MUST have trace lengths LESS than 5mm. 2. The ground wires of pin1(VSS_LED), pin5(VSSD), pin6(VSSA) must be separated from PS2/USB connector ground node in PCB layout. 3. VSS_LED and VSSD must have trace lengths less than 100mm, VSSA must have trace lengths less than 80mm, and typical trace width is 30mil. 4. The trace lengths of OSCOUT, OSCIN must less than 6mm. PS2/USB onnector D+/SCLK D-/SDATA VCC GND
DGND DGND
PIN1 (VSS_LED)
PIN5 (VSSD)
PIN6 (VSSA)
AGND
Figure 25. PCB layout consideration 8.5 Recommended value for R1 Radiometric intensity of LED Bin limits (mW/Sr at 20mA)
Bin N P Q R S T Min 14.7 17.7 21.2 25.4 30.5 36.6 Max 17.7 21.2 25.4 30.5 36.6 43.9
Note: Tolerance for each bin will be 15%
@5V:
LED bin R1 value (ohm) N 100 P 100 Q 100 R 120 S 120 T 120
Figure 26. Recommended value for R1

22 V1.4, FEB. 2003
9. Package Information 9.1 Package Outline Drawing

20 19 18 17 16 15 14 13 12 11
10
19.30 0.760
3.20 0.126
9.98 0.393
1.02 0.040
5.08 0.200 0.254 0.010
0.457 0.018
1.778 0.070
1.46 0.0575
5 - 12 14.22 0.560
13.589 0.535 11.938 0.470 1 2 3 4 5 6 7 8
5.715 0.225 4.064 0.160 9 10
5.080 0.200
4.55 0.179 20 19 18 17 16 15 14 13 12 11
NOTES: 1. All dimensions in MM/INCH. 2. All dimensions tolerance: +/- 0.10mm 3. Maxmumflash: +0.2mm
5.56 0.2189
0.800 0.031
Figure 27. Package Outline Drawing

23 V1.4, FEB. 2003
9.2 Recommended PCB Mechanical Cutouts and Spacing

4.064 0.160 2.286 0.090 6.985 0.275 4.445 0.175 1.194 0.047 10.998 0.433 0 ref. 16.942 0.667 27.153 1.069
26.010 1.024
7.544 0.297
0.711 0.028 Optical Center
0 ref.
1.194 0.047 4.445 0.175 6.985 0.275 0.711 0.028
3.251 0.128
7.544 0.297
All Dimensions : mm / inch
Figure 28. Recommended PCB Mechanical Cutouts and Spacing
10. Update history

Version V1.0 V1.1 V1.2 V1.3 V1.4 Update Creation, 1st version 8.4 PCB layout consideration Figure 27. Package Outline Drawing 4. Specifications - DC Electrical Characteristics Figure 27. Package Outline Drawing 3.2 Register descriptions 8.4 PCB layout consideration Figure 25. PCB layout consideration Figure 27. Package Outline Drawing Date 07/02/2002 08/29/2002 10/02/2002 10/14/2002 02/10/2003
24 V1.4, FEB. 2003

1) Pan101b

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PAN101B

PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw

V1.4, FEB. 2003

PixArt Imaging Inc. PAN101B CMOS Optical Navigation Sensor

2 V1.4, FEB. 2003

PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw

PixArt Imaging Inc. PAN101B CMOS Optical Navigation Sensor

2. Block Diagram and Operation

VDDD VDDA VSSD VSSA PD

DIGITAL SIGNAL PROCESSOR

VRB VRT VAY

Figure 3. Block Diagram

3 V1.4, FEB. 2003

PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw

PixArt Imaging Inc. PAN101B CMOS Optical Navigation Sensor

3. Registers and Operation

3.2 Register descriptions

4 V1.4, FEB. 2003

PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw

PixArt Imaging Inc. PAN101B CMOS Optical Navigation Sensor

0x02 Bit Field Usage 7 Motion 6 Reserved 5 Reserved

Motion_Status 4 DYOVF 3 DXOVF 2 Reserved 1 Reserved 0 RES

0x03 Bit Field Usage 0x04 Bit Field Usage 7 Y7 6 Y6 5 Y5 4 Y4 7 X7

5 V1.4, FEB. 2003

PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw

PixArt Imaging Inc. PAN101B CMOS Optical Navigation Sensor

0x05 Bit Field Usage 7 Reserved 6 XY_enh 5 RES

Operation_Mode 4 Slp_enh 3 Slp2au 2 Slp2mu 1 Slp1mu 0 Wakeup

XY_enh RES Slp_enh Slp2au Slp2mu Slp1mu Wakeup

PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw

PixArt Imaging Inc. PAN101B CMOS Optical Navigation Sensor

Unit C V mV MHz MHz mm in/sec

3.0 18.432 3000

3.6 100 24.576 4000 FCLK /4

Peak to peak within 0-100 MHz Set by ceramic resonator

Frames/s 4000Frames/s @ FCLK=24.567MHz

3.9 400 800

Package Lid Lens

Z OBJECT SURFACE Figure 4. Distance from Lens Reference Plane to Surface

7 V1.4, FEB. 2003

PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw

PixArt Imaging Inc. PAN101B CMOS Optical Navigation Sensor

Data delay after PD

tr,tf tr,tf tr,tf

500, 5 25, 20 500, 5 25, 20 10, 10

8 V1.4, FEB. 2003

PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw

PixArt Imaging Inc. PAN101B CMOS Optical Navigation Sensor

Type: OSCIN 0.8 150 V

9 V1.4, FEB. 2003

PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw

PixArt Imaging Inc. PAN101B CMOS Optical Navigation Sensor

Figure 5. PD minimum pulse width

Figure 6. Forcing PAN101B SDIO line to the Hi-Z state

Figure 8. Read the motion data from PAN101B

10 V1.4, FEB. 2003

PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw

PixArt Imaging Inc. PAN101B CMOS Optical Navigation Sensor

6.1 Quadrature Output Timing

Figure 9. Quadrature Output Timing

11 V1.4, FEB. 2003

PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw

PixArt Imaging Inc. PAN101B CMOS Optical Navigation Sensor