Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
- I
o
)(1 -)I
s
(3)
Figure 9. Interval 1and 3: Q1 and Q2 are OFF, body diode of Q2
conducting
Figure 10. Interval 2: Q1 ON, body diode of Q2 conducting
Figure 11. Interval 4: Q1 OFF and Q2 ON
D. Detailed Positive Half-Cycle Operation and Analysis for
D < 0.5
The three unique operating interval circuits of the
proposed converter are given in Fig. 9 to Fig. 11 for duty
cycles smaller than 0.5 during the positive half-cycle. The
waveforms of the proposed converter during these conditions
are shown in Fig. 12. The intervals of operation are
explained as follows.
Figure 12. Phase shifted semi-bridgeless boost converter steady-state
waveforms at D < 0.5
Interval 1 [t
0
-t
1
]: At t
0
, Q1/ Q2 are off, as shown in Fig.9.
During this interval, the energy stored in L1 and L2 are
released to the output through L1, D1, body diode of Q2 and
L2. The ripple currents in D1 and body diode of Q2 are the
same as the ripple currents in L1 and L2:
I
In
=
1
L
1
+L
2
(:
- I
o
)(
1
2
- B)T
s
(4)
Interval 2 [t
1
-t
2
]: At t
1
, Q1 is on and Q2 is off, as shown
in Fig.10. During this interval, the current in series
inductances L1 and L2 continues to increase linearly and
store the energy in these inductors. The energy stored in Co
provides energy to the load. The ripple currents in Q1 and
the body diode of Q2 are the same as the current in series
inductances L1 and L2, where the ripple current is given by:
I
In
=
1
L
1
+L
2
v
I
BT
s
(5)
Interval 3 [t
2
-t
3
]: At t
2
, Q1/Q2 are off again, and interval
1 is repeated, as shown in Fig. 9. During this interval, the
current in series inductances L1 and L2 increases linearly
and stores the energy in these inductors. The ripple currents
in D1 and body diode of Q2 are the same as the ripple
current in series inductances L1 and L2, as shown in
equation (1).
Interval 4 [t
3
-t
4
]: At t
3
, Q1 is off and Q2 is on, as shown I
Fig. 11. During this interval, the energy stored in L1 and L2
is released to the output through L1, D1, Q2 and L2. The
ripple currents in D1 and Q2 are the same as the ripple
currents in L1 and L2:
I
n
=
1
L
1
+L
2
(:
- I
o
)I
s
(6)
The operation of converter during the negative input
voltage half-cycle is similar to the operation of converter
during the positive input voltage half-cycle.
IV. LOSS EVALUATION
The estimated loss distribution of the semiconductors is
provided in Fig. 13 at 70 kHz switching frequency, 240V
input and 3300W load for benchmark conventional boost and
interleaved boost converters and the proposed phase shifted
semi-bridgeless boost converter. The currents in regular
diodes Da and Db were assumed to be split with the current
going through intrinsic body diodes for phase shifted semi-
bridgeless topology. The regular diodes in input bridge
rectifiers have the largest share of losses among the
topologies with the input bridge rectifier. The phase shifted
semi-bridgeless topology nearly eliminates this large loss
component (~30W). However, the tradeoff is that the FET
losses are higher and the intrinsic body diodes of FETs
conduct, producing new losses (~8W). The fast diodes in the
conventional and interleaved PFC have slightly lower power
losses, since the boost RMS current is higher in these
topologies.
Figure 13. Comparison of the estimated loss distribution in the
semiconductors at 70kHz switching frequency, 240V input, 3300W load at
400V
Overall the FETs are under slightly more stress in phase
shifted semi-bridgeless topology, but the total loss for the
proposed phase shifted semi-bridgeless boost are 17% lower
than the benchmark conventional boost and 7% lower than
the interleaved boost . Since the benchmark converter bridge
rectifier losses are large, it is expected that phase shifted
semi-bridgeless boost converter should have the lowest
losses among the topologies investigated. Additionally, it is
noted that the losses in the input bridge rectifiers are 63% of
total losses in the conventional PFC converter and 71% of
total losses in the interleaved PFC converter. Therefore,
eliminating the input bridge in PFC converters is justified
despite that the introduction of new losses.
V. EXPERIMENTAL RESULTS
Prototypes of a phase shifted bridgeless boost converter
and an interleaved boost converter were built to verify the
proof-of-concept and analytical work presented in this paper
and to benchmark the proposed converter. The devices used
in experimental prototypes are provided in Table 1.
TABLE I. DEVICES/COMPONENTS USED IN EXPERIMENTAL PROTOTYPES
Topology
Components Used in Prototype Unit Head
Device Part # / Value # of Devices
P
h
a
s
e
S
h
i
f
t
e
d
S
e
m
i
-
b
r
i
d
g
e
l
e
s
s
P
F
C
c
o
n
v
e
r
t
e
r
Regular Diode
25ETS08S 2
Fast Diode
IDB06S60C 2
MOSFET
IPB60R099CP 2
Inductors
400 H 2
I
n
t
e
r
l
e
a
v
e
d
P
F
C
c
o
n
v
e
r
t
e
r
Regular Diode
25ETS08S 4
Fast Diode
IDB06S60C 2
MOSFET
IPB60R099CP 2
Inductors
400 H 2
Pictures of the proposed phase shifted bridgeless boost
prototype are provided in Fig. 14. It consists of a control
board, a capacitor bank of 820 F and an IMS power board
attached to a heatsink with the PFC inductors.
Figure 14. Top: control board, Bottom: power board
3
0
.
0
W
6
.
9
W
1
0
.
8
W
0
.
0
W
4
7
.
7
W
3
0
.
0
W
6
.
9
W
5
.
4
W
0
.
0
W
4
2
.
3
W
4
.
1
9
.
8
2
1
.
6
4
.
1
3
9
.
4
0
10
20
30
40
50
60
R
e
g
u
l
a
r
D
i
o
d
e
s
F
a
s
t
D
i
o
d
e
s
F
E
T
s
I
n
t
r
i
n
s
i
c
B
o
d
y
D
i
o
d
e
s
T
o
t
a
l
L
o
s
s
e
s
P
o
w
e
r
L
o
s
s
e
s
(
W
)
Semiconductor Losses
Conventional Boost
Interleaved Boost
Phase Shifted Semi-Bridgeless Boost
The experimental efficiency of the phase shifted
bridgeless boost converter and benchmark interleaved boost
converter is provided in Fig. 15 for 240V input and Fig. 17
for 120V input at 70 kHz switching frequency and 400 V
output. Loss reduction curves as a function of output power
are provided in Fig. 16 and Fig. 18 for 240V and 120V input,
respectively.
Figure 15. Efficiency as a function of output power at Vin = 240V,
Vo=400V and 70kHz switching frequency
Figure 16. Loss reduction as a function of output power at Vin = 240V,
Vo=400V and 70kHz switching frequency
Figure 17. Efficiency as a function of output power at Vin = 120V,
Vo=400V and 70kHz switching frequency
Figure 18. Loss reduction as a function of output power at Vin = 120V,
Vo=400V and 70kHz switching frequency
From the results, it is noted that proposed semi-bridgeless
PFC converter achieves a peak efficiency of 98.6% at 1 kW
output power. Additionally, the light load efficiency of the
proposed converter is significantly better than that of the
interleaved PFC due to the absence of input bridge rectifier.
However, as the load increases, the efficiency drops due to
additional heat dissipation in the intrinsic body diodes of the
FETs.
Figure 19. THD as a function of output power at Vin = 120 V and 240V,
Vo=400V and 70kHz switching frequency
Figure 20. Power Factor as a function of output power at Vin = 120 V and
240V, Vo=400V and 70kHz switching frequency
94
95
96
97
98
99
100
0
5
0
0
1
0
0
0
1
5
0
0
2
0
0
0
2
5
0
0
3
0
0
0
3
5
0
0
E
f
f
i
c
i
e
n
c
y
(
%
)
Output Power (W)
Interleaved PFC Converter
Phase Shifted Semi-
Bridgeless PFC Converter
0
10
20
30
40
50
60
70
0
5
0
0
1
0
0
0
1
5
0
0
2
0
0
0
2
5
0
0
3
0
0
0
3
5
0
0
L
o
s
s
R
e
d
u
c
t
i
o
n
(
%
)
Output Power (W)
Loss Reduction for PFC
Converters at Vin = 240 V
91
92
93
94
95
96
97
98
0
2
0
0
4
0
0
6
0
0
8
0
0
1
0
0
0
1
2
0
0
1
4
0
0
1
6
0
0
1
8
0
0
E
f
f
i
c
i
e
n
c
y
(
%
)
Output Power (W)
Interleaved PFC Converter
Phase Shifted Semi-
Bridgeless PFC Converter
0
10
20
30
40
50
60
70
0
2
0
0
4
0
0
6
0
0
8
0
0
1
0
0
0
1
2
0
0
1
4
0
0
1
6
0
0
1
8
0
0
L
o
s
s
R
e
d
u
c
t
i
o
n
(
%
)
Output Power (W)
Loss Reduction for PFC
Converters at Vin = 120 V
0
5
10
15
20
25
30
35
40
45
0
5
0
0
1
0
0
0
1
5
0
0
2
0
0
0
2
5
0
0
3
0
0
0
3
5
0
0
T
H
D
(
%
)
Output Power (W)
Vin=240
Vin=120
0.84
0.86
0.88
0.9
0.92
0.94
0.96
0.98
1
1.02
0
5
0
0
1
0
0
0
1
5
0
0
2
0
0
0
2
5
0
0
3
0
0
0
3
5
0
0
P
o
w
e
r
f
a
c
t
o
r
Output Power (W)
Vin=240
Vin=120
Figure 21. Harmonics orders at Vin = 120 V and 240V, compared against
EN61000-3-2 standard.
In order to verify the quality of the input current, the input
current THD is shown in Fig.19. The power factor and
harmonic orders are given and compared with EN 61000-3-2
standard in Fig.20 and 21. It is noted that mains current THD
is less than 5% from 50% load to full load and it is compliant
to IEC 6100-3-2 (Fig. 19 and Fig. 21). The converter power
factor is shown over entire load range for 120 and 240V
input in Fig. 20. The power factor is greater than 0.99 from
50% load to full load.
Experimental waveforms from the proposed converter
prototype are provided in Fig. 22 through Fig. 26. The input
current, input voltage and output voltage are given in Fig. 22.
As it can be seen, the input current is in phase with the input
voltage and has a sinusoidal shape. Additionally, there is a
low frequency ripple on output voltage, which is inversely
proportional to the value of PFC bus output capacitors.
In Fig. 23, the inductor current is provided in addition to
the above mentioned waveforms from Fig. 22. It is noted that
during the positive half-cycle, the inductor current is the
same as input current. However, during the negative half-
cycle, the input current is partially flowing through slow
diodes, Da and Db.
Figure 22. Inut current, input voltage and output voltage.
Ch1= Vo 100V/div. Ch2= Vin 100V/div. Ch4= Iin 10A/div.
Figure 23. Inut current, inducotr current, input voltage and output voltage.
Ch1= Vo 100V/div. Ch2= Vin 100V/div. Ch3= IL1 10A/div. Ch4= Iin
10A/div.
Figure 24. Inductor current, input current and sensed FET current.
Ch1= Sensed IQ1 2V/div. Ch3= IL1 / IDb 10A/div. Ch4= Iin 10A/div
Figure 25. Gating signal, Inductor and sensed FET current for D < 0.5
Ch1= Vg 10V/div. Ch2= IQ1 2V/div. Ch3= IL1 10A/div
In Fig.24 the inductor current, input current and current
sensed in the FET through a current transformer are given.
0
0.5
1
1.5
2
2.5
3579
1
1
1
3
1
5
1
7
1
9
2
1
2
3
2
5
2
7
2
9
3
1
3
3
3
5
3
7
3
9
A
m
p
l
i
t
u
d
e
(
A
)
Harmonics Order
EN 61000-3-2 Class D Limits (A)
Amplitude (A) Vin = 120 V
Amplitude (A) Vin = 240 V
Input Voltage
Output Voltage
Input Current
Input Voltage
Output Voltage
Input Current
Inductor
Current
Input
Current Inductor
Current
Sensed FET Current
Inductor Current
Gating Signal
Sensed FET
Current
The gating signals, sensed FET current and the inductor
current are provided for duty cycles less than 0.5, Fig 25, and
greater than 0.5, Fig. 26. These waveforms match the
theoretical models.
Figure 26. Gating signal, Inductor and sensed FET current for D > 0.5
Ch1= Vg 10V/div. Ch2= IQ1 2V/div. Ch3= IL1 10A/div
VI. CONCLUSIONS
A new high performance phase shifted semi-bridgeless
AC-DC Boost converter topology has been presented in this
paper for the front-end AC-DC converter in PHEV battery
chargers. The proposed converter features high efficiency at
light loads and low lines, which is critical to minimize the
charger size, charging time and the amount and cost of
electricity drawn from the utility; the component count,
which reduces the charger cost; and reduced EMI. The
converter is ideally suited for automotive level I residential
charging applications in North America where the typical
supply is limited to 120V and 1.44kVA.
An analysis and performance characteristics are presented.
A breadboard converter circuit has been built to verify the
proof-of-concept. The theoretical waveforms were compared
with the results taken from prototype unit. Additionally, key
experimental waveforms were provided and input current
harmonics at each harmonic order were compared more
explicitly with the IEC 6100-3-2 standard limits.
Experimental results demonstrate that the mains current
THD is smaller than 5% from 50% load to full load and the
converter is compliant with the IEC 6100-3-2 standard. The
converter power factor was also provided for full power
range at 120 and 240V input. The power factor is greater
than 0.99 from 50% load to full load. The proposed
converter achieves a peak efficiency of 98.6 % at 240 V
input and 1 kW output power.
REFERENCES
[1] Young-Joo Lee; Khaligh, A.; Emadi, A.; "Advanced Integrated
Bidirectional AC-DC and DC-DC Converter for Plug-In Hybrid
Electric Vehicles," IEEE Trans. on Vehicular Technology, vol. 58,
pp. 3970 - 3980 2009.
[2] K. Morrow, D. Karner, and J. Francfort, "Plug-in Hybrid Electric
Vehicle Charging Infrastructure Review," U.S. Departent of Energy -
Vehicle Technologies Program, 2008.
[3] Petersen, L.; Andersen, M.; "Two-Stage Power Factor Corrected
Power Supplies: The Low Component-Stress Approach " in Proc.
IEEE Applied Power Electronics Conference and Exposition, APEC.
vol. 2, 2002, pp. 1195 - 1201.
[4] Singh, B.; Singh, B.N.; Chandra, A.; Al-Haddad, K.; Pandey, A.;
Kothari, D.P.; "A Review of Single-Phase Improved Power Quality
AC-DC Converters," IEEE Trans. on Industrial Electronics, vol. 50,
pp. 962 - 981, 2003.
[5] Dehong Xu; Jindong Zhang; Weiyun Chen; Jinjun Lin; Lee, F.C.;
"Evaluation of output filter capacitor current ripples in single phase
PFC converters " in Proc. IEEE Power Conversion Conference, PCC.
vol. 3 Osaka, Japan, 2002, pp. 1226 - 1231.
[6] Lu, B.; Brown, R.; Soldano, M.; "Bridgeless PFC implementation
using one cycle control technique," in Proc. IEEE Applied Power
Electronics Conference and Exposition, APEC, vol. 2, 2005, pp. 812 -
817.
[7] Petrea, C.; Lucanu, M.; "Bridgeless Power Factor Correction
Converter Working at High Load Variations," in Proc. International
Symposium on Signals, Circuits and Systems, ISSCS. vol. 2, 2007, pp.
1 - 4
[8] U. Moriconi, "A Bridgeless PFC Configuration based on L4981 PFC
Controller ": STMicroelectronics Application Note AN1606, 2002.
[9] J. M. Hancock, "Bridgeless PFC Boosts Low-Line Efficiency,"
Infineon Technologies, 2008.
[10] Yungtaek Jang; Jovanovic, M.M.; Dillman, D.L.; "Bridgeless PFC
boost rectifier with optimized magnetic utilization," in Proc. IEEE
Applied Power Electronics Conference and Exposition, APEC, 2008,
pp. 1017 1021.
[11] Yungtaek Jang; Jovanovic, M.M.; "A Bridgeless PFC Boost Rectifier
With Optimized Magnetic Utilization," IEEE Trans. on Power
Electronics, vol. 24, pp. 85 - 93 2009.
[12] Woo-Young Choi; Jung-Min Kwon; Eung-Ho Kim; Jong-Jae Lee;
Bong-Hwan Kwon; "Bridgeless Boost Rectifier With Low
Conduction Losses and Reduced Diode Reverse-Recovery Problems,"
IEEE Trans. on Industrial Electronics, vol. 54, pp. 769 780, April
2007.
[13] Huber, L.; Yungtaek Jang; Jovanovic, M.M.; "Performance
Evaluation of Bridgeless PFC Boost Rectifiers," IEEE Trans. on
Power Electronics, vol. 23, pp. 1381 - 1390 2008.
[14] Pengju Kong; Shuo Wang; Lee, F.C.; "Common Mode EMI Noise
Suppression for Bridgeless PFC Converters," IEEE Trans. on Power
Electronics, vol. 23, pp. 291 297, January 2008 2008.
[15] Baur, T.; Reddig, M.; Schlenk, M.; "Line-conducted EMI-behaviour
of a High Efficient PFC-stage without input rectification," Infineon
Technology Application Note, 2006.
[16] Frank, W.; Reddig, M.; Schlenk, M.; "New control methods for
rectifier-less PFC-stages," in Proc. EEE International Symposium on
Industrial Electronics. vol. 2, 2005, pp. 489 - 493
[17] M. OLoughlin;, "An Interleaved PFC Preregulator for High-Power
Converters." vol. Topic 5: Texas Instrument Power Supply Design
Seminar, 2007, pp. 5-1, 5-14.
[18] Yungtaek Jang; Jovanovic, M.M.; "Interleaved Boost Converter With
Intrinsic Voltage-Doubler Characteristic for Universal-Line PFC
Front End," IEEE Trans. on Power Electronics, vol. 22, pp. 1394
1401, July 2007.
[19] Balogh, L.; Redl, R.; "Power-factor correction with interleaved boost
converters in continuous-inductor-current mode," in Proc. IEEE
Applied Power Electronics Conference and Exposition, 1993, pp. 168
- 174.
Inductor Current
Gating Signal
Sensed FET Current