1 Introduction

TheUniversalVerificationMethodology(UVM)isastandardizedhybridmethodologyforverifyingcomplexdesigninthesemiconductor industry.IthassupersededtheOpenVerificationMethodologywhichwasanOpenSourceverificationmethodologywassupportedbyboth CadenceandMentor.UVMhasfullindustrywidesupportandstandardisedundertheAccelleraSystemsInitiative. InthispaperTVSdescribesindetailthedifferencesbetweentheOpenVerificationMethodology(version2.1.2)andtheUniversalVerification Methodology(version1.b).ItisintendedtohelpengineerstounderstandtheimplicationsofmovingfromOVMtoUVM. ThepaperstartswithashorthistoryofOVMandUVMtosetthecontext.Adetailedcomparisonthenfollowslookingatphases,managingthe endoftest,componentconfigurationandfinallyregistermodeling.

AbouttheAuthors:
SureshBabuhasbeeninvolvedinhardwareverificationfor10years.Currentlyheisaprojectlead@TVSwithresponsibilityforOVM,UVM andeRMBasedtestbenchandVIPdevelopment,customersupportandmetricdrivenbasedverificationsignoffusingasureSign. Dr.MikeBartleyfoundedTVSin2008afterspendingover20yearsworkinginbothhardwareverificationandsoftwaretesting.

AboutTestandVerificationSolutions
TVS delivers tailored solutions for hardware verification and software testing. TVS is an independent company providing both services and products(VIP&asureSign)fromofficesaroundtheworld.TVSpridesitselfonhavingtheflexibilitytomeetdiverseclientrequirements. Tolearnmoreaboutourofferings,visitwww.testandverification.comorwritetousatinfo@testandverification.com

2 OverviewofUVMHistory
UVMisbuiltonSystemVerilogandthehistoryofthatlanguageisshowninFigure1:HistoryofSystemVerilogbelow. 1980 1990 2000 2005

HiLo

Verilog SuperLog VHDL Vera System Verilog

C e
Figure1:HistoryofSystemVerilog

VerificationmethodologiescameintoexistencesoonafterthefirstdedicatedHVLs(HardwareVerificationLanguages)appeared(see.Themain advantagesofadoptingamethodology(suchasUVM)are ReusabilitythroughtestbenchreuseandverificationIPallowingplugandplay Aprovenmethodologywithindustrywidesupportandavailabilityofengineerswithexistingknowledge/experience Simulatorandvendorindependence

Vera

RVM VMM VMM 1.2 OVM UVM

System Verilog

AVM URM

OpenSource

eRM

Figure2:HistoryofVerificationMethodologies

2.1 OVMandUVMAvailability
Thefollowingreleasesareavailableinhttp://verificationacademy.com/verificationmethodology UVM1.1b(tar.gz)Accellera UVM1.1bUserGuideAccellera UVM1.1a(tar.gz)Accellera UVM1.0(tar.gz)Accellera OVM2.1.2(.zip) OVM2.1.2(tar.gz) UVMRegisterKitforOVM2.1.2(tar.gz) OVM<>VMMreferencelibrary,examplesanddocumentation

3 OVMPhasesvs.UVMPhases
InthissectionwelookatthemainchangesinthewayphasesarehandledinUVM.Thereare2changesinthemethods(seesection3.1)and changesintheactualnumbersofphases(seesection3.2).Notethatasthesechangesaresignificantandnotbackwardscompatiblethenthereis awaytoinvokeOVMstylesemantics. Ifyouadd+UVM_USE_OVM_RUN_SEMANTICinthecommandlineitwillcausetherunphasetouseoldOVMstylerunsemantics.

3.1 Changesinphasemethods
Thereare2changesintheinterfacetothephasemethods.ThesearesummarisedbelowwiththedetailinTable1:Summaryofthechangesin phasemethods. 1. Methodnamechangedinto<phase_name>_phase. 2. Argumentaddedinallthephasemethods. OVM classxbus_envextendsovm_env; //VirtualInterfacevariable protectedvirtualinterfacexbus_ifxi0; functionvoidbuild(); stringinst_name; super.build(); if(has_bus_monitor==1)begin bus_monitor=xbus_bus_monitor::type_id::create("bus_monitor", this); end Endfunction:build UVM classubus_envextendsuvm_env; //VirtualInterfacevariable protectedvirtualinterfaceubus_ifvif; functionvoidbuild_phase(uvm_phasephase); stringinst_name; super.build_phase(phase); if(!uvm_config_db#(virtualubus_if)::get(this,"","vif",vif)) `uvm_fatal("NOVIF",{"virtualinterfacemustbesetfor: ",get_full_name(),".vif"}); Endfunction:build_phase

 //implementruntask taskrun; fork update_vif_enables(); join endtask:run functionvoidend_of_elaboration(); $display("%0t:%0s:end_of_elaboration",$time,get_full_name()); endfunction functionvoidstart_of_simulation(); $display("%0t:%0s:start_of_simulation",$time,get_full_name()); endfunction functionvoidextract(); $display("%0t:%0s:extract",$time,get_full_name()); endfunction functionvoidcheck(); $display("%0t:%0s:check",$time,get_full_name()); endfunction functionvoidreport(); $display("%0t:%0s:report",$time,get_full_name()); Endfunction
Table1:Summaryofthechangesinphasemethods

//implementruntask taskrun_phase(uvm_phasephase); fork update_vif_enables(); join endtask:run_phase functionvoidend_of_elaboration_phase(uvm_phasephase); $display("%0t:%0s:end_of_elaboration",$time,get_full_name()); endfunction functionvoidstart_of_simulation_phase(uvm_phasephase); $display("%0t:%0s:start_of_simulation",$time,get_full_name()); endfunction functionvoidextract_phase(uvm_phasephase); $display("%0t:%0s:extract",$time,get_full_name()); endfunction functionvoidcheck_phase(uvm_phasephase); $display("%0t:%0s:check",$time,get_full_name()); endfunction

3.2 AdditionalphasesinUVM
UVMsawtheintroductionofalargenumberofnewphasestogivefinercontroloverthesimulation.ThesearesummarisedinError!Reference sourcenotfound.below.

 OVM UVM

Table2:AdditionalphasesinUVM

4 ManagingtheEndofTest
Moderntestbenchesprovideawayforcomponentsandobjectstosynchronizetheirtestingactivityandindicateitissafetoendthephaseand thesimulation.UVM(andOVM)providesabuiltinobjectionforeachphasewhichallowsacomponenttoobjecttothephaseending.This objectionmechanismgivesastructuredwayforhierarchicaltestbenchcomponentsstatustocommunicatetheirstatus.Forexample,a componentmayraiseanobjectionwhenitstartsatransactionwiththeDUT(DesignUnderTest)andnotdropthatobjectionunderthe transactioniscomplete.OracomponentexpectingaresponsefromtheDUTwillkeepanobjectionraiseduntiltheresponseisreceived. Notethattheuvm_test_doneobjectionalsoworksinUVM,butitisnottherecommendedwayofmanagingtheendoftest.InUVMitis recommendedtousetheavailabletimeconsumingphases,sousingaglobalvariableisnolongerarobustmechanism. InOVM,callingglobal_stop_requestwasnotrecommendedbutitwasnotdeprecated. OVM
task run(); seq.start( m_virtual_sequencer ); global_stop_request(); endtask

UVM
task run_phase( uvm_phase phase ); phase.raise_objection( this ); seq.start( m_virtual_sequencer ); phase.lower_objection( this ); endtask

task run(); ovm_test_done.raise_objection(); seq.start( m_virtual_sequencer ); ovm_test_done.drop_objection(); endtask task run_phase( uvm_phase phase ); phase.raise_objection( this , "started sequence" ); seq.start( m_virtual_sequencer ); phase.drop_objection( this , "finished sequence"); endtask Table3:ComparingendoftestinOVMandUVM

5 ConfiguringComponent
InUVMitisrecommendedtouseuvm_config_dbmethodforconfiguringcomponents.OVMusedthe[set,get]_config_[int,string,object] methodsforconfiguringcomponents.TheUVMequivalentsofthesemethodsareavailable,butnotrecommended. Theuvm_config_dbisparameterizedbythetypeofobjectthatisbeingconfigured. OVM
class my_env extends ovm_env; ... function void build(); ahb_cfg = ahb_config::type_id::create("ahb_cfg"); ahb_cfg.width = 16; // set additional fields set_config_object("*","ahb_cfg",ahb_cfg); endfunction ... endclass class my_ahb_agent extends ovm_component; ... function void build(); ovm_object cfg; ahb_config my_cfg; assert(get_config_object("ahb_cfg",cfg,0); if (!$cast(my_cfg, cfg)) ovm_report_error(...); ... endfunction ... endclass

UVM
class my_env extends uvm_env; ... function void build(); ahb_cfg = ahb_config::type_id::create("ahb_cfg"); ahb_cfg.width = 16; // set additional fields uvm_config_db#(ahb_config)::set( this,"ahb_agent","ahb_cfg",ahb_cfg); endfunction ... endclass class my_ahb_agent extends uvm_component; ... function void build(); ahb_config my_cfg; if (!uvm_config_db::ahb_config::get( this,"","ahb_cfg",my_cfg); `uvm_error(...) ... endfunction ... endclass

Table4:ConfiguringcomponentsinOVMandUVM

Itisrecommendedtoavoidusingassign_vifunctionthattakesavirtualinterfacehandleasanargumentandcallsanequivalentfunctionon oneormorechildcomponent.Thisisrepeateddownuntilthelastcomponentreached. Followingapproachisnotrecommended

XBUS ENV

function void assign_vi(virtual interface xbus_if xi); xi0 = xi; if( bus_monitor != null) begin bus_monitor.assign_vi(xi); end for(int i = 0; i < num_masters; i++) begin masters[i].assign_vi(xi); end for(int i = 0; i < num_slaves; i++) begin slaves[i].assign_vi(xi); end endfunction : assign_vi

AGENT function void assign_vi(virtual interface xbus_if xmi); monitor.assign_vi(xmi); if (is_active == UVM_ACTIVE) begin sequencer.assign_vi(xmi); driver.assign_vi(xmi); end endfunction : assign_vi Table5:Avoidusingassign_vi

6 UVMRegisterlayer
ConstrainedrandomtestbenchesarerequiredtomodeltheDUTbehaviourtopredictexpectedbehaviours.Thisincludesmodelsofthe registersand/ormemorieswithintheDUT.TheUVMprovidesregisterlayerclassestocreateahighlevel,objectorientedmodelformemory mappedregistersandmemoriesinadesignunderverification.Thefollowingmethodologyfeaturesarekeytobuildingandusingsuchamodel. CreateanabstractmodeloftheregistersandmemoriesinDUT o TomaintainamirroroftheDUTregisters. CreateahierarchythatisanalogoustotheDUThierarchy o RegisterBlock o RegisterFile o Memory o Register o Field ProvideaccesstotheregisterthroughadefinedAPI o Addressindependentinstance/stringnames Modeltheaddressmap o Modelaccessviaspecificinterface

Figure3oppositeshowsthestepsinvolvedinusingtheregister model.

Figure3:Thestepsinvolvedinusingtheregistermodel

6.1 AccessAPI
Table6:RegisteraccessAPIbelowgivesanoverviewoftheregisteraccessAPIandhowitshouldbeused. Command Read()/Write() Description

GeneratePhysicalReadfromtheDUT GeneratephysicalWritetotheDUT Peek()/poke()

Peek()orpoke()methodsRead/writedirectlytotheregister Get()/set()

Get()orset()methodsread/writedirectlytothedesiredvalue

Update()

Update()theDUTwithdesiredvalueinthemodel Mirror()

ReadtheDUTregisterandcheck/updatethemodelvalue
Table6:RegisteraccessAPI

7 Summary
Overtheyearsvariousverificationmethodologieshavebeenintroducedinordertooptimiseuseofscarceverificationresources.The methodologieshavefollowedanevolutionthathasbroughtusnaturallytoUVManindustrywidemethodologybuiltonanopensource languageandlibrary. InthispaperwehaveshownwhatisrequiredinordertotransitionfromOVMtoUVM.