Report

PS2/GS2 Control Electronics Automated Checkout System.
1. ABSTRACT This project is based on developing a PS2/GS2 Control Electronics Automated Checkout System. This is a unit which simulates input to DUT (Device under Test), process the output from the DUT, verify the output and validate the results. The checkout has software and hardware subsystems. The hardware deals with the various interconnections to the package (eg: sensors). The software part deals with the various test aspects of the PS2/GS2 Control Electronics. The checkout hardware is configured using a cPCI system with I/O modules and power supplies. The software is in Linux Operating System and is built on Qt Designer platform.
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Rajadhani Institute of engineering and technology
2. INTRODUCTION PS2/GS2 Control Electronics is the servo controller for PS2/GS2 stages of PSLV/GSLV which controls the launch vehicle in the desired trajectory during the thrusting phase of PS2/GS2 stage by means of Engine Gimbal Control Hydraulic Actuator System. The function of the Control Electronics is to position the vehicle in pitch and yaw axes in closed loop mode.The package needs power input and commands for both prime and redundant chain. The functional aspects of the package like Initial health, Power supply status, Linearity, Frequency response are tested.By developing user interface programs and driver software of specific I/O modules, we can test the package. Important tests done by using PS2/GS2 control electronics checkout system are: 1. Initial health check 2. Power supply status 3. Linearity test 4. Frequency response analysis 5. Telemetry Monitoring This document gives details of the checkout system used to evaluate the performance of PS2/GS2 Control Electronics packages for onboard flight use. PS2 CE & GS2 CE are identical packages .
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3. BLOCK DIAGRAM
POWER SUPPLIES COMMAND INPUT
PS2/GS2 CONTROL ELECTRONICS SYSTEM
TELEMETRY SENSOR EXCITATION
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PS2/GS2 CE CHECKOUT SYSTEM
cPCI
Control ling user
User interface
SOFTWARE SUBSYSTEM
HARDWARE SUBSYSTEM HARDWARE SUBSYSTEM I/O MODULES GPIB GPIB DP-cPCI-4455 Relay switch module
Power supply o/p
I/O MODULES
GPIB
Power supply
DP-cPCI-2509 precision voltage source DP-cPCI-4113 Relay Matrix Module DP-cPCI-7554 Digital transfer Function
Analyzer Module
Command signals
DP-cPCI-4032 Relay scanner Module DP-cPCI-1105 ADC module DMM Digital Multimeter Telemetry & sensor excitation
PS2/GS2 CE CHECKOUT SYSTEM
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4. PS2/GS2CE CHECKOUT CONFIGURATION
4.1.
HARDWARE CONFIGURATION For these tests the following cPCI based I/O modules are used:
1. GPIB 2. DP-cPCI-2509 precision voltage source 3. DP-cPCI-4455 Relay switch module 4. DP-cPCI-4113 Relay Matrix Module 5. DP-cPCI-4032 Relay scanner Module 6. DP-cPCI-7554 Digital transfer Function Analyzer Module 7. DP-cPCI-1105 ADC module 8. DMM
4.2.
SOFTWARE CONFIGURATION
1. Linux Fedora operating system 2. QT designer
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5. PS2/GS2 CE CHECKOUT SCHEMATIC DIAGRAMS
5.1.
HARDWARE SCHEMATIC DIAGRAMS
5.1.1. POWER SUPPLY SCHEMATIC DIAGRAM
CHECKOUT GPIB CARD
PS2/GS2 CHECKOUT POWER SUPPLY 1
The PS2/GS2 Control Electronics Checkout consisting of one power supply as shown in the above figure. The power supply is selected by using relay switch module 4455. The inputs and outputs are brought to the fascia for high flexibility. Use of rugged connectors field terminations ensures long term reliability.
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5.1.2. COMMAND SCHEMATIC DIAGRAM
The command section consists of PVS 2509 card and DTFA 7554 card. The output of these two cards are given to 4113 Relay Matrix Module and the corresponding commands are given to the actuator. .
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5.1.3. ANALOG TELEMETRY SCHEME
CHECKOUT
RELAY SCANNER 4032
PS2/GS2 CE CHECKOUT ANALOG OUPUT MUX DMM
The Analog Telemetry signals from the PS2/GS2Control Electronics Checkout is given to the 4032 Relay Scanner Module. The Analog signal is MUXed and the ouput is taken from the Digital Multimeter.
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5.2.
SOFTWARE SCHEMATIC DIAGRAMS
5.2.1. ADC ACQUISITION
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Test Procedure Set the power supply voltage to 28V to the input of package and switch it ON. Press the adc acquicition start button Monitor all the telemetry points Then plot the values
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5.2.2HEALTH CHECK
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INPUT MEHOD Set the power supply voltage to 28V to the input of package and switch it ON. Connect Precision DC source output to Command inputs of the package. Set the command inputs of both axes to 0V. Set the feedback input points of both axes to 0V. Connect the servo valve from package to both the axes. Monitor the following signals Current drawn by the package ( DC/DC input current ) Servo valve Direct current of both axes Servo valve Direct output voltage of both axes Servo current T/M. of both axes Command T/M of both axes LVDT output T/M of both axes 15 V T/M output 28V T/M output Comp. Lag Capacitor Bypass Switching relay status LVDT excitation T/M
OUTPUT METHOD Current drawn by the package (DC/DC input current)) Command T/M (P&R) LVDT output T/M(P&R) Servo current T/M. (P&R) LVDT Excitation. T/M 15 V T/M 28V T/M : @28V, @26V,@32V Servo valve Direct current Servo valve Direct output voltage Comp. Lag Capacitor Bypass Switching relay status: Pole at NC contact.
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Repeat the above steps with Lag capacitor bypassed (Give 28 V to (+ ve to C1 22 /23 (Solenoid Valve Command High) and -ve to C1 24/25 (Solenoid Valve Command Low.))
Repeat the above steps at 26 V and 32 V
5.3 LINEARITY AND FEEDBACK PATH 5.3.1 FORWARD LINEARITY
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5.3.2 FEEDBACK PATH LINEARITY
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Linearity test for forward path Prime Controller. Test Procedure for Axis 1 (Pitch Axis) Set the power supply voltage to 28V and switch it ON. Connect Precision DC source output to Command inputs of the package. Set the feedback input points of both axes to 0V by shorting. Set the command input of axis 2 to 0V. Connect the Reference Servo valve with package to the axis-1 and another similar servo valve in Axis 2. At the command input of axis 1 apply a DC voltage varying from 1V to 1V in steps of 0.1 V and -10Vto 10V in steps of 1V. For each input setting monitor the following signals of both axes and calculate the linearity, bias and Scale factor for axis-1by least square best fit straight line fit method with cmd input as the input Servo valve Direct current ( S.F & Linearity calculation for cmd input 0.7 V to +0.7 V). Servo valve output voltage ( S.F & Linearity calculation for cmd input 0.7 V to +0.7 V ) Servo current telemetry ( S.F & Linearity calculation for cmd input 0.7 V to +0.7 V) Command telemetry (S.F & Linearity calculation for cmd input 10V to +10 V ) Ensure that there is no cross coupling in Axis 2. by checking any change in the above parameters of axis-2 from null condition outputs (No change expected) The above procedure is to be repeated with the supply voltage set to 26V & 32V.
Test Procedure for Axis 2 (Yaw Axis) Set the power supply voltage to 28V and switch it ON. Set the feedback input points of both axes to 0V by shorting. Set the command input of axis 1 to 0V. Connect the Ref. servo valve with the package to Axis 2 and another similar servo valve in Axis 1. At the command input of axis 1 apply a DC voltage varying from 1V to 1V in steps of 0.1 V and -10Vto 10V in steps of 1V.
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For each input setting monitor the following signals of both axes and calculate the linearity, bias and Scale factor for Axis 2 by least square best fit straight line fit method with command input as the input Servo valve current (S.F & Linearity calculation for command input 0.7 V to +0.7 V.
Servo valve output voltage (S.F & Linearity calculation for command input 0.7 V to +0.7 V ) Servo current telemetry. ( S.F & Linearity calculation for command input 0.7 V to +0.7 V) Command telemetry ( S.F & Linearity calculation for command input 10V to +10 V) Ensure that there is no cross coupling in Axis 1 by checking any change in the above o parameters of axis-1 from null condition outputs ( No change expected) o The above procedure is repeated with the supply voltage set to 26V & 32V.
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5.4 FREQUENCY RESPONSE ANALYSIS
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Test Procedure Set the power supply voltage to 28V and switch it ON. Set the feedback inputs of both axes to 0V. Set the command input of axis 2 to 0V. Connect the Ref. Servo valve to axis 1 and another similar Servo valve to Axis2 Apply a sine wave of amplitude 1.0Vpp at the command input and sweep the frequency from 0.1Hz to 1Hz in steps of 0.1Hz and 2Hz to 20Hz in steps of 1Hz. This input signal also to be connected to Channel 1 of Frequency Response Analyzer The servo valve voltage direct output (connector C1 pin No.6 w.r.t C3 pin 7)) is to beconnected to Channel 2 of FRA across with a 10K resistor load. Bode plot (Amplitude and phase Vs frequency) is to the plotted and compared with the reference plots provided (attached). Compare the numerical data obtained with the reference data. Compute the maximum difference in gain the dB and phase in deg. Repeat the above procedure by varying the supply voltage to 26V & 32V. Similarly do the test for axis 2 (Yaw axis) also. Set the command input of axis 1 to 0V. Connect the Ref. Servo valve to axis 1 and another similar Servo valve to Axis1. Repeat rest of the above steps.
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5.5 FREQUENCY RESPONSE PLOT
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5.6 TELEMETRY MONITORING
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Test Procedure Set the power supply voltage to 28V and switch it ON. Set the feedback inputs of both axes to 0V. Connect the servo valves from the package to both the axes. Connect the LVDTs to package for both axes. Apply the command inputs (0 V10V & +10V) to both axes simultaneously and monitor 15V T/M and LVDT Excitation T /M outputs.Also monitor current drawn by the package in all cases. The above procedure is to be repeated with the supply voltages of 26V and 32V
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PS2/GS2 CE CHECKOUT HARDWARE DEESCRIPTION
6.1 cPCI CHASSIS: The cPCI rack is a versatile, flexible platform to build any standard cPCI application with standard cPCI cards. Chromate conversion using aluminium alloy is performed on inner surface of the rack to provide electrical contact. While powder containing with black matt is done on the outer surface to protect from corrosion 6.1.1 COMPACT PCI CONNECTOR: This 2 mm hard metric connector has 47 rows of 5 pins per row, with a total 220 pins (15 pins are lost to the keying area). An additional external metal shield is also use the large number of ground pins ensures adequate shielding and grounding for low ground bounce and reliable operation in noisy environments. This connectors controlled impedance minimizes unwanted signal reflection and enables compact PCI system to have eight slots. This can easily be expanded with PCI bridge chips available from a number of manufacturers. Staged power and ground pins are specified for future swap capability. 6.1.2 FEATURES: Standard Euro card dimensions High density High Reliability 2mm Pin-and-socket connectors Positive card retention Excellent shock and vibration characteristics Metal front panel User I/O Connections on front and rear Designed with proper ventilation and EMI/EMC compatibility Hot Swap capability Eight slots in basic configuration, easily expanded with bridges to 21 or more slots Vertical card orientation for good cooling and air routing. Dual redundant power supply Power supply LED indications in the front. Protected and illuminated ON/OFF switch. Light weight and durable aluminium alloy rugged construction.
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6.1.3
cPCI BACKPLANE: A cPCI back plane is an 8-layer PCB containing slots or sockets into which expansion boars are plugged. The 18 slots are separated into 3 groups of 6 slots each. The three groups are connected by two low profile bridges. At the top of each slot, there are jumpers. Which set the geographic address of that slot? The geographic address should be set so that the left most slot in the system has geographic address 1 and the address increments by 1 for each slot to the right.
6.2 I/O MODULES: 6.2.1 GPIB GPIB (general Purpose interfacing Bus) is a communication system between two or more electronic devices. A device can be either an instrument or a computer. When a computer is used on the bus. It serves as a supervisor of the communication exchange between all the devices and is known as the controller. Supervision by the controller consists of determining which will talk and which device will listen. As a talker, device will output information and, as a listener, a device will receive information. To simplify the task of keeping track of the devices, a unique address number is assigned to each. It allow data to be transferred across the GPIB at the maximum rate of 1 MBPS because the GPIB is a transmission line system.
6.2.2
GPIB CONNECTOR AND SIGNAL ASSIGNMENT: The standard connector is the Amphenol or Cinch Series 57 MICRORIBBON or AMP CHAMP type. For special interconnect applications, an adapter cable with nonstandard cable and/or connectors is used.
Fig: Pin out
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DATA LINES Data I/O bit Data I/O bit Data I/O bit Data I/O bit Data I/O bit Data I/O bit Data I/O bit Data I/O bit
Pin No. 1
MANAGEMENT LINES Interface clear Remote enable
Pin No. 9 17 11 10 5
Attention Service request
End/identify
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HANDSHAKE LINES
Pin No. 6 7 8
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Data valid Not ready for data
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Not data accepted
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6.2.2 CONFIGURATION REQUIREMENTS:
To achieve the high data transfer rate for which the GPIB was designed, the physical distance between devices and the number of devices on the bus are limited. The following restrictions are typical for normal operation:
A maximum separation of 4 m between any two devices and an average separation of 2 m over the entire bus
A maximum total cable length of 20 m No more than 15 device loads connected to each bus, with no less than two-thirds powered on
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6.3 DP-cPCI-2509 PRECESSION VOLTAGE SOURCE The DP-MM-2509 is a high precision DC voltage source built on M Module form factor. The use of a main and line source for producing output voltages enables module to produce an output of high precision and accuracy. Four such modules can be mounted in a 6U CPCI slot. The module uses four-wire sensing and can support a maximum current of 10 mA. The output voltage drift with respect to temperature is low. The module provides 4 programmable output ranges. Calibration constants are stored on on-board EEPROM. System ground and field ground are digitally isolated up to 500 V DC. DP-MM-2509 delivers instrument grade high quality precision DC voltage suitable for commercial, avionics, marine and military applications. DP-MM-2509 offers programmable output ranges of 10 mV, 100 mV, 1 V and 10 V with precise D/A conversion and signal conditioning chips higher resolution and accuracy are achieved.
M Module interface section
DAC section
Range selection & output driver section
Fig: block diagram of DP-MM-2509 module
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6.3.1
BLOCK DIAGRAM DESCRIPTION
M-MODULE INTERFACE The communication between the M-Module carrier and the module is carried out by this block. This block consists of the necessary registers through which the MModule carrier can control the precision DC source module. The DP-MM-2509 has 8-bit address bus, a write signal and chip select, using which the registers inside the module is accessed by the carrier. A 2K 8 parallel EEPROM is connected to the M-Module interface. All the linear calibration constants and the non-Linear calibration correction voltages are stored in the EEPROM. This EEPROM is accessed by the processor through FPGA registers. All the digital control and data signals to the DAC and range selection are completely isolated by using Opto-couplers and Photo-mos relays. POWER SUPPLY: The module uses only +5V supply from the carrier for its operation. Low Drop Out Regulators (LDO) are used to generate the required digital supplies of 2.5V and 3.3V from the 5V supply. A low noise DC-DC converter is used for the generation of the analog supplies of +15V and -15V. The output of the DC-DC converter is filtered using LC filters in order to reduce the effect of power supply noise in the output. DAC SECTION: Two 16-bit serial DACs, one for fine adjustment and the other for the coarse adjustment are used. The two DACs are interfaced to the FPGA through opto-couplers. Both the DACs are programmed to obtain the required voltage.
A low noise, low drift reference source is used for the DAC reference supply. RANGE SELECTION AND OUTPUT DRIVER: The outputs of the DACs are given to this section. The range selection is done by means of a low drift resistor network. The output of this network is given as input to an
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analog multiplexer (formed by using Photo-mos relay). The appropriate relay is switched to provide four output voltage ranges of 10V, 1V, 100mV, 10mV. The output voltage from the divider is buffered through a precision OP-AMP. It is compensated for capacitive loads and lead length. It has protection against output over voltage. It is also short circuit protected
6.3.2
FEATURES: Resolution up to 10 V Output accuracy 0.01 % Software selectable output ranges of 10V, 1V, 100mV, 10mV Remote sensing feature Isolated analog output Dual 16-bit DAC per channel for fine and coarse adjustment Standard M Module form factor RT Linux drivers provided Up to 4 channels in a single 6U slot Suitable for CPCI, VME, VXI and PCI systems with appropriate carrier
6.3.3
APPLICATIONS: Traducer simulation automated test systems component / circuit analyses hardware in-loop simulation
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6.4 DP-cPCI-4455 RELAY SWITCH MODULE The DP-MM-4455 is a hot swappable 24 channel, 5 A Relay Switch Module confirms to cPCI bus specifications. It is a relay module using 1 form C 5V relays. The relays can be operated separately or all at once. Relays are of NO: 150W/1250 VA, NC: 30W/500VA which can switch high voltage signals upto 250 V AC / 30 V DC. The inputs and outputs are brought to the fascia for high flexibility. Use of rugged connectors field terminations ensures long term reliability. This module provides for 500V DC/peak isolation between channels.
cPCI interface
Hot swap
CPLD section
Relay drive section
6.4.1
BLOCK DIAGRAM DESCRIPTION cPCI INTERFACE: The Compact PCI is an adaptation of the peripheral component interconnects (PCI) specification PICMG 2.1 for industrial and / or embedded application requiring a more robust mechanical form factor than desktop PCI. The module interfaces with the backplane through J1 connector (32 bit PCI signals). HOT SWAP:
DP-cPCI-4455 uses PCI 9030 and a hot swap controller to ensure safety and error free operation as a result of live insertion and extraction. PCI 9030 has necessary, hardware and software features, which indicates to the user the current status of the module. Hot swap controller ensures proper supply of required voltages to the board.
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PCI 9030 interfaces with a serial EEPROM to load configuration information, such as Device ID, Vendor ID, Chip Select, etc. cPLD SECTION: The local bus signals from 9030 are brought into CPLD & CPLD section of the module performs the function of generating drive signals to the relay drivers. The relay drivers are latched through two stages, primary latch and secondary latch. Input to the primary latch is given by the user, this input is responsible for the condition of the relays. Read back of the primary latch, read back status taken from relay coils are available for verification purpose. RELAY DRIVE SECTION: The relay drive section provides the necessary drive to switch ON the relays. The output of CPLD is buffered using ULN2003A drivers. This output drives the relay coil.
6.4.2
FEATURES: cPCI interface live insertion/removal 1 form C SPDT switch High voltage up to 250 V AC/30 V DC Maximum switching current 5 A (NO0 1A (NC) Relays can be operated individually, or all at once Switch verification of latched data Rugged connectors for field terminations
6.4.3APPLICATIONS: Power supply switching Automated test equipment General purpose switching Process control Relay output for soft PLCs
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6.5 DP-cPCI-4113 RELAY MATRIX MODULE The DP-MM-4113 is a hot swappable 12*4 relay Matrix Module confirms to cPCI bus configurations. Relays can be operated individually, or all at once. The relays are of A configuration. The relays can be used to switch voltage signals up to 200 V DC. The inputs and outputs are brought out to the fascia for high flexibility. Use of rugged connectors for field terminations ensures long term reliability. DP-cPCI-4113 offers switching matrix in a single slot 6U sized cPCI module with flexibility to configure for 48 cross-points or 72 cross-points on factory selectable basis. The Reed Relays (Ruthenium sputtered type) used makes it ideal for applications where very low switching is required. These relays have internal magnetic shield with mu metal screen. This prevents signal cross talk due to relay coil magnetic fields. All relays are arranged in matrix connecting 12 differential inputs across 4 differential outputs on fascia. The flexibility of matrix switching allows connection of any input(row) to any output(column), singly or in combination, for complex signal and measurement device switching. For larger switching configuration multiple modules of DP-cPCI-4113 can be used.
cPCI interface
Hot swap logic
Control logic
Relay section
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6.5.1
BLOCK DIAGRAM DESCRIPTION cPCI INTERFACE: The Compact PCI is the advanced version of the Peripheral Component Interconnect (PCI) specification 2.1. It is meant for industrial and/or embedded application where a more robust mechanical form factor is required than desktop PCI. The module interfaces with the backplane through J1 connector (32 bit PCI signals) and J2 connector (for geographic addressing option). PCI 9030 is used as the interface controller. It has hardware and software features, which indicates the current status of the module to the user. PCI 9030 interfaces with a serial EEPROM to load configuration information, such as Device ID, Vendor ID, Chip Select, etc. HOT SWAP LOGIC: Hot swap controller is used along with PCI 9030 to ensure safe and error-free operation during live insertion and extraction. The hot swap controller ensures proper supply of required voltages to the board. The interface indicates the current status of the module to the user. CONTROL LOGIC: The local bus signals from the PCI 9030 are brought into the control logic section. The Glue Logic for controlling relays is implemented on a field programmable gate array. The user can write commands for the selected channels to the primary latch. A read back is available to confirm selected commands. The Decode and Control logic enables data transfer from primary to secondary latch. Buffers provided offer necessary drive for relay coils.
RELAY SECTION: The relays used in this section are of Form A configuration. These relays are capable of switching low currents and voltages. These relays can be used to switch voltages upto 200V DC. The relays are positioned at the cross points of the matrix and
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the required relay is switched ON with the driving signal generated from the control logic section. 6.5.2 FEATURES: Contact rating Maximum Switching voltage of 200V DC Maximum Switching current of 0.5A Maximum carrying current of 1.2A
Up to 48 differential cross points(standard) Up to 72 differential cross points(optional) Ideal for low signal switching 100% tested for dynamic contact resistance Hot swap compliant Single slot 6U form factor Windows 2000 drivers provided RT Linux drivers provided
cPCI interface Live insertion/removal Form A relay, having high dielectric strength. Relays can be operated individually, or all at once During power down stage, all relays are open During power ON stage, all relays are open
6.5.3
APPLICATIONS: Data Acquisition system Automated test equipment Battery testing Power supply testing Transducer testing
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6.6 DP-cPCI-4032 RELAY SCANNER MODULE The DP-MM-4032 is a hot swappable 96*2 Low thermal relay scanner Module that confirms to cPCI bus configurations. This module supports 1 wire and 2 wire formats. The relays can switch up to 200 V DC. The inputs and outputs are brought out to the fascia for high flexibility. Resistors are provided on all common terminals for short circuit protection. Rugged connectors for field terminations are used to ensure long term reliability.
cPCI interface
Hot swap logic
Control logic
Relay section
6.6.1
BLOCK DIAGRAM DESCRIPTION cPCI INTERFACE: The Compact PCI is an adaptation of the Peripheral Component Interconnect (PCI) specification 2.1 for industrial and/or embedded application requiring a more robust mechanical form factor than desktop PCI. The module interfaces with the backplane through J1 connector (32- bit PCI signals) and J2 connector (for geographic addressing option). HOP SWAP: DP-cPCI-4032 uses PCI 9030 and a hot swap controller to ensure safety and
error free operation during live insertion and extraction. PCI 9030 has necessary, hardware and software features, which indicates to the user the current status of the module. Hot swap controller ensures proper supply of required voltages to the board. PCI 9030 interfaces with a serial EEPROM to load configuration information, such as Device ID, Vendor ID, and Chip Select and so on.
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CONTROL LOGIC SECTION; The local bus signals from the PCI 9030 are brought into the control logic section. The control logic section generates the necessary drive signals for the on-board relays. Wide range of trigger options is provided for the user. The trigger can be any one of the following two triggers Software Trigger or Fascia Trigger. Clock Control Logic Circuitry is used to select the trigger. These triggers are used for secondary registers. The module works in two ways. Single Channel Selection Multi Channel Selection If multi channel mode is selected, the data for relay selection are from the direct data bus. If single channel mode is selected, the data for relay selection is the decoded data from the direct data bus. Break before make circuit ensures reliable switching for accurate signal measurement. This circuit is used to switch OFF all the channels before the next channel is switched ON. The relay driving is achieved through two sections, namely, the Primary latch section and Secondary latch section. The purpose of secondary latch section is to allow simultaneous operation of all relays. The user gives input to the primary latch, which is responsible for the condition of the relays. Read back of the primary latch section is available. Geographic addressing feature is implemented for unique slot identification.
RELAY SECTION: The relay used in this section is of Form A configuration. These relays are capable of switching low currents and voltages. These relays can be used to switch voltages up to 200V DC. There are six groups of 16 relays each. Each group has a three switch relay. The final output can be switched in 1- wire or 2- wire formats. The driving signals for these relays are generated from the logic section.
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6.6.2
FEATURES: Single slot cPCI 6U form factor 192 channels for 1-wire format 96 channels for 2-wire format Break before make circuitry for accurate signal measurement. Fast switching speed < 1 ms Switch up to 200 volts Unique slot identification through geographic addressing option Relay status indicators Trigger options through soft ware and fascia control High reliability I/O outputs with short circuit protection I/O termination using rugged field connectors. Single Slot cPCI 6U form factor 191 (1-wire), 962 (2-wire) formats Break Before Make circuitry Fast switching speed < 1msec Switch up to 200Volts Geographic addressing option Hot swap complian
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6.7 DP-cPCI-7554 DIGITAL TRANSFER FUNCTION ANALYZER (DTFA) MODULE DP-cPCI-7554, a cPCI card is capable of analyzing the phase and gain characteristics of a system. DP-cPCI-7554 card consists of a generator and two analyzer channel. The user defined waveform can be generated of varying frequency of about 1 MHz to 2 kHz. This system under test is simulated by the user defined waveform and the obtained response is correlated with the applied stimulus by the on-board DSP processor to determine the phase difference and the gain. This card employs on-board DSP processor. Which correlates the defined waveform along with the applied stimulus and calculates the phase difference and the gain. The phase difference can be used in calculating the system's transfer function. 6.7.1 FEATURES: Waveform generate with 16-bit resolution. Two channel analyser with 16-bit resolution. Sine, step, ramp, arbitrary waveform generation. Frequency generation from 10-3 to 2 KHz. Sweeping step size from 10-3 to 500 Hz. Linear and logarithmic step change. Programmable number of cycles. On-board 32 bit floating point SHARC DSP. In built short circuit protection. Gain Vs frequency and phase Vs Frequency measurement. Software programmable master/ slave mode. Complete isolation for the generated output from the PC return. Frequency changes are phase continuous Isolator Generator and Analyzer circuits
6.8 DP-cPCI-1105 ADC MODULE The DP-MM-1105 is an M-Module ADC of 16-chu resolution. Inputs are optically isolated from the system and the supply voltages are provided using on-board DC-DC converter. Option is available for providing external supplies, in which card the
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on-board DC-DC converter should be removed. Inputs can be configured as either 8 differential channels or 16 single ended channels. The channel and signal selection is done by the on -board multiplexer which is provided with an active over voltage protection. ADC pacing is done by means of numerically controlled oscillator. The sequences and modes of channels to be measured are defined in the 512 x 8 Scan RAM. The analog to digital values along with the channel and gain selection value are available in the 1K x24 FIFO. An A/D converter combined with multiplexed channel makes this module ideal for high speed sampling measurement.
6.8.1
FEATURES: Analog input M-Modules 100khz 16bit analog to digital conversion 8 differential inputs or 16 single ended inputs Programmable gain of 1,10,100,1000 512 Entry scan RAM for Scan sequencing 1K sample FIFO for converted data numerically controlled oscillator for flexible scan frequency Digitally isolated channel to system for high linearity.
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PS2/GS2 CE CHECKOUT SOFTWARE DESCRIPTION:
7.1 LINUX FEDORA OPERATING SYSTEM: Fedora is a RPM-based, general purpose collection of software, including an operating system based on the Linux kernel, developed by the community-supported Fedora Project and sponsored by Red Hat. The Fedora Project's mission is to lead the advancement of free and open source software and content as a collaborative community. One of Fedora's main objectives is not only to contain software distributed under a free and open source license, but also to be on the leading edge of such technologies. Fedora developers prefer to make upstream changes instead of applying fixes specifically for Fedora-this ensures that their updates are available to all Linux distributions. Compared to more main stream Non-Linux operating systems Fedora has a short life cycle. Version X is maintained until one month after version X+2 is released. With 6 months between releases, the maintenance period is a very short 13 months for each version. This can lead to trouble should one wish to use a particular version of Fedora for product development (i.e., embedded systems) where long term support is more important than maintaining leading edge revisions of software. In 2008, Linus Torvalds, author of the Linux kernel, stated that he used Fedora because it had fairly good support for the PowerPC processor architecture, which he favored at the time. According to DistroWatch, Fedora is the third most popular Linux-based operating system as of June 2011, behind Ubuntu and Mint, and it is the most popular RPM-based Linux distribution.
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7.2 QT DESIGNER: Qt is a cross-platformapplication framework that is widely used for developing application software with a graphical user interface (GUI) (in which cases Qt is classified as a widget toolkit), and also used for developing non-GUI programs such as command-line tools and consoles for servers. Qt uses standard C++ but makes extensive use of a special code generator (called the Meta Object Compiler, or moc) together with several macros to enrich the language. Qt can also be used in several other programming languages via language bindings. It runs on the major desktop platforms and some of the mobile platforms. It has extensive internationalization support. Non-GUI features include SQL database access, XML parsing, thread management, network support, and a unified cross-platform API for file handling.
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8. CONCLUSION
Thus the project entitled Development of Checkout for Test and Evaluation of PS2/GS2 Control Electronics System. This is a unit which simulates input to DUT (Device under Test), process the output from the DUT, verify the output and validate the results. PS2/GS2 Control Electronics is a unit which generates control signals for the movement of the Actuator. It gives outputs like sensor excitation, telemetry outputs regarding the health of the package. The package needs power input and commands for both prime and redundant chain. The functional aspects of the package like Initial health, Power supply status, Linearity, Frequency response are evaluated
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10.BIBLIOGRAPHY
1. Conde, R.F., Haber, J.W., Webbert, R.W., Redman, R.J., Mellert, J.D., Bogdanski, J.F., Ling, S.X.,
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Processing (Hardware/Software) ,Fields, Waves & Electromagnetics , Robotics & Control Systems ; Signal Processing & Analysis , Transportation
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Topic(s): Bioengineering , Components, Circuits, Devices & Systems , Engineered Materials, Dielectrics & Plasmas ,Fields, Waves & Electromagnetics , General Topics for Engineers (Math, Science & Engineering) , Photonics & ElectroOptics , Power, Energy, & Industry Applications
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6. Gilbert,R. Micro,IEEE Volume:2, Issue:1 Topic(s): Computing & Processing (Hardware/Software) 7. Savi Maharaj, Bicarregui, J. Automated Software Engineering, 1997. Proceedings.,12th IEEE Internationa Conference Topic(s): Computing & Processing (Hardware/Software) 8. Zhou, J.M., Jian Guo, Fu Song Information Engineering and Computer Science, 2009.ICIECS2009.InternationalConferenceon Topic(s): Computing & Processing (Hardware/Software) 9. Owre, S., Rushby ,J., Shankar, N., vonHenke, F. SoftwareEngineering, IEEE Transaction Volume:21, Issue:2Topic(s): Aerospace ; Bioengineering.
10. Pal, R.K.; Sengupta, I. Computational Intelligence in Cyber Security, 2009. CICS '09.IEEE Symposiumon Topic(s): Computing & Processing (Hardware/Software) 11. Cotroneo, D., Natella, R., Pietrantuono, R., Russo, S. Software Reliability Engineering (ISSRE),2010 IEEE 21st International Symposium
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APPENDIX
44
11.2I/O MODULE SPECIFICATIONS 11.2.1. DP-cPCI-1105 ADC Module specifications 8 differential voltage inputs or 16 single ended voltage inputs 16 bit 0.01% with calibration 1.75 LSB
No. of channels Resolution Precision Differential Nonlinearity Input range of A/D converter Impendence to ground Input impendence Input protection Common mode rejection A/D conversion time Throughput Programmable gain factor
10 V >10M/<100pF 10M 42 V >80dB 5s( max) 100 KHz 1.10.100 or 1000 External trigger (isolated, rising- edge sensitive)
Miscellaneous
External binary input via front pannelon shielded D type connector
Isolation
500 V DC channel to system 25 s for gain =1, Voltage swing =-10V to +10V 30 s for gain =10, Voltage swing =-1V to +1V
Settling time (0.01 %)
140 s for gain =100, Voltage swing =-100mV to +100mV 1300 s for gain =1000, Voltage swing =-10mV to +10mV
45
11.2.2. 2509 SPECIFICATIONS: No. of channels: one Range & accuracy characteristics Range 10 mV 100 mV 1 V 10 V Noise characteristics Range 10 mV RMS V P-P (V) Output characteristics Current 10 mA, short circuit protected Maximum capacitance load Settling time Maximum isolation Stability characteristics Recommended warm up time Offset temperature coefficient Gain temperature coefficient DC stability 30 minutes 0.2 V/C 12 ppm / C <36 V in 24 hours 10,000 pF 10 ms 500 V 0.12 1.2 100 mV 0.13 1.24 1 V 0.44 4.4 4.24 42.4 10 V Usable resolution 10V 10V 10V 50V Accuracy 0.1% 0.01% 0.01% 0.01%
46
11.2.3. 4455 SPECIFICATIONS INPUT CHARACTERISTICS No. of channels Maximum switching voltage Maximum switching current Maximum switching power/channel 24 DC :0 V, AC rms: 250V NO: 5 A, NC: 1 A NO: DC 150W, AC 1250 VA NC: DC 30W , AC500 VA
DC CHARACTERISTICS Closed channel resistance Insulation resistance (at 500V DC) AC CHARACTERISTICS Relay life Relay closure time Power up time Power down stage Relay release time ISOLATION Between channels POWER Power requirements CONNECTOR Back plane interface Field interface cPCI interface 37 pin D type male connectors DIMENSIONS Board Module ENVIRONMENT Operating free air temperature Storage temperature
47
300 m/channel 1000M
At no load: 10 operations At rated load: NO:105, NC: 105 10ms(typical) All contacts are open All contacts are open 5ms(typical)
250V DC/peak AC
5 V, 2.6 A
233.35 mm(H) x 160 mm (D) 6U (H) 0.50C 0-70C
Relative humidity
Up to 90 % (non condensing)
11.2.4. 4113 SPECIFICATIONS INPUT CHARACTERISTICS Cross point/ nodes Maximum switching voltage Maximum switching current Maximum carrying current Type of relay Power rating DC CHARACTERISTICS Maximum contact resistance Insulation resistance RELAY SPECIFICATIONS Power down stage Power ON stage Contact material Power requirement SYSTEM CONFIGURATION Bus utilization CONNECTOR Back plane interface Field interface DIMENSIONS Board Module ENVIRONMENT Operating free air temperature Storage temperature Relative humidity 0.50C 0-70C Up to 90 % (non condensing) 233.35mm (H) x 160 mm (D) 6U cPCI J1 & J2 connector 25 pin D type connectors One slot in the cPCI-6U All relays are open All relays are open Sputtered ruthenium 5 V @ 2 A, 3.3 A @ 500 mA 150 m (initial) >1012 48(12 x 4 matrix switch) 200 V 0.5 A 1.2 A Form A 10 Watts
48
11.2.5. 4032 specifications 102channels 1 wire 96channels 2 wire Read relay <15V 200V 10W
Multiplexer configuration Switch type Differential terminal offset Maximum switch power Maximum power Path resistance Between channel to bank common Between channel and tree output OFF Relay coil voltage Tree switch relay coil resistance(per relay) Bank relay coil resistance (per relay) Operating time Release time Power up state Power down state Power requirement Connectors MECHANICAL Slot size
<105 <105 >10 5V DC 1000 ohms
375 ohms <1ms(max).0.5ms(type) <1ms(max).0.5ms(type) Relays contacts open Relays contacts open 5V@2A 78-pinD type male connectors
Single, 6U cPCI slot 233.35mm *160.0mm
49
11.2.6.7554 specifications GENERATOR No: of channels Method Resolution Waveform Waveform memory 2 Direct digital synthesis 16 bit Sine, square, ramp and arbitrary wave form 256 K words Range : 1 mHz to 2 KHz Frequency Resolution : 1mHz Error : <0.01% Sweep: Linear. Log Amplitude Bias + amplitude Impedance to ground Output impedance Full scale output :10 mv,100mV,1V and 10V Range : 10 V >10 M/ <100pF 0.6 ANALYZER No: of channels Resolution 4 16 bits For gain 1 Input range For gain 10 For gain 100 10V 1V 100mV
For gain 1000 10 mv Input protection Common mode rejection A/D conversion time Throughput Measurement delay Integration time 42 V 65 dB 10s(max) 100KHz 0.01% of full scale Minimum : 1 cycle Maximum:1000cycles
50

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PS2/GS2 Control Electronics Automated Checkout System.

PS2/GS2 Control Electronics Automated Checkout System.

PS2/GS2 Control Electronics Automated Checkout System.

POWER SUPPLIES COMMAND INPUT

PS2/GS2 CONTROL ELECTRONICS SYSTEM

TELEMETRY SENSOR EXCITATION

PS2/GS2 Control Electronics Automated Checkout System.

PS2/GS2 CE CHECKOUT SYSTEM

Control ling user

PS2/GS2 CE CHECKOUT SYSTEM

PS2/GS2 Control Electronics Automated Checkout System.

4. PS2/GS2CE CHECKOUT CONFIGURATION

1. Linux Fedora operating system 2. QT designer

PS2/GS2 Control Electronics Automated Checkout System.

5. PS2/GS2 CE CHECKOUT SCHEMATIC DIAGRAMS

HARDWARE SCHEMATIC DIAGRAMS

5.1.1. POWER SUPPLY SCHEMATIC DIAGRAM

CHECKOUT GPIB CARD

PS2/GS2 CHECKOUT POWER SUPPLY 1

PS2/GS2 Control Electronics Automated Checkout System.

5.1.2. COMMAND SCHEMATIC DIAGRAM

PS2/GS2 Control Electronics Automated Checkout System.

5.1.3. ANALOG TELEMETRY SCHEME

RELAY SCANNER 4032

PS2/GS2 CE CHECKOUT ANALOG OUPUT MUX DMM

PS2/GS2 Control Electronics Automated Checkout System.

SOFTWARE SCHEMATIC DIAGRAMS

5.2.1. ADC ACQUISITION

PS2/GS2 Control Electronics Automated Checkout System.

PS2/GS2 Control Electronics Automated Checkout System.

PS2/GS2 Control Electronics Automated Checkout System.

PS2/GS2 Control Electronics Automated Checkout System.

Repeat the above steps at 26 V and 32 V

5.3 LINEARITY AND FEEDBACK PATH 5.3.1 FORWARD LINEARITY

PS2/GS2 Control Electronics Automated Checkout System.

5.3.2 FEEDBACK PATH LINEARITY

PS2/GS2 Control Electronics Automated Checkout System.

PS2/GS2 Control Electronics Automated Checkout System.

PS2/GS2 Control Electronics Automated Checkout System.

5.4 FREQUENCY RESPONSE ANALYSIS

PS2/GS2 Control Electronics Automated Checkout System.

PS2/GS2 Control Electronics Automated Checkout System.

5.5 FREQUENCY RESPONSE PLOT

PS2/GS2 Control Electronics Automated Checkout System.

5.6 TELEMETRY MONITORING

PS2/GS2 Control Electronics Automated Checkout System.

PS2/GS2 Control Electronics Automated Checkout System.

PS2/GS2 CE CHECKOUT HARDWARE DEESCRIPTION

PS2/GS2 Control Electronics Automated Checkout System.

Fig: Pin out

PS2/GS2 Control Electronics Automated Checkout System.

MANAGEMENT LINES Interface clear Remote enable

Attention Service request

Data valid Not ready for data

Not data accepted

PS2/GS2 Control Electronics Automated Checkout System.

6.2.2 CONFIGURATION REQUIREMENTS:

PS2/GS2 Control Electronics Automated Checkout System.

M Module interface section

Range selection & output driver section

Fig: block diagram of DP-MM-2509 module

PS2/GS2 Control Electronics Automated Checkout System.

BLOCK DIAGRAM DESCRIPTION

PS2/GS2 Control Electronics Automated Checkout System.