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Self-Powered Gate Driver for Normally ON Silicon Carbide Junction Field-Effect Transistors Without External Power Supply
Dimosthenis Peftitsis, Student Member, IEEE, Jacek Rabkowski, Member, IEEE, and Hans-Peter Nee, Senior Member, IEEE

AbstractThe very low on-state resistance, the voltagecontrolled gate, and the relative simplicity of fabrication of the normally ON silicon carbide junction eld-effect transistor (JFET) make this device the most important player among all state-of-theart silicon carbide transistors. However, the normally ON nature counts as the main factor which keeps this device far from being considered as an alternative to the silicon insulated-gate bipolar transistor. A self-powered gate driver without external power supply for normally ON silicon carbide JFETs is presented in this paper. The proposed circuit is able to handle the short-circuit currents when the devices are subjected to the dc-link voltage by utilizing the energy associated with this current. On the other hand, it supplies the necessary negative gate-source voltage during the steady-state operation. A detailed description of the operating states in conjunction with a theoretical analysis of the proposed self-powered gate driver is presented. The rst part of the experimental investigation has been performed when the proposed circuit is connected to a device which is directly subjected to the dc-link voltage. The second set of measurements were recorded when the self-powered gatedriver was employed as the driver of normally ON components in a half-bridge converter. From the experimental results, it is shown that the short-circuit current is cleared within approximately 20 s after the dc-link voltage is applied, while the power consumption when all devices are kept in the OFF state equals 0.37 W. Moreover, it is experimentally shown that the proposed gate driver can properly switch when it is employed in a half-bridge converter. Finally, limitations regarding the range of the applications where the self-powered gate drive can efciently operate are also discussed. Index TermsGate-driver power supply, normally ON silicon carbide (SiC) junction eld-effect transistors (JFETs), protection circuit, silicon carbide.

I. INTRODUCTION

URING recent years, several types of power transistors in silicon carbide (SiC) have been introduced on the market [1], [2]. The only type that can be driven from a standard driver for silicon insulated-gate bipolar transistors is the SiC metaloxide silicon eld-effect transistor (MOSFET) [3]. This device, however, is far more complicated to

Manuscript received May 19, 2012; revised July 3, 2012; accepted July 12, 2012. Date of current version October 12, 2012. Recommended for publication by Associate Editor Y. C. Liang. The authors are with the Electrical Energy Conversion (E2C) Lab, School of Electrical Engineering, KTH Royal Institute of Technology, SE-10044 Stockholm, Sweden (e-mail: dimost@kth.se; rabkow@kth.se; hansi@kth.se). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TPEL.2012.2209185

fabricate [4] than SiC junction eld-effect transistors (JFETs) or SiC bipolar junction transistors (BJTs) [5] because the SiC MOSFET requires a gate-oxide layer as the silicon counterpart. There are mainly two problems associated with this gate-oxide layer in SiC MOSFETs. First, the oxide itself may not have a sufcient long-term reliability [6][8], especially at high temperatures. The second problem is found directly beneath the gate oxide. The mobility in the channel is more than one order of magnitude lower than what could be expected [4], [9][11], which causes a substantial increase in the on-state resistance (at least for 12001700 V devices). Even if the values of the channel mobility have increased over the years, the SiC MOSFET still cannot compete with JFETs and BJTs in SiC in terms of on-state resistance [12], but in the future high-voltage SiC MOSFETs may become very competitive [13]. SiC BJTs, on the other hand, require a considerable base current as long as the BJT is in the ON state [14]. With current gains of approximately 85 [15], the base driver must provide more power than gate drivers of SiC MOSFETS or JFETs. The other drawback of SiC BJTs is that the BJT cannot conduct in the reverse direction. It may seem strange that this is put against the SiC BJT. However, if an antiparallel or free-wheeling diode in SiC is employed, the voltage drop of this diode is signicantly higher than that of a silicon diode, and up ten times higher than the on-state voltage of a SiC JFET, depending on the choice of current density in the JFET. The SiC JFET, however, can conduct in the reverse direction [16], [17] and has no gate-oxide layer. JFETs can be designed as enhancement-mode normally OFF [18][21] JFETs or depletion-mode normally ON JFETs [18][21]. Some semiconductor structures such as the vertical trench JFET can be designed to be either normally ON or normally OFF simply by changing the doping level of the channel region [22], [23]. Especially, in this context it becomes clear that a normally ON JFET will have a lower on-state resistance [24]. Another drawback of the normally OFF JFET is that the gate-source junction has to be forward biased in order to turn the JFET ON. This implies a considerable gate current [25], almost as high as the base current of the SiC BJT. In the opinion of the authors, the normally ON JFET is, therefore, preferable if the normally ON problem can be accepted [26]. This is a problem that has to be handled on the system level in such a way that a sufcient reliability can be ensured. This may involve several safety systems, of which some would be used also for normally OFF transistors. A vital unit in such a safety system is an automatic power-up gate driver without the need for external power sources. Such a

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gate driver should be able to handle the short circuit caused by the normally ON JFETs at start-up and bring them to a stable OFF state. Additionally, it should be capable of driving the JFET during normal operating conditions taking the power from the main circuit. In the literature, ve suggestions for solutions to the normally ON problem have been presented. The rst [27], [28] is based on a cascode connection with a low-voltage silicon MOSFET. The solution is promising because the cascode connection makes the switch to behave as a normally OFF device. However, this is achieved at the cost of three drawbacks. First, the series-connected silicon MOSFET will add voltage drop [29]. Second, the two devices of the cascode connection must be matched in order to cooperate successfully. Such matches are usually cost driving. Finally, by introducing a silicon device, operation at high temperatures is prohibited. This is a severe shortcoming of the cascode concept as high-temperature operation is one of the most important benets of SiC technology [30][36]. To conclude, it is the opinion of the authors that this is a temporary solution until better alternatives appear. The second solution which has been presented in the literature deals with handling both the start-up and gate-driver power failures of normally ON SiC JFETs employed in a voltage source converter (VSC) [37], [38]. An auxiliary normally ON JFET is used as a linear regulator and it is connected to the input of the VSC. Under either the start-up process or a gate-driver failure, the protection scheme is activated, and by employing an ultrafast converter a negative voltage is supplied to the gates of the lower SiC JFETs of the VSC. Even though the short-circuit currents are handled in a very short time (approximately 100 s), the gate drivers of the SiC JFETs still require an external power supply for the steady-state operation. Moreover, the protection scheme is only employed on the low-side JFETs. Thus, the upper JFETs operate without any protection scheme. A protection circuit against gate-driver failures has also been presented in [39]. It is able to handle the short-circuit current within a few microseconds, but the external power supply which is required counts as a basic drawback of this solution. A shoot-through protection scheme for VSCs with normally ON SiC JFETs has also been shown in [40]. It basically consists of a Si insulated gate bipolar transistor (IGBT) in series connection with a relay while both are connected in parallel with a charging resistor. This protection scheme is employed in the mid-point between the dc-link capacitors and it is able to clear any short circuits in a very short time. Nevertheless, an external power supply for the gate drivers of the SiC JFETs is also needed in this case. Under a short-circuit case on a phase-leg of the VSC, the fault is detected and a high impedance path is created due to the charging resistor. Thus, the short-circuit current dissipates power in this resistor. A successful example of a protection circuit for normally ON SiC JFETs employed in a switch-mode power supply (SMPS) fed by the grid has been presented in [41]. The proposed circuit utilizes the inrush current during the start-up process in order to turn OFF the JFET. It must be noted that this circuit ensures a safe operation of the JFET either if the sinusoidal input voltage starts at zero or at any other value when the SMPS is connected to the grid. As most of the previous ideas described previously,

this protection scheme also requires an external power supply for the gate driver of the SiC JFET under steady-state operation. In this paper, a self-powered gate driver (SPGD) for normally ON SiC JFETs without the need for an external power supply is presented. The proposed circuit is able not only to handle the start-up process of the normally ON SiC JFET, but also to properly supply the gate during steady-state operation. A modied dc/dc forward converter is used in order to handle the start-up process, while the gate power during steady-state operation is provided by a dc/dc yback converter. The (start-up) forward converter basically utilizes the JFET voltage drop caused by a well-dened shoot-through current and supplies a negative gatesource voltage which turns the JFET OFF. The shoot-through current is determined by a start-up resistor, in the same way as in many commercial products. During normal operation, the high blocking voltage across the JFET is converted to a negative low voltage which continuously supplies the gate driver by means of a yback converter. A detailed analysis of the proposed circuit is provided in Section II. The experimental investigation of the SPGD has been performed using two different test circuits as presented in Section III. A discussion on the design limitations of the proposed idea is given in Section IV, while Section V summarizes the main conclusions of this paper. II. SELF-POWERED GATE-DRIVER CONCEPT There are basically two design requirements that must be taken into account when a smart gate driver for normally ON SiC JFETs is designed. On the one hand, a solution to the normally ON problem must be provided in order to stop the shoot-through current which might thermally destroy the device. On the other hand, a power supply to the gate-drive unit must also be provided in order to enable stable steady-state switch-mode operation of the device. These two main issues have been considered during the design steps of the proposed SPGD for normally on SiC JFETs. A brief description of the SPGD concept is presented next, while a more detailed analysis is also shown in Section II-B. A. SPGD Concept The proposed SPGD includes two switch-mode converters as shown in the block diagram in Fig. 1. The input stage of both converters is in parallel connection with the main SiC JFET, Jm . In order to analyze the sequence of the operation of the two converters, the output capacitors C1 and C2 are also depicted in Fig. 1. In particular, a capacitor is connected at the output of each converter. The start-up converter only operates during the start-up process of the SiC JFET, and by utilizing a well-dened short-circuit current owing through the device, it generates a negative gate-source voltage Vsu which appears across C1 . This voltage must be more negative than the pinch-off voltage of the SiC JFET in order to turn OFF the normally ON SiC JFET. Thus, the short circuit is turned OFF and the drain-source voltage of the JFET equals the blocking voltage, which is determined by the circuit parameters (e.g., in the case of a half-bridge inverter the blocking voltage equals half of the dc-link voltage, etc). As can be seen from Fig. 1 the start-up converter only supplies the

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Fig. 1. Block diagram of the proposed self-powered gate driver for normally ON SiC JFETs.

integrated-circuit driver (IC driver) and not the optocoupler due to the diode D3 . This practically means that the optocoupler is disconnected from the circuit, and thus, the input signal to the IC driver is in the low state. Consequently, the output of the IC driver is equal to the low voltage state, which in this case is the negative voltage supplied by the start-up converter. The steady-state converter, on the other hand, converts the high blocking voltage to a low voltage, Vss , which supplies both the IC driver and the optocoupler. This converter is able to start operating as soon as the drain-source voltage of Jm , Vds m , is high, or practically when Vds exceeds a certain voltage limit. During the steady-state operation of the steady-state converter, the capacitor C2 is continuously charged to a certain voltage level determined by the duty-ratio controller of M1 . Hence, the SiC JFET Jm can be properly driven by providing appropriate control signals to the input of the optocoupler. A sufciently large capacitance value for C2 is required in order to ensure that the output voltage Vss will be kept approximately constant. B. Operating States of the SPGD As described previously, there are basically two operating states of the proposed SPGD: the start-up and the steady-state ones. It is worth to mention that it is the combination of these two states which is required in order to eliminate the short-circuit current and properly switch the device. Fig. 2 shows a detailed schematic of the SPGD where all the vital components are depicted. The Rpm Cgm Rg network has shown to be successful in providing fast switchings, noise immunity, and the possibility to parallel-connect several SiC JFETs [42], [43]. The start-up converter, which is a forward converter without a freewheeling diode, is illustrated with the bold lines in Fig. 3(a). It consists of a normally ON SiC JFET, Jaux , a highfrequency current transformer with very high turns ratio T/F1 , a low-voltage diode D1 , and a capacitor C1 . This converter is connected across the main SiC JFET. On the contrary, the steadystate converter is a high-to-low voltage yback converter as indicated with the bold lines in Fig. 3(b). As the start-up converter, it is also connected across the main SiC JFET, or in other words in parallel with Jm . The vital components of the steady-state converter are the high-frequency transformer T/F2 , the diode D2 ,

Fig. 2.

Detailed schematic of the SPGD.

Fig. 3. Identication of (a) start-up and (b) steady-state converters of the self-powered gate driver.

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Fig. 4.

Detailed circuit schematic of the MOSFET with the integrated controller.

and the output capacitor C2 . A silicon MOSFET, M1 , with an integrated controller is employed as the main switch for the steadystate converter. It must be noted that this integrated switch is able to operate when the drain-source voltage of the MOSFET exceeds a certain value as this is determined by the manufacturer. Once the drain-source voltage across the MOSFET exceeds this certain limit, the integrated controller is enabled and no external duty-ratio controller is required. A detailed functional block diagram of the MOSFET with the integrated controller, as released by the manufacturer, is shown in Fig. 4. It basically consists of an n-type MOSFET, which is integrated with a dedicated control circuit. The control circuit is mainly denoted with blocks in conjunction with several logic gates in Fig. 4. In this gure, the DRAIN (D) and the SOURCE (S) connections are shown, while two additional connection points are also illustrated. The ENABLE/UNDERVOLTAGE pin enables and controls the switching process of the MOSFET. It is also able to terminate the switching process if a current greater than a threshold current is drawn from this pin. An external capacitor is connected to the BYPASS/MULTIFUNCTION pin in order to keep the internally generated voltage of 5.85 V constant. Depending on this capacitor value, the threshold current which has been mentioned previously can also be set to a certain value. The connectivity of this MOSFET in a yback converter with the integrated controller is shown in detail in Section III-A. In Fig. 3 the IC driver and the optocoupler are also depicted. Diode D3 is connected in such a way that even though the IC driver is supplied both from the start-up and the steadystate converters, the optocoupler is only supplied by the steadystate one. The reason for this is that during the start-up process the optocoupler is not utilized, and hence it does not require a power supplied. On the contrary, under the normal operation of the SPGD, the optocoupler, which optically isolates the signals

from the microprocessor from the SPGD, is supplied by the steady-state converter. The detailed circuit schematics of the optocoupler and the IC driver are depicted in Figs. 5 and 6, respectively. Both the optocoupler and the IC driver are basically totem poles employing MOSFETs. The only difference is that the optocoupler is optically isolated as shown in Fig. 5, where the input stage consists of a light-emitting diode and an integrated photodetector which do not require any external power supply. Thus, the microprocessor signals are isolated from the main circuit. On the contrary, the input of the IC driver is not isolated with respect to the output. However, the IC driver is able to supply high output currents (in the range of few tens of amperes) which are needed if fast switching speeds are required. It is clear that both components are necessary to obtain a stable system operation with very fast switching speeds. In order to clarify the way that the negative supply voltage Vss and the reference ground are connected to the optocoupler and the IC driver, these two points are also denoted in Figs. 5 and 6. Thus, in conjunction with Fig. 1 and with Figs. 25, the ground point (drawn with a small up-side down triangle) and the point where the supply voltage Vss is connected are the same for all these gures. Figs. 79 show the three main operating states of the SPGD. In these gures, the parallel networks of the resistor and the speedup capacitor (Rpm , Cgm and Rp aux , Cg aux ) which are connected to the gates of the SiC JFETs are also shown. Assuming that the main normally on SiC JFET Jm is connected to a direct voltage source Vdc as shown in Fig. 7, the short-circuit current is owing both through Jm and Jaux (bold lines in Fig. 7). Both of these SiC JFETs are normally ON devices and it is obvious that without any negative gate-source voltage supply they are kept in the ON state. The steady-state converter is inactive during this state, because the MOSFET M1 with the

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Fig. 5.

Detailed circuit schematic of the optocoupler.

Fig. 8.

Operating state of the start-up converter.

Fig. 6.

Detailed circuit schematic of the IC driver.

Fig. 7.

Short-circuit current paths during the start-up process of Jm . Fig. 9. Start-up sequence of the SPGD.

integrated control circuit requires a certain voltage across it in order to start operating. A detailed schematic showing the components which are involved in the operation of the start-up converter is depicted in Fig. 8 with bold lines. The transformer T/F1 , the diode D1 , and the capacitor C1 are involved in this state. The short-circuit currents IJ m and IJ aux owing through the main and the auxiliary SiC JFETs, respectively, are also indicated with small arrows in Fig. 8. A very low voltage drop across the primary winding of T/F1 and Jaux is caused due to IJ aux . Considering that the turns

ratio of T/F1 is very high (e.g., 1:100 or higher), the voltage which appears across the secondary winding is also expected to be high. The diode D1 is forward biased and hence the capacitor C1 is charged up to a certain voltage level which equals the voltage across the secondary winding of T/F1 . The IC driver is directly supplied from the output of the start-up converter, Vsu , while the same voltage is directly supplied to the gate of the auxiliary SiC JFET Jaux . As has been already mentioned

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Fig. 10.

Operating state of the steady-state converter.

earlier, the input signal to the IC driver is low, and the output of the driver also equals its low-input voltage. As a consequence, Jm is turned OFF, as soon as the absolute value of Vsu exceeds the absolute value of the pinch-off voltage of Jm . Similarly to this, Jaux is also turned OFF when Vsu becomes less negative than its pinch-off voltage. It is, therefore, obvious that the drainsource voltage across Jm and Jaux equals the direct voltage Vdc . Even though the optocoupler is disconnected in this operating state, the input signal to it is kept in the low state. Thus, when the optocoupler is supplied by the steady-state converter, the SiC JFETs will continue to be in the OFF state. A schematic of the theoretical performance of the SPGD is shown in Fig. 9. Assuming that the direct voltage is applied across Jm at t1 , the rst and third traces of Fig. 9 show the short-circuit currents through Jm and Jaux , respectively. From the third trace of Fig. 6(a), a lower slope of IJ aux is observed due to the series connection of the primary winding of T/F1 with Jaux . The fourth and fth traces of Fig. 9 depict the output voltages of the start-up and steady-state converters, respectively. A certain time is required in order to magnetize the transformer T/F1 and thus the output voltage Vsu across C1 starts to appear at t2 . The short-circuit current IJ m is turned OFF at t3 , when Vsu equals the pinch-off voltage of the main SiC JFET Jm . If it is assumed that the two SiC JFETs have different pinch-off voltages, especially Jaux has a less negative one, it is turned OFF at t4 as shown in Fig. 9. Finally, at t5 , the drain-source voltage of Jm equals the dc voltage Vdc . As soon as the drain-source voltage of Jm equals the direct voltage Vdc , the steady-state converter is able to operate and constantly supply a negative output voltage Vss . Even though the voltage across the MOSFET M1 with the integrated controller is higher than the limit voltage which allows it to operate, a delay time might occur. This delay time might be caused by the soft-starting feature of M1 . The steady-state converter starts supplying the output voltage at t6 , while the nal value of Vss is reached at t7 . It is upon the design requirements of the specic application to decide about the value of Vss . A circuit schematic

of the steady-state converter operation is shown in Fig. 10 with bold lines. As already mentioned, the steady-state converter is basically a low-power yback converter. When the steady-state converter operates, the output voltage of the start-up converter Vsu starts increasing to zero at t6 while Vsu equals 0 V at t8 as shown in the fourth trace of Fig. 9. Moreover, diode D3 is also forward biased in this case and both the IC driver and the optocoupler are supplied by Vss . The auxiliary SiC JFET Jaux is still kept in the OFF state, while the main SiC JFET Jm is now able to switch. It can be seen from Fig. 9 that the main JFET starts switching at t9 . The last trace of this gure shows the gate-source voltage of Jm , while the corresponding switching curves for the JFET current and the drain-source voltage are presented in the rst and second traces, respectively. Considering the analysis presented so far, it is clear that the proposed SPGD is able to operate as a protection circuit against the shoot-through currents, on the one hand, while on the other hand it is employed as a normal power supply for the gatedrive unit. Moreover, it is worth to mention that the choice of the SPGD parameters must be made with care in order to ensure a reliable and stable operation. A detailed analysis of the parameter choices is presented in the next section. III. EXPERIMENTAL RESULTS In order to experimentally investigate the performance of the SPGD, two sets of measurements were performed. The rst set of measurements deals with the stand-alone investigation of the SPGD, while the second one has been done when the SPGD is employed in a half-bridge converter. However, Section III-A shows the choice of the SPGD parameters, which are crucial for the reliable operation. The SiC JFETs which have been used for the experimental verication of the SPGD are the so-called depletion-mode vertical-trench JFETs (DMVTJFET). A graphical illustration of the cross-section of this device is shown in Fig. 11. Samples of this certain design rated at 1200 V and 27 A are commercially available and they have been considered in the current investigation. The pinch-off voltage of this SiC JFET equals approximately 6 V, while the reverse breakdown voltage of the gate is in the range from 19 to 28 V. Typical transfer characteristics of this device which were measured at various gate-source voltages are illustrated in Fig. 12. Finally, it is worth to mention that compared to other JFET designs the DMVTJFET has no antiparallel body diode, but there is still the possibility for reverse current ow through the channel. A. Choice of the SPGD Parameters In order to make the operation of the SPGD reliable and stable, a special effort on selecting various design parameters must be made. Especially, the start-up converter must be designed with care. Without the start-up converter, the short-circuit currents cannot be turned OFF, and thus, the steady-state converter is also not able to operate. The start-up converter must be able to turn OFF both the main and auxiliary JFETs for a certain time until the steady-state converter starts. This practically means that a certain amount of energy must be supplied by the start-up

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Fig. 13. Fig. 11. Graphical illustration of the cross section of the depletion-mode vertical trench JFET.

Detailed schematic of the start-up converter.

circuit currents must be kept as low as possible, the voltage drop across L1 is also low. Consequently, in order to obtain an adequate output voltage, Vsu which turns OFF the JFETs properly, a very high turns-ratio value for T/F1 is required. The adequate output voltage Vsu corresponds to a value which is less negative than the pinch-off voltage of the JFETs, and thus, it is adequate to turn OFF both Jm and Jaux . If, on the other hand, the turns-ratio value is low, a signicantly higher short-circuit current is needed in order to supply a certain output voltage. As already mentioned previously, the steady-state converter requires a certain time in order to start operating. During this time delay, the start-up converter must be able to supply a certain amount of energy to the gate-source junctions of Jm and Jaux in order to keep them in the OFF state. If L1 is the inductance of the primary winding of T/F1 and IJ aux is the short-circuit current owing through Jm , the stored energy in the transformer is given by EL 1 = 1 2 L1 IJ aux . 2 (1)

Fig. 12. Static transfer characteristics at various gate-source voltages for the SiC DMVTJFET.

Similarly, if C1 is the output capacitor and Vsu is the output voltage, the total stored energy in this capacitor is given by EC = 1 2 C1 Vsu . 2 (2)

converter to the gates of Jm and Jaux . The presented analysis is based on the simplied circuit schematic of the start-up converter shown in Fig. 13. The on-state resistances of the main and auxiliary JFETs rJ m and rJ aux , respectively, are also shown in this gure with the dashed lines. Moreover, the resistance of the primary winding of the transformer rL 1 is also shown. Assume that the on-state resistances of Jm and Jaux are equal. (In the future, Jm would be a large device while Jaux would be a small device.) It is obvious that the total resistance of the primary winding of the transformer and Jaux is higher than rJ m . It is, therefore, clear that IJ m which is owing through Jm is slightly higher than IJ aux . Hence, the voltage drop across the primary winding of T/F1 equals the difference between the voltage drop across Jm and the voltage across Jaux . Keeping in mind that typical values of the on-state resistance of the JFETs are in the range of few tens of millohms, and that the short-

Assuming that there are no losses in the converter, EL 1 must be equal to EC and thus a relationship between the output voltage Vsu and the short-circuit current IJ aux is obtained. Accordingly, Vsu = L1 IJ aux . C1 (3)

A graphical presentation of (3) is shown in Fig. 14. This gure actually shows the variation of the output voltage Vsu of the start-up converter with respect to the value of the output capacitor C1 for various short-circuit currents IJ aux . The gate capacitance Cg of the SiC JFETs is also shown with dashed lines in Fig. 13. In order to turn OFF the JFET a certain amount of energy is required to be stored in the gate capacitance. There is a minimum required value for this energy

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Fig. 14. Output voltage of the start-up converter for various output capacitors and short-circuit currents. TABLE I PARAMETERS OF THE START-UP CONVERTER

which is given by Qg Vpi (4) 2 where Qg is the total charge of the gate capacitance and Vpi is the pinch-off voltage of the JFET. Even though the pinch-off voltage is the gate-source voltage at which the turn-off process of the JFET starts, a more negative gate source is required in order to properly turn OFF the device. Taking into account this fact, and in conjunction with Fig. 14, it is clear that the choice of the output capacitor C1 must be made with care so that, on the one hand, an adequately negative voltage Vsu is supplied to the gates of Jm and Jaux , and that, on the other hand, the start-up converter is able to supply a certain amount of energy for a certain duration. This amount must be signicantly higher than Eg , m in , while the short-circuit current IJ aux must be kept between reasonable limits. If this current is too high, it might cause thermal destruction of the device without letting the SPGD to start operating. An additional reason to why Ec must be signicantly higher than Eg , m in is that losses caused in the gate-source junction as such, but also in the gate circuit must be taken into consideration. Table I summarizes the parameters of the start-up converter. Taking into account the analysis of the start-up parameters so far and considering the results shown in Fig. 14, the capacitance value of C1 can be chosen assuming a certain shoot-through current IJ aux and a certain turns-ratio of T/F1 . In order to avoid any thermal destruction of the JFETs, IJ aux has been chosen to be equal to approximately 15 A. This practically means that the Eg , m in =

shoot-through current which ows through Jaux equals approximately half the rated current of the component. Thus, Jaux is kept far from its thermal limits. In a similar way, the current owing through Jm also equals half the rated current. Considering that the typical value for the pinch-off voltage of this particular JFET design equals 6 V, and taking into account Fig. 14, a value of 100 nF has been chosen for C1 . Consequently, the output voltage Vsu of the start-up converter equals approximately 9 V, which is an adequate voltage to turn OFF the JFETs. As can be seen from Fig. 14, there are basically several combinations of C1 and Ij aux which result in a certain output voltage Vsu . However, as already mentioned, the energy which is stored in C1 must be adequate in order to compensate for the losses caused in the gate-source junction as such, but also in the external gate circuit. Due to the difculties in measuring these very low power losses in the gate, experiments using various values of C1 were performed in order to choose the best-performing value of the output capacitor. If Ij aux had been chosen to be equal to 5 A and assuming the same turns ratio of T/F1 , then as it is clear from Fig. 14 the output voltage Vsu of the start-up converter would not be adequate in order to turn OFF both SiC JFETs and at the same time supply an adequate energy to the devices. Finally, it must be noted that Ij aux can be set at a certain value by properly adjusting the start-up resistor, Rstart -up . As for the start-up converter, an investigation concerning the choice of the parameters of the steady-state converter has been performed. The steady-state converter has been designed assuming an input voltage of Vdc = 500 V and an output voltage equals Vss = 30 V. A detailed schematic of the steady-state converter, which is a yback converter from 500 to 30 V is shown in Fig. 15. A silicon MOSFET with an integrated controller is employed as the main switch of this yback converter as already mentioned in Section II. Apart from the drain (D) and the source (S) connections of the MOSFET (see Fig. 15), there are also two more input ports (EN and BP as they are called by the manufacturer). The rst input EN is used in order to sense the output voltage, and thus, the duty ratio is properly controlled. In particular, the output voltage of the converter is sensed by means of an optically controlled transistor Tph and a zener diode Dz . When the output voltage Vss exceeds the zener voltage of Dz , Tph is turned ON and thus an input signal to EN is sent. Hence, the switching cycles of M1 are overlapped until the output voltage Vss becomes lower than the zener voltage of Dz . On the other hand, a capacitor C3 is connected to the input port BP, which is responsible for stabilizing the auxiliary voltage in the integrated switch. The parameters of the steady-state converter are shown in Table II. B. Stand-Alone Investigation The SPGD has been experimentally tested when it is employed as the gate driver of a single SiC JFET which is directly connected to a direct voltage. A picture of the SPGD prototype is illustrated in Fig. 16. Fig. 17 illustrates a schematic of the test circuit for the stand-alone operation. A 1200 V/55 A IGBT in conjunction with a start-up resistor Rstart -up was employed

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Fig. 15.

Detailed schematic of the steady-state converter. TABLE II PARAMETERS OF THE STEADY-STATE CONVERTER Fig. 16. Experimental circuit prototype of the SPGD.

Fig. 17.

Schematic of the test circuit for stand-alone operation. TABLE III PARAMETERS OF THE STAND-ALONE TEST CIRCUIT

in order to emulate the start-up process as shown in Fig. 13. The start-up resistor has been selected in such a way that the shoot-through current will be limited, while the IGBT emulates the operation of a circuit breaker (or a relay). The IGBT is controlled using a special control circuit, which turns the IGBT ON for a certain time period and thus, the short-circuit current starts owing through the main SiC JFET Jm . The SPGD also starts operating as described previously. The reason for that a special start-up circuit (IGBT and start-up resistor) is employed is to emulate a standard start-up circuit containing an inrush-current limiting start-up resistor (which is short-circuited during normal operation). Table III summarizes the parameters of the test circuit for stand-alone operation. Figs. 1821 show various measured quantities during the start-up process. In particular, Fig. 18 illustrates the shootthrough current (light-pink color) which is turned OFF in approximately 20 s after the start-up process starts. This current

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Fig. 18. Measured gate-source voltage of the main SiC JFET Jm (purple line, 10 V/div), drain-source voltage of Jm (dark-pink color, 200 V/div), shootthrough current IJ m (green line, 10 A/div), short-circuit current ows through Ja u x , IJ a u x (yellow line, 10 A/div) and the sum of the shoot-through currents (light-pink color, 10 A/div), (time base 10 s/div).

Fig. 20. Measured supply voltage of the SPGD (pink line, 10 V/div), drainsource voltage of the main SiC JFET Jm (purple color, 500 V/div), shootthrough current IJ m (green line, 10 A/div) and shoot-through current IJ a u x (yellow line, 10 A/div), (time base 5 ms/div).

Fig. 19. Measured gate-source voltage of the main SiC JFET Jm (purple line, 10 V/div), gate-source voltage of the auxiliary SiC JFET Ja u x (dark-pink color, 10 V/div), shoot-through current IJ m (green line, 10 A/div), short-circuit current ows through Ja u x (yellow line, 10 A/div) and the sum of the shootthrough currents (light-pink color, 10 A/div), (time base 10 s/div).

Fig. 21. Measured gate-source voltage of the main SiC JFET Jm (yellow line, 10 V/div), gate-source voltage of the auxiliary SiC JFET Ja u x (purple color, 10 V/div), shoot-through current IJ m (green line, 10 A/div) and drain-source voltage of Jm (pink line, 200 V/div), (time base 5 ms/div).

equals the sum of the short-circuit currents owing through both Jm and Jaux . The short-circuit current IJ aux which ows through the auxiliary SiC JFET is shown with the yellow line in the same gure, while IJ m is illustrated with the green line. It is obvious that the speed of IJ aux is less than IJ m due to the inductance of the primary winding of T/F1 which is connected in series with Jaux . Regardless of this phenomenon, both currents are turned OFF very rapidly after the start-up process starts (15 s for Jm and 20 s for Jaux ). The gate-source voltage of Jm is shown with the purple line in Fig. 18, while the drain-source voltage of the same device is presented with the dark-pink line. The gate-source voltage is basically equal to the output voltage Vsu of the start-up converter. It is clear from Fig. 18 that the SPGD provides negative gate voltages very rapidly after the start-up, and thus, the short-circuit currents through the SiC JFETs are no longer owing. Additional experimental results dealing with the start-up process are shown in Figs. 1921. The gate-source voltage of Jaux is illustrated with the dark-pink color in Fig. 17. It is obvious from the experimental results that during the start-up process Vgs , aux equals Vsu .

Fig. 20 presents the whole start-up process including the starting process of the steady-state converter. The dark-pink line in Fig. 20 shows the supply voltage to the IC driver and the optocoupler. As already mentioned, the steady-state converter requires a certain input voltage in order to start its operation. Even though the input voltage to the steady-state converter is high, a delay on the starting of this converter is observed in Fig. 20, which approximately equals 25 ms. This is caused due to the soft-start feature of the MOSFET with the integrated controller. Thus, when the SPGD is enabled, the output voltage equals Vsu for a certain time (approximately 25 ms), while after this the output equals Vss which has been adjusted to Vss = 30 V. It must be noted that the drain-source voltage of Jm is shown with the purple line in the same gure. Finally, Fig. 21 shows the gate-source voltages of Jm and Jaux (yellow and purple lines, respectively). Even though the output voltage of the steady-state converter has been adjusted at Vss = 30 V, the measured gate-source voltages are slightly less negative. The reason for this is that the reverse breakdown voltages of the gates of the SiC JFETs are less negative than 30 V. Thus, the voltage drop across the gate-source junction equals the reverse breakdown voltage of the gate, while the

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TABLE IV PARAMETERS OF THE HALF-BRIDGE TEST CIRCUIT

Fig. 22.

Schematic of the half-bridge converter with the SPGDs.

Fig. 23. Experimental setup of the diodeless half-bridge converter where the SPGDs are employed.

voltage across the parallel network of Rpm and Cgm (see Fig. 10) is equal to the difference between the reverse breakdown voltage of the gate and the supply voltage of 30 V. The choice of 30 V supply voltage is based on experience regarding switching speed and noise immunity. As Rpm has a high value, the negative gate avalanche current is limited to values that are not harmful. Last but not the least, it is worth to mention that the measured steady-state power consumption of the SPGD when Jm and Jaux are both kept in the OFF state equals 0.37 W. This power consumption of the SPGD has been measured using a power meter connected on the dc-link side. The dc-link input voltage Vdc and the input current are both acquired, and thus, the power consumption is measured. C. Experimental Investigation in a Half-Bridge Converter The second set of measurements was performed on a halfbridge converter as shown in Fig. 22. In this case, the halfbridge converter is operating as a step-down dc/dc converter with open-loop output voltage control. The main idea of these measurements is to show that the proposed SPGD is properly switching when it is employed in a realistic power converter. A picture of the experimental setup is shown in Fig. 23.

Two normally ON SiC JFETs Jm 1 and Jm 2 are employed in the half-bridge converter as the upper and lower switches, respectively, while two individual SPGDs drive the two SiC JFETs. It is obvious from the schematic shown in Fig. 22 that there are no antiparallel diodes connected across the SiC JFETs. In the diodeless operation of the half-bridge converter, the reverse current ows through the channel of the SiC JFET [17], [42], [44]. As illustrated in Fig. 22, the start-up converters are directly connected across the main SiC JFETs as illustrated with the bold lines. On the other hand, both steady-state converters are supplied by the dc-link voltage Vdc . As in the stand-alone investigation, a start-up IGBT and a start-up resistor are also used in this case in order to emulate the inrush-current limiting startup circuit of any standard converter. Additionally, a mechanical relay is connected in parallel to the start-up resistor in order to bypass it during the steady-state operation of the converter. The parameters of this circuit are summarized in Table IV. As already shown in Figs. 20 and 21 in the previous section, the steady-state converter requires a certain time in order to start operating. This time is approximately equal to 25 ms. After this time period, the SPGD supplies the nominal output voltage, which has been adjusted to Vss = 30 V. However, the gatesource voltages that are illustrated in Fig. 24 are somewhat less negative than 30 V due to the reverse breakdown voltage of the gates. This is caused due to the fact that the reverse breakdown voltages of the gates are less negative than 30 V. A detailed description of this phenomenon has been already analyzed in the previous section. Since the output voltage of the SPGD equals 30 V, the mechanical relay can be closed and thus Rstart -up is bypassed. Finally, PWM signals can be sent to the drivers and the two SPGDs are able to switch. The whole control process for the half-bridge converter has been implemented using a digital signal processor (Texas Instruments TMS320F28335).

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Fig. 26. Typical dc/dc boost converter with a high input impedance due to the inductor L b .

Fig. 24. Measured gate-source voltage of the upper SiC JFET Jm 1 (pink line, 10 V/div), gate-source voltage of the lower SiC JFET Jm 2 (yellow color, 10 V/div), shoot-through current IJ m measured on the drain of Jm 1 (green line, 10 A/div) and on the drain of Jm 2 (purple line, 10 A/div), (time base 10 ms/div).

IV. LIMITATIONS OF THE SELF-POWERED GATE DRIVER The concept and the design of the proposed SPGD in conjunction with a detailed experimental investigation have been presented so far. It is shown that the normally ON problem of the SiC JFETs can be solved by employing the SPGD design. Regardless of the outstanding performance of the SPGD as described in the previous section, there are three limitations of the SPGD operation which must be taken into account. The rst limitation deals with the value of the shoot-through current which ows though the main and auxiliary SiC JFETs. Even though this current might be adjusted by properly selecting the value of Rstart -up , the selection must be done considering two issues. On the one hand, the shoot-through current must not be excessively high because it might thermally destroy the SiC JFETs, and may have an adverse effect on the supply from which the current is taken, especially if it is a battery. On the other hand, if the shoot-through current is low, the stored energy Ec on the output capacitor of the start-up converter will also be low. Thus, it might be possible that Jm and Jaux will be both accidentally turned ON before the steady-state converter starts operating. Moreover, as has been shown in Fig. 14, the output voltage of the start-up converter also depends on the shoot-through current of Jaux . For instance, if the shoot-through current IJ aux equals 5 A, then in order to reach the desirable output voltage Vsu , a very low capacitor value is required. However, the stored energy in this case might not be sufcient to keep Jm and Jaux in the OFF state for a certain time interval. The second limitation is related to the range of the power electronics converters where the SPGD can be efciently employed. A basic requirement in order to activate the start-up converter of the SPGD is a rapidly increased shoot-through current. This practically means that the SPGD is only able to operate when the input impedance is sufciently low. Assuming, for instance, a typical dc/dc boost converter as shown in Fig. 26, the input impedance of the circuit is high due to the inductor Lb which is connected on the input of the converter. Thus, the slope of IJ aux is slow and the time needed for activating the start-up converter is longer compared to the low-impedance case. A long activation time for the start-up converter might result in thermally destruction of the devices due to the shoot-though current. On the contrary, in the case of an inverter (or half-bridge converter as previously shown) the input impedance is low and thus a rapidly increased shoot-through current directly ows when the circuit breaker is closed.

Fig. 25. Measured gate-source voltage of the upper SiC JFET Jm 1 (pink line, 10 V/div), gate-source voltage of the lower SiC JFET Jm 2 (yellow color, 10 V/div), drain current of the upper SiC JFET IJ m 1 (green line, 5 A/div), (time base 10 ms/div).

Fig. 24 shows the gate-source voltages of both JFETs during the whole start-up and steady-state processes of the SPGDs. It can be seen that the shoot-through currents are turned OFF very rapidly. The time delay for the steady-state converter is also clear from this gure. Finally, after a certain time period, which can be adjusted by the user, the SPGDs are switching. The operating time intervals of each converter are indicated with arrows in Fig. 24. It must be noted that in order to avoid any high transient current when the switching process starts, the duty ratio of the upper SiC JFET is slowly increased from 1% to its nal value which has been set to 50%. An oscilloscope screenshot where the duty ratio equals approximately 25% is illustrated in Fig. 25. The two upper waveforms in Fig. 25 depict the gate-source voltages of the upper and lower JFETs. It is clear that the operation of these two devices is complementary, while a short blanking time has been also set (250 ns) so that any shoot-through phenomena will be eliminated. Finally, the lower waveform (green color) in Fig. 25 shows the drain current of the upper JFET Jm 1 .

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The last limitation deals with the shut-down process of the SPGD. Considering, for instance, a phase leg of an inverter, when the system is shut down, the stored energy in the dc-link capacitor must be dissipated before the power to the gate driver disappears. The energy can either be dissipated to the load or to a separate discharging resistor. In the case where the power to the gate driver disappears before the dc-link capacitor is fully discharged, there might be a short circuit through the JFETs which may thermally destroy them. V. CONCLUSION In this paper, a concept along with a circuit solution to the normally ON problem of the SiC JFETs is presented. The proposed SPGD is able not only to clear the short-circuit current through the SiC JFETs, but also to supply the gate-drive circuit with an appropriate negative voltage during steady-state operation without the requirement of an external power supply. It basically consists of two separated converters: the start-up converter which handles the short-circuit currents and the steady-state converter which supplies an appropriate steady-state negative gate voltage. A certain value of short-circuit current is necessary in order to activate the start-up converter. It has been shown that this current does not need to be excessively high if the passive components of the start-up converter are properly chosen. Thus, the devices are kept far from any thermal destruction due to the high short-circuit current. From the experiments, it is clear that the activation short-circuit current equals approximately half of the rated device current. Moreover, the output voltage of the steady-state converter might be adjusted to the desired level according to the design requirements. The performance of SPGD has been investigated on a stand-alone circuit and when it is employed in a half-bridge converter. From the measurements, it is shown that using the SPGD, the short-circuit current is cleared within approximately 20 s. Additionally, it is experimentally shown that the SPGD is able to properly switch the normally ON SiC JFETs employed in a half-bridge converter without any external power supply. REFERENCES
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Dimosthenis Peftitsis (S03) was born in Kavala, Greece, in 1985. He received the Diploma in electrical and computer engineering from the Democritus University of Thrace, Xanthi, Greece, in 2008. Since 2008, he has been working toward the Ph.D. degree in the Electrical Energy Conversion Lab (E2C), KTH Royal Institute of Technology, Stockholm, Sweden. In 2008, he worked on his diploma thesis at ABB Corporate Research, V aster as, Sweden, for six months. His research interests include gate and base driver design for SiC JFETs and BJTs, as well as protection circuits for normally ON SiC JFETs.

Jacek Rabkowski (M10) received the M.Sc. and Ph.D. degrees in electrical engineering from the Warsaw University of Technology, Warsaw, Poland, in 2000 and 2005, respectively. He joined the Institute of Control and Industrial Electronics, Warsaw University of Technology, as an Assistant Professor in 2005. In 20102011, he has been with Electrical Energy Conversion Lab (E2C), KTH Royal Institute of Technology, in Sweden, as a Guest Researcher. His research interests include novel topologies of power converters, PWM techniques, drive units, and converters with SiC devices.

Hans-Peter Nee (S91M96SM04) was born in V aster as, Sweden, in 1963. He received the M.Sc., Licentiate, and Ph.D. degrees in electrical engineering from the Royal Institute of Technology (KTH), Stockholm, Sweden, in 1987, 1992, and 1996, respectively. In 1999, he became a Professor of power electronics at KTH, where he currently serves as the Head of the Electrical Energy Conversion Laboratory. His current research interests include power electronic converters, semiconductor components, and control aspects of utility applications, such as exible ac transmission systems and high-voltage dc transmission, and variable-speed drives. Dr. Nee has been the recipient of several awards for his research. He is an Associate Editor of the IEEE TRANSACTIONS ON POWER ELECTRONICS, and was on the board of the IEEE Sweden Section for several years, serving as its Chairman during 20022003. He is a member of the European Power Electronics and Drives Association, involved with the Executive Council and the International Scientic Committee.