CHAPTER - 4 CENTRAL PROCESSING UNIT (C P U) The block diagram of the card is as in T 12E. 4. 1.

The Central Processing Unit is the heart of the Exchange as it is the Main Controlling Processor and common for the whole exchange. The microprocessor is the 16 bit HITACHI Chip HD 68000 working at 8 MHz. This 64 pin IC has 23 address and 16 data lines. It has 8 numbers of 32 bit data registers and 7 number of 32 bit address registers and can address 16-megabyte linear space of memory. The main oscillation clock is 15.97Hz, which is divided by 2 for processor clock of 7.98 MHz and further divided by 2 to 3.99 MHz for peripheral units. This card is housed in CME Rack slots 1 and 32. The card has a PROGRAMMABLE TIMER 8253, which has three 16 bit counters, one for operating system and the other two for application. The counters work on Mode 2 and the reference clock is 244.6 kHz (4 microsecs). Interrupt IRQ5 is used for system while IRQ4 and IRQ3 are used for user.

The MASTER TIMER consists of a real time clock LS 1 chip 58321 and connected to the processor and sets and reads the timer data by using specified software. The counter provides seconds, minutes, hours, day, week, month, and year. There are provisions of 12hour/24hour switches and leap year function. The counters have the device addresses 7E8020H to 7E8022H. The timer interrupts are having addresses 7E8024H to 7E8026H. Master Timer addresses are 7E8400H to 7E8402H. The IPL/OS ROM is of 64KB space from 000000H to 00FFFFH and is made of 2 numbers of 27256 ICs. This is accessed in RESET mode. In other cases, this space is used as RAM space. Again FE0000H - FEFFFFH is the ROM area. The Memory Protection Circuit is used to divide the memory space in 4096 blocks of 2K words (4K Bytes) each and sets write protection in every block in memory. When the memory protection is specified, the memory key and the protection key if both are kept at '1' enable only READ operation. In any other combination, read and write operations are possible. These keys are read or written by the user program. In this memory protect condition access from DMA is not allowed. Access is possible by the CPU. The Switch Register reads the definition data for the system and DIP switches data from MISCA card and keeps them for software. The register width is 16 bit. It checks the CPU

number, CPU simplex /duplex status and IPL I/O number from the motherboard and slave/master status single/multiple CPU, IPL unit simplex/duplex, IPL type, fixed / switched system from the MISCA. There is an Invalid /valid monitor switching front panel of the CPU card. The interruptions can be due to Internal cause e.g. illegal instructions which trap instructions in CPU or external calls e.g. RESET bus error and external signal exceptions. 68000 have 7 levels of exception priority with 7th level being of highest priority (NMI). The interruption control circuit consists of the priority encoder and Programmable Interruption controller. External Interrupt vectors are used for vector Number 240 to 255 with address 3C011 - 31`CH. Internal vectors are from 00 to 63 with addresses 000H to 0FFH. There is an Emergency Control circuit which helps in system recovery if supporting software fails to do so. This is done by performing system initialisation. For this EMA, Initial Program Loading (IPL) and OS ROM are used. The EMA has 4 constituents - EMA counteract F/F, ERR Detection Timer (TF) and ERR Control Timer (TE). The EMA counter counts the number of EMA activation. The counter value, which is called the EMA store, can be read or written with the supported program. This counter updates counter value by transferring data of current value from the ACT to SBY side every 130 micro sees. The ACT F/F indicates which CPU is in active condition. The ACT CPU controls the whole system. The ED and EC timers are made up of the same circuits. Usually this circuit works as ED timer and during emergency control operation only EC timer-works. The over flow time of TE and TF is approximately one second. The memory map is shown in T12E. 4.2.

The memory space is 16 MB (000000 to FFFFFF). There are 4 portions in the memory, dynamic data is kept in 8 MB RAM area (000000 to 7FFFFF). A common memory area is there for data transfer between the individual units and CPU. The CCM common memory area is of 2 MBs (C00000 to DFFFFF). The DTC common memory and time switch common memory is of 64-KB

area each and the spaces are F20000 to F2FFFF and F30000 to F3FFFF respectively. The I/O devices for 68000 are memory mapped and so the user I/O and system I/O have 64 KB area each spaced respectively from FC0000 to FCFFFF and FD0000 to FDFFFF. The 64-KB area FE0000 to FEFFFF is kept for ROM. Thus C00000 to FFFFFF area of 4 MB is kept for ROM/CM / SIO. Between 8 MB RAM area and this 4-MB area another 4MB area from 800000 to BFFFFF is reserved area for RAM. The address of I/O unit consists of device address and operation and instructional block. For normal I/O control function A1 to A4 is for OP codes while A5 to A23 are for device addresses. But for DMAC, I/O control functions, A1 to A5 and A6 to A8 are for OP codes, while A9 to A23 are for device addresses. In the duplex system, one CPU controls the other and this is called MATE CONTROL. The CPU on Active mode gets the control. The Mate Control communication is exchanged via the Data Transfer Card (DTC) as per diagram T12E. 4.3

The system activation and system reset operation are done through Initial Program Load (IPL), Emergency control operation and reset operations. These controls are executed by the firmware kept in ROM depending upon the positions of the four keys on the front panel of the CPU card EMA SUP to make EMA operation valid or invalid, EMA ACT to activate EMA, SYS RST to provide Hardware reset instruction', and OFF LINE MONITOR to monitor the system.

The description of switch settings is as per T12E. 4.4

There are three indicating LEDs RUN (Green) to indicate CPU machine cycle execution, ACT (Green) to show the status of the CPU ( ACT or SBY ) and SYS0 (Red) to show system unit down condition.

DATA TRANSFER UNIT (DTC) This card is placed in CME rack slot 15 and the block diagram is shown in T12E.4.5 is used only in NE 1200/1300 as it helps in inter communication between two CPUs. It has a common memory unit connected to two processor buses. This card has three serial ports for connecting RS 232 C interfaces. In addition to these there is a FDD selector which selects and connects the duplex FD controller from IOC-2package to the floppy discs. The serial port operation is same as IOC-2 card. This PCB is powered from both systems 0 and 1.

Fig. 4.5 The common memory size is 8K words and address from 790000 to 791FFF.When memory access requests is sent from both CPUs, a conflict control operation is performed by the DTC by using hardware. In such condition, the access request from the preceding system is attended first. If both the requests are synchronous the copy 0 request will be served first. At that time copy 1 will stay in wait mode. The call mate signal between the two CPUs transfer data via the common memory. This card has 4 front end connectors, 34 pin CNA for memory operation and 16 pin CNB,CNC and CND for serial ports. This PCB can be connected to a terminal of either DCE or DTE type. INPUT OUTPUT CONTROL 2 (IOC 2) This card is placed in cme rack slots 02 and 31 and is used to connect maximum 4 Nos. of 5 1/4 floppy discs and 3. RS 232C interface for connecting one PC and 2 printer. The I/0 devices are directly connected to CPU Bus by 1002 in NE 1100 model. But in NE 1200, the device is connected via DTC card.

The card has a 34-pin connector CNA for FDD and 3 16-pin connectors for the RS 232 interfaces. It has DMA control with 4 channels of which chl 1 is for FDD, Channels, 2 is kept for hard disk drive (if used) whereas channels 3 and 4 are for memory to memory transfer. MAIN MEMORY A set of 3 cards (in CME slots 03 to 05 and 28 to 30) per CPU provides main memory for the system. These cards contain 256K x 1 DRAM chips and 9 bits (8 for data and 1 for parity checking) make a row. The cards have normally 2MB/PCB but can be expanded to 4MB/PCB to give 12MB maximum capacity. Though the memory can be normally accessed for reading and writing, a write protection function can be activated by the CPU. SELECT BO (SLBO) This card is mounted in CME rack slots 10 and 23 and selects hard disc units. It has a 34-pin connector CNA for common connection and three 20-pin connectors for connection to drives 0, 1 and 2. The selection of a particular Disk unit is under the control of CPU. The connectors are similar to that in DKC card. DISC CONTROL UNIT (DKC) This unit is placed in CME rack slots 11 and 22 and has one card for a control set. It can be connected to 5 1/4 " magnetic disc unit (D K U). The card contains buffer memory (512 Words) with FIRST IN FIRST OUT control. The data transfer between memory and buffer memory of DKC is done via the processor bus under DMA control. The DKC and the Disc connection is of cross configuration in SLBO card and there is a flip-flop in DKC, which selects the route. The data transfer rate is up to 313 Kilo Words /Sec. The DKU can have 4 Discs and 8 Read / Write heads. The disc capacity is 19.9 MB/drive. The disc drive needs +12V in addition to +5V supply. The disc address is according to the cylinder number, head number, and sector number. There are 32 sectors, 8 heads and 306 cylinders. The hardware disc control is achieved by an IC microprocessor D7261A. It controls the DKU and reports to the CPU regarding DKU` state. A 10 MHz oscillator samples the data read from the DKU. The block diagram and connectors are shown in T 1 2E. 4. 6

Fig. 4.6 The power supply to the DKU can be controlled form the active CPU. The POW flip-flop set/reset command can control the power supply to the duplicated DKU. The DKU` cannot be accessed up to 15 secs after the SET order is received. Before resetting the POW F/F the R/W heads must be set in the cylinder numbers 306 - 319. After resetting, the POW F/F is placed in OFF State FIFO reset command resets the FIFO memory. This command must be sent before hardware disc control command. The DMA transfer control flip-flop is reset by TRS reset command. This command is sent when the Read Write system command to be sent to HDC is abnormally finished. The DMAC transfer is stopped after getting this command. There are four front end connectors - 34 pin CNA for common connection, 20 pin CNB, CNC for drives 0 and 1 and 8 pin CND for Power ON OFF. There is one DKU power-on LED. SYSTEM STATUS CHECK CIRCUITS (SSC)

This card is mounted in the CME rack slot 17 and it reports system status e.g. major/ Minor faults, system CPM or SWM failures etc. The card itself displays different status information by several LEDs. Control information is sent / received to / from the LIF under software control via processor bus. The indications are as per T12E. 4.7 The connectors in front of PCB contain 48 V.

LOOP HIGHWAY INTERFACE (L I F)

This card is placed in CME rack slots 14 and 18 and provides communications between multiple units by using loop highway. This card is of two types - the Master LIF (LIF - 01), mounted in the Master Unit and the slave LIF (LIF - 02) mounted in slave unit. The speech path forms a loop highway between the units and need both LIF - 01 and LIF - 02. The LIF - 01 and LIF - 02 are duplicated in Master and Slave unit respectively. The block diagram is in T12E 4.8.

The intercommunication is via 6 X 8 MB/s HWY and the maximum distance between the units is 30 meters. There is a provision of by pass Duplicated Loop to prevent system failure. If dedicated digital line is used, then an interface circuit for, external clocks (CLKD) is needed in LIF-01. Clocks for speech and basic clocks are available from an oscillator in the LIF-01, An ACT/ SBY control circuit checks the other system LIF status. This is placed only in LIF -01. There is an ELASTIC circuit, again only in LIF-01which absorbs phase difference in bits and frames caused by delay on the loop. This is a memory which stores the data sent from the loop and absorbs any phase difference by reading this data at a timing generated by LIF - 01. There is a Pilot Data Detection Circuit (P-DET) in the Fault Detection Circuit (TRODET). The first bit of a frame inserted by LIF - 01 is specified as-pilot data and this is alternately set to '0' and '1'. This sequence is detected by each LIF for checking up correctness of the frames. If five consecutive frames are of the same polarity an error is detected and an Interrupt signal is sent to SSC and the ACTIVE system is switched. The switching circuit of LIF is shown in T12E 4.9

TRODET has a card health Display Circuit, which displays ACT / SBY, Bypass, Input disconnection, Output disconnection and -pilot error. The connection diagram of LIF with TSWC is as per T12E 4.10

TONE SENDER (TNSE CARD) This card is placed in CME rack slots 08 and 25 and generates up to 30 audible signals including idle current pattern. It is connected to the TSW via one 2 Mb High Way. The block diagram is as per T12E 4.11. A SYNCRONOUS DATA LINK CONTROLLER is formed via the TSW using channel 15 of this High Way to have communication between TNS in CME rack and HWIF in LTE rack. This card has also one test pattern generator and detector to send and receive patterns by using channel 13 of above High Way. Test patterns are 55H and AAH in alternate frames. Maximum 15 HWIF can be connected for SDLC (Synchronous Data Link Controller) via GO-AHEAD POLLING SYSTEM. This card uses Z-80 microprocessor. The major components of this card are memory devices and counters. They are described below. TONE ROM (T-ROM): This is a 8K ROM and stores up to 32 types of tone bit pattern and the

lower 8 bits of start and end address of each tone bit pattern. It uses 4K space. INTER ROM (IROM): This stores addresses of the Address RAM which in turn stores the read address of T-ROM and it also contains the upper 4 bits of start and end addresses of each tone stored in T-ROM. It uses 4K space. 240 locations are used to keep A-RAM address for each tone. TNS card memory map is as per T12E 4.12 ADDRESS RAM (A-RAM): It stores read address used for reading tone data from T-ROM. This uses 32 locations, one for each tone. BIT COUNTER (BCNT): It generates a clock signal of 2 MHz or less from the 4MHz clock signal available from TSW.

25 msec COUNTER: It generates a maximum continuation time of 25 msec from BCNT output, for each tone. ADDRESS COMPARATOR: This unit compare start and end address from the TONEROM with a read address available from ARAM after incrementing the later. The ADDER unit does this incrementing. A PARALLEL TO SERIAL CONVERTER: It converts the parallel bit pattern available from T-ROM to the serial form. The maximum frequency deviation allowed for the tone is 1 % and level deviation is +1 dbm. OPERATION OF TONE GENERATOR: Refer T12E 4.10. A T-ROM tone bit pattern address contained in ARAM is updated for each tone once within each frame. An end address for a tone, read from T-ROM / IROM is compared in ACMP with the current read address after incrementing the later in Adder. If the END address is not reached the incremented current address is taken as the next read address. The next address is stored in ARAM. The IROM contains an ARAM address of 240 locations corresponding to a tone for each signal. One byte is read continuously from IROM for 25 msec (200 frames of 125 microsec, once per frame). One cycle of read is completed in 6 sec (25 msec x 240 bytes). As DTMF signal does not have any cadence, the ARAM address is generated from BCNT'S output. The ARAM is accessed for obtaining a T-ROM tone bit pattern locations, address from the IROM. The T-ROM gives a tone bit pattern output from the data saved in these T-ROM locations. The calculation of a T-ROM is independent of an audible tone signal. I/O PORT CONTROLLER: The counter/timer has 4 channels timer/counter for controlling the DMA SDLC and Timer interrupts. The interrupt controller is of Daisy Chain type.

Interruption is generated to Z-80 CPU in mode 2. The DMA controller has a 4 channel control and transfers data between the SDLC and RAM using two channels CH 0 & CH 1. The terminal count is connected to the interruption input terminal of the counter/timer for interrupting the microprocessor. Synchronous Data Link Controller controls communication with the HWIF over a channel ( No :15 ) of the 2Mb/s High Way and transfers data to and from the RAM under the control of DMA. It also connects an interrupt request to the microprocessor via CTC. Normally the SDLC is used in NON-LOOP mode. Loop mode can be set for diagnostics only. The Maintenance Signal Distributor sends a clock signal for loop mode use of SDLC for diagnostics. It also conducts ON-OFF control of the Alarm Indicator LED on the card front panel. The common memory between Tone Sender and the Main CPU of the Exchange is accessed by the former in Byte units and the later in Word units and the Z-80 has got the priority in bus contention control. The memory space is 4 K Bytes. TEST PATTERN: A portion of the TNS has the test pattern '55' and 'AA' generator. These patterns are previously written in the T-ROM. These data patterns are read out alternately frame by frame to be test patterns. TIME SWITCH (TSWC0 / TSWC1) This card is mounted in CME Rack slots 07, 09, 24, 26 and card accommodates forty 2Mb/s serial HWY to and from HWIF (5 Per HWIF), where line or trunk cards are placed. One 2Mb/s HWY is connected to tone card and six 8Mb/s HWY are there for Inter Unit Communication. There is a 2048-multiplexed non-blocking time switching provided in this card. The clocks of 4.096 MHz and 8KHz are supplied to the TNS and HWIF from this card. HWY connection to HWIF is of RS422 serial format. There is 16.384 MHz built-in oscillator and a 5db PAD. The function of the various blocks in the block diagram TI2E 4.13. are described below.

Fig. 13 SERIAL TO PARALLEL CONVERTER (S/P): It converts 2Mb/s serial HWYs to be connected from TNS and HWIF into 9-bit parallel data (8 Bits data + 1Bit parity). It also converts 8Mb/s serial HWY from the LIF into 9 Bit parallel data. S/P consists of LSI equivalent to MSM 6913. MULTIPLEXER (MPX 0,1): Each multiplexer multiplexes a total of 1024 channels 9 bit parallel data including three 8Mb/s HWY and twenty 2Mb/s HWY onto 8.192 MHz data and outputs the data to Time Switch Memory. It also partially inserts a 9 Bit parallel data (32 channel) converted by 2M HWY from TNS into time slots for 8 Mb/s HWY. There are two multiplexers, one for HWIF 0 - 3 and other for HWIF 4 - 7. Both get input from LIF also, while only MPX0 gets input from TNSE. TIME DIVISION SWITCH MEMORY (TSM 00 --11): Each TSM writes or reads data during one time slot of 122 nsec (125 micro sec / 1024) and switches 1024 multiplexed data by the switch memory control. There are three general memories (RAM) each having a storage capacity of 1024 X 4 bits. There are 4 TSM blocks. TSM 00 and 01 get input from MPX 0 and TSM 10 and 11 get input from MPX 1. They get the address from SCM 0 and SCM 1 respectively and send output to PDM 0 and PDM 1. SWITCH CONTROL MEMORY (SCM 0/1): This outputs the address information to the TSM for reading 9 bit parallel data and selects the TSM. The address to the PAD is also provided for attenuation insertion needed for conversation for each time slot. It allows for read/write control by the CPU via Processor Bus Interface. There are two SCM blocks, each consisting of three general memories (RAM) having a storage capacity of 1024 x 4 bits. It does not contain the parity check function. PROGRAMMABLE, ATTENUATOR DIGITAL MEMORY (PDM 0,1): The necessary attenuation for conversation in extension is inserted by PDM according to the instruction of SCM. There are two units, each having three ROMs of 1024 X 4 bits, when PAD is not inserted the data with the PAD inserted is output according to the input data and converts the data including the parity bit. 8 MBs HWY MULTIPLEXER (MPX 8MHW): This block selects 8 MHW output data from two groups of TSM (1024 Multiplexer switches) coming via PDM 0 and 1 and output this to P/S converter. DEMULTIPLEXER (DMPX 0, 1): These extract 2Mb/s HWY data from the parallel output from the TSM, then output the data to the P/S converter. PARALLEL TO SERIAL CONVERTER, (P/S): It converts 9 bit parallel data output from MPX 8MHW into 8M serial HWY data and converts 9 bit parallel data out put from DMPX 0 and 1 into 2Mb/s serial HWY. It executes parity check, Besides these there are some blocks used for interfacing with CPM. A) P-BUS INTERFACE (PBUSINF): It has the interface circuit with the processor bus of the CPM and R/W controls for SCM. It also provides an interface of MSD and MSCN with the CPM. B) MAINTENANCE OF SIGNAL DISTRIBUTION CIRCUIT (MSD): It distributes the reset signal to the HWIF and the TNS via PBUSINF according to the order of CPM. MSD operation is done in response to the write operation of TSW C) MAINTENANCE SCAN CIRCUIT (MSCN): It reads the error information and clock disconnection information via the PBUSINF and carries out the reset operation. It is also under the control of CPM. This checks the parity error information of TSM, pattern check information of

TNSE and clock disconnection information to the TSW. The parity error and clock disconnection information to the CPM is given by interrupts, MSCN operation is carried out in response to the read interrupts, MSCN operation is carried out in response to the read operation of TSW. MSD\WSCN is processed as memory map I\O. TIMING OCCURRENCE CONTROL (TIM): By using the internal oscillator and 8 MHz clock of LIF/8KHZ clock of CLKX, it generates the control timing for each block and supplies 4.096MHZ clock and 8KHz clock signals to TNS and HWIF. Out of the six 8Mb/s HWY,8MHW 0 has 32 channels for accommodating 2Mb\s data from TNS and 96 channels for LIF thus LIF has 736 (5*128+96) channels. Actual channel numbers of 8MHW 0 used for tone are 0,4,8,12,---- 120,124 The residual channels are named in order from 32 to 127 for convenience. TNS Highway is connected to TSWC0 and LIF Highways are connected to TSWC1. MSD\MSCN data is kept is kept in memory location F37FFE (H) MSD uses bits 0 to 7 for HWIF 0 to 7 reset and bit 15 for IP reset in TNS. This is achieved during write operation. Logic " 1 " is valid for all these bits. MSCN uses only bits 0 to 4 with bit3 as don't care and bit 4 kept set as "0" bits 0 to 2 detect error if data is " 1 ", for TSM parity error, clock disconnection and TNS pattern check respectively. When LIF/CLKX card is mounted J11&J12 are to be shorted and CLK-OFF detection is invalid. When TSW is self-running with out LIF/CLKX, J11&J10 are to be shorted and CLK - OFF detection is valid. INPUT OUTPUT CONTROL - 1 This card is mounted in slot 16 of the CME card and controls three RS232C interface I/O terminals. The interface among the I/O terminals provide general purpose programmable configuration. Each of the post can have a separate communication speed. Depending on the type of terminal to be connected (DCE or DTE), each of the post uses different signal line connection modes. I/O terminal data comes to the internal bus via a Driver/ Receiver stage which converts RS232C to TTL and vice versa and then through a programmable communication interface. There is a time for communication clock generation. Port 0 is fixed for DCE mode while posts 1 and 2 are for DTE mode.

The block diagram and I/O terminal interface connection are shown in T12E 4.14.

NETWORK SYNCHRONOUS CLOCK (CLKD) This card is mounted in slot 06 and 27 of CME Rack and is used for supplying synchronised clock to the system, if Digital Tie Lines are used. It receives 64 Kb/s Data and 8 kb/s control information having AMI codes from Mux or 2Mb/s Digital Tie Line Trunk and performs level as well as coding conversion. It also generates 16 MHz, 384MHz and 8KHz clock and sends them to LIF or TSWC. It can also supply clock signals to external equipment.

The block diagram is showed in T12E 4.15.

The card sends Fault Information to LIF, SSC and TSW e.g., EXCLK1 (Frame out of frequency), EXCLK2 (External alarm) or CLKDAL (No output clock or frame) etc. It has LED indication also

for these fault signals. It accepts up to 4 input clock ports. 4 LED s show the Route selected. There are two 16-pin connectors CNC and CND.