PIC18F is Microchips 8-bit microcontroller.

It uses Harvard architecture (program and data memory unit in separate spaces) Use flash memory to store program memory and SRAM contains data memory. Typically, the flash memory is 4Kbytes, EEPROM in 256 bytes, SRAM is 512 bytes.

 WREG : working register. 8 bits. An accumulator. Most arithmetic and logic operations are performed using WREG. Its address is 0xFE8. SP : Stack Pointer. 8 bits wide. PC : Program Counter. 21 bits. Points to the next instruction to be executed. Table Pointer: 21 bits. BSR : Bank Select Register, 8 bits. Is used for directly addressing the data SRAM. FSR: File Select Register. Three 16-bit register namely FSR0, FSR1, FSR2.
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 SR : Status Register. 8 bits. Address 0xFD8. Contains flags:

C(Carry flag) set if there is carry/borrow. DC(digit carry) set if there is carry/borrow due to addition/subtraction of low 4 bits into the high 4 bits. Z(zero) set if result is zero. OV(Overflow) set if there is arithmetic overflow. N(negative) set if MSB is 1 indicating negative number. Bits 5-7 are not implemented, read as zero.

 Add 0616 and 1416. Subtract 0616 from 6816.

Determine the state of each condition code.

 An addressing mode specifies how to determine the operand and destination addresses during the execution of an instruction. Various types of addressing modes:
Inherent/Implied Immediate /Literal Absolute/Direct Addressing Indirect

The instruction has no operand. Are also called no-operand instructions. Example : SLEEP, DAW DAW adjust the sum in the WREG register stored after addition of two 8-bit packed BCD numbers.

 Whenever an instruction/operand contains literal or constant data. Example: ADDLW 3 ; [WREG] [WREG] + 3
This instruction adds 3 to the contents of WREG and then stores the result in WREG.

MOVLW 0x2A
Moves 8-bit data 2AH into WREG

 If an instruction contains a memory address in the operand field. Example: MOVWF 0x20; [0x20] [WREG] This moves the contents of the WREG register into a memory location whose address is 0x20. The contents of WREG are unchanged. It is called direct addressing mode since address 0x20 is directly specified in the MOVWF instruction.

 When an instruction specifies a register to hold the address. A register is used as a pointer to an address in the data memory. Example: MOVWF INDF0 ; Move contents of WREG into a data RAM address pointed to by FSR0 since INDF0 is associated with FSR0.
This moves the contents of WREG to a data memory whose address is in FSR0 register. This instruction use the contents of FSR0 register as a pointer to data memory. INDF0 means the FSR0 will hold the address of data memory.
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MOVLW MOVWF LFSR REPEAT CLRF DECF BNZ LFSR LFSR LFSR 0,0x0010 1,0x0040 2,0x0080

D20 0x10 0,0x0030 POSTINC0 0x10,F REPEAT

; Move 20 decimal into WREG ; Initialize counter 0x10 with 20 ; Initialize pointer FSR0 with 0x0030 ; Clear a location to 0 and increment FSR0 by 1 ; Decrement counter by 1 ; Branch to REPEAT if Zero flag = 0, otherwise go to next instruction

; Load 0010H into FSR0 ; Load 0040H into FSR1 ; Load 0080H into FSR2

MOVLW 0x35 ; Move 35H into WREG LFSR 2,0x0050 ; Initialize FSR2 with the RAM location 0050 MOVWF INDF2 ; Move contents of WREG (35H) into a RAM address pointed by FSR2 (address 0050)

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Indirect with postincrement mode Indirect with preincrement mode Indirect with postdecrement mode Indirect with 8-bit indexed mode.

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 Reads contents of FSR specified, then the FSR is then incremented by 1 to point to the next address. Special function register POSTINC is used for this. Example : CLRF POSTINC0.
Suppose that FSR0 are 0030H, and its contents are 84H. After execution CLRF POSTINC0, the contents of 0030H will be cleared to 00H. Then the contents of FSR0 will be incremented by 1 to point to address 0031H.

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 First FSR is incremented by 1 to point to the next address, then it reads the contents of the new FSR. Special function register PREINC is used for this. Example : CLRF PREINC0.
Suppose that FSR0 are 0030H, and its contents are 84H. After execution CLRF PREINC0, the contents of FSR0 will be incremented by 1 to point to address 0031H. The contents of 0031H will be cleared to 00H.

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 Reads contents of FSR specified, then the FSR is then decremented by 1. Special function register POSTDEC is used for this. Example : CLRF POSTDEC0.
Suppose that FSR0 are 0054H, and its contents are 21H. After execution CLRF POSTDEC0, the contents of 0054H will be cleared to 00H. Then the contents of FSR0 will be decremented by 1 to point to address 0053H.

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 Adds the contents of the FSR specified in the instruction with the contents of WREG. The sum is used as an address of a data register in RAM. The instruction are executed using these data. Contents of FSR and WREG are unchanged. Example : CLRF PLUSW2.
Supposed that contents of FSR2 are 0020H, WREG are 04H. Content at address 0024H are 37H. After execution, the contents of 0024H will be cleared to 00H. The contents of FSR2 and WREG are 0020H and 04H respectively, unchanged.
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 Identify the addressing mode for the following: NOP MOVLW 0x2A CLRF PREINC2

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