EXERCISES

1. For the following two DTL gate circuits as shown: a. W rite the logic levels (H or L) at both inputs and the output. b. What is the State o f the transistor? c. Draw arrows showing the direction o f all currents in the circuit.

For the following exereises, the manufacturer o f DTL gates gives the following specifications: ^inL m ax 1-00 Volts ^oL m ax ^ volts ^inH m in 2.00 volts VoHmin = 2.75 volts loLmax = 10.00 mA loHmax = -5-00 mA (@V q = 2.75 v)

inLmax ^-1-OOmA
linH = 0-00

3. A logic system shown below is made up o f DTL gates. 1. Write the logic level (H orL) beside each input and output for each gate. 2. Draw arrows beside each connecting wire, including inputs and outputs, showing the direction o f current in the wire. If zero, write 1=0.
+5

4. On the diagram, give the magnitude o f all currents except the two final outputs.

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5. Determine the minimum valu o f each o f the load resistors if the gates are to be operated within specifications and logic levels are preserved.

p u llu p m in

R,p u lld o w n m in

6. The circuit below is used to interface a switch to the DTL gate specified above. It is assumed that with the switch in one position, the gate sees a valid logic low, and when the switch is in the other position, the gate sees a valid logic high. a. Indcate on the drawings, which logic level the gate input sees. b. Draw arrows showing currents when the switch is open and when the switch is closed.

7. For the input interface circuit above, determine the mximum valu o f R that can be used and still have the gate operate within specifications. W hat determines the minimum valu o f R? Rmay Rmin is determined by:

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Problems
1. Your employer, M ountaineer Logic, Inc., is developing a new line o f discrete DTL gates shown below. Write up a specification sheet for the device. (Use nominal calculations only.) Define the high level output current at V q = VinHmin+1-0 volts. Use a tabular format similar to the DTL data sheet given in this chapter. Assume the following diode and transistor models. Vocutin = 0.6, Voon 0.7, VBEcutin = 0.5, VeEsat = 0.8, Beta = 20 2. The Quality Control Department o f MLI just called you about the DTL gate above. It seems they connected it to a network with a single load gate. The output rise time seemed much too long. Upon questioning, you discover that they used a very long wire to coimect between the driver and the load. You estmate that the capacitance o f the wire to be 5000 pF as shown in the figure below. Estmate how long it will take to charge the capacitor so the output o f the gate to rise from a "low" to V infm iti- Because you are a professional, present only the circuit you used, the results, and the assumptions you made (including circuit models). Do not show details o f the calculations.
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Long wire
5000pF-

DTL Gate

Circuit with 5000pF capacitive load

3. The m anufacturers specifications for a DTL gate are:

^inLm ax ^ ^-00 volts ^inH m in ^ 2.00 volts linLmax linH - LOO mA = 0.00

^oLmax V oHmin ^oLmax

loHmax ^oHmax = -5-00 mA
(@ V
q

= 2.75 v)

This gate is used to drive two identical gates, plus a resistive load as shown. Determine the allowed range for Ri if R 2 = 2200 Ohms.

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Ri Rn

4. A DTL gate has an additional diode added as seen in the circuit below. Determine
V itiL m a x j V i n H m i n j lin L ? l i n H j a n d lo L m a x -

Diode Models: V dy = 0.60, Transistor Models:

V bey 0.50,

Voon = 0.70 volts

VBEsat~0.80, VcEsat~0.20, Beta = 20

+5

IK

6. Two logic families are being used in a logic system. Their terminal specifications are given below. Fill in the compatibility chart. McOO 1.00 WVOO 1.50 3.00 - 1.00 mA 0.050 mA 0.75

V in L m ax

V in H m in

2.00
- 0.500

li n L

lin H

1.00
0.50

VoLmax

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V o H m in
lo L m a x

2.50 5.50 -7.00 Load McOO W VOO

McOO Driver

4.00 8.00 mA -2.50 mA

lo H m a x

WVOO

7. In the following logic circuit, all the gates are McOO gates whose specifications are given below. Determine the range o f resistance allowed for the resistor R such that all gates are working within their specifications. Note that the load gates must see a legitmate logic low and legitmate logic high.
V in L m a x = l- 0 0 V in H m in = 2 . 0 0 li n L = 0 . 5 0 0 I i n H = l -0 0

V oL m ax

0 .5 0

V o H in in

2 .5 0

lo L m a x

5 .5 0

lo H m a x

7 .0 0

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