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Dynamic Combinational Circuits

• Dynamic circuits

– Charge sharing, charge redistribution

• Domino logic

• np-CMOS (zipper CMOS)

Dynamic Logic

Dynamic gates use a clocked pMOS pullup

• Two modes: precharge and evaluate

A

pMOS pullup • Two modes: precharge and evaluate A 2   2/3 φ 1    

2

 
2   2/3 φ 1

2/3

φ

2   2/3 φ 1

1

   

Y

   

Y

   

Y

       

1

A

1 A 4/3 A 1

4/3

A

1 A 4/3 A 1

1

     
 
     
 
     
 

Static

φ

Y

Pseudo-nMOS Dynamic Precharge Evaluate Precharge
Pseudo-nMOS
Dynamic
Precharge
Evaluate
Precharge
The Foot • What if pulldown network is ON during precharge? • Use series evaluation
The Foot
• What if pulldown network is ON during
precharge?
• Use series evaluation transistor to prevent fight.
φ
φ
precharge transistor
φ
Y
Y
Y
inputs
inputs
A
f
f
foot
footed
unfooted

Dynamic Logic

In 1

In 2

In 3

V DD Φ M p Out C L PDN Φ M e
V DD
Φ
M
p
Out
C L
PDN
Φ
M
e

In 1

In 2

In 3

Φ n network

• Precharge 2 phase operation: • Evaluation

V DD Φ M e PUN Out Φ M C L p
V DD
Φ
M
e
PUN
Out
Φ
M
C L
p

Φp network

Logical Effort Inverter NAND2 NOR2 φ 1 Y φ 1 φ 1 A 2 unfooted
Logical Effort
Inverter
NAND2
NOR2
φ
1
Y
φ
1
φ 1
A
2
unfooted
Y
Y
A
1
B
2
A
1 B
1
= 1/3
g
d = 2/3
= 1/3
g d
g d
= 2/3
= 3/3
= 3/3
p d
p d
p d
φ 1
Y
φ 1
φ
1
A 3
Y
Y
footed
A 2
B 3
A
2
B
2
= 2/3
= 3/3
= 2/3
g d
g d
g d
2
3
2
= 3/3
= 4/3
= 5/3
p d
p d
p d

Dynamic Logic

• N+2 transistors for N-input function

– Better than 2N transistors for complementary static CMOS

– Comparable to N+1 for ratio-ed logic

• No static power dissipation

– Better than ratio-ed logic

• Careful design, clock signal Φ needed

Dynamic Logic: Principles

In 1

In 2

In 3

V DD Φ M p Out C L PDN Φ M e
V DD
Φ
M p
Out
C L
PDN
Φ
M
e

Precharge

Φ = 0, Out is precharged to V DD by M p .

M e is turned off, no dc current flows

(regardless of input values)

Evaluation

Φ = 1, M e is turned on, M p is turned off.

Output is pulled down to zero depending

on the values on the inputs. If not, precharged value remains on C L .

Important: Once Out is discharged, it cannot be charged again! Gate input can make only one transition during evaluation

• Minimum clock frequency must be maintained

• Can M e be eliminated?

Example

V DD

M p M e
M
p
M
e
Example V DD M p M e Φ Out A B C Φ • Ratioles s
Example V DD M p M e Φ Out A B C Φ • Ratioles s

Φ

Out

A

A

B

B

C

Φ

Example V DD M p M e Φ Out A B C Φ • Ratioles s

• Ratioles s

• No Static Power Cons umption

• Nois e Margins s mall (NM L )

• Requires Clock

Dynamic 4 Input NAND Gate φφφφ
Dynamic 4 Input NAND Gate
φφφφ

Cascading Dynamic Gates

Φ

V DD V DD M p Φ M p Out1 Out2 In Φ M e
V DD
V DD
M p
Φ
M p
Out1
Out2
In
Φ
M e
Φ
M e
V Φ In Out1 V Tn Out2 t
V
Φ
In
Out1
V Tn
Out2
t

Internal nodes can only make 0-1 transitions during evaluation period

Monotonicity

Dynamic gates require monotonically rising inputs during evaluation

0 -> 0

0 -> 1

1 -> 1

But not 1 -> 0

A

φ

Y

φ

A

– 1 -> 1 – But not 1 -> 0 A φ Y φ A violates
– 1 -> 1 – But not 1 -> 0 A φ Y φ A violates
violates monotonicity during evaluation Precharge Evaluate Precharge
violates monotonicity
during evaluation
Precharge
Evaluate
Precharge

Output should rise but does not

Monotonicity Woes

• But dynamic gates produce monotonically falling outputs during evaluation

• Illegal for one dynamic gate to drive another! A = 1 φ Precharge Evaluate
• Illegal for one dynamic gate to drive another!
A = 1
φ
Precharge
Evaluate
Precharge
φ
Y
X
A
X
X monotonically falls during evaluation
Y
Y should rise but cannot

Reliability Problems — Charge Leakage

V DD

M Φ p Out (1) C L A (2) Φ M e
M
Φ
p
Out
(1)
C
L
A
(2)
Φ
M
e

(a) Leakage sources

Φ

V out

(1) C L A (2) Φ M e (a) Leakage sources Φ V out t precharge

t

(1) C L A (2) Φ M e (a) Leakage sources Φ V out t precharge

precharge

A (2) Φ M e (a) Leakage sources Φ V out t precharge t (b) Effect
A (2) Φ M e (a) Leakage sources Φ V out t precharge t (b) Effect
A (2) Φ M e (a) Leakage sources Φ V out t precharge t (b) Effect
A (2) Φ M e (a) Leakage sources Φ V out t precharge t (b) Effect

t

A (2) Φ M e (a) Leakage sources Φ V out t precharge t (b) Effect

(b) Effect on waveforms

evaluate

A = 0

(1) Leakage through reverse-biased diode of the diffusion area (2) Subthreshold current from drain to source

Minimum Clock Frequency: > 1 MHz

Leakage

• Dynamic node floats high during evaluation

– Transistors are leaky (I OFF 0)

– Dynamic value will leak away over time

– Formerly miliseconds, now nanoseconds!

• Use keeper to hold dynamic node

– Must be weak enough not to fight evaluation

φ

A

weak keeper 1 k X H Y 2 2
weak keeper
1
k
X
H
Y
2
2

Charge Sharing (redistribution)

V DD

• Assume: during precharge, A and B are 0, C a is discharged

• During evaluation, B remains 0 and A rises to 1

• Charge stored on C L is now redistributed over C L and C a
• Charge stored on C L is now redistributed over C L and C a
M
p
Out
C
C L V DD = C L V out (t) + C a V X
L
A
M
a
X
V X = V DD - V t , therefore
δV out (t) = V out (t) - V DD =
C
a
(V DD -V t )
C
a
C
B = 0
M
L
b
C
b
M
e
Desirable to keep the voltage drop below threshold
of pMOS transistor (why?) C a /C L < 0.2
Charge Sharing • Dynamic gates suffer from charge sharing φ φ Y A A C
Charge Sharing
• Dynamic gates suffer from charge sharing
φ
φ
Y
A
A
C
x
Y
Y
C
B = 0
x
Charge sharing noise
x
C
Y
V
=
V
=
V
x
Y
DD
C
+ C
x
Y

Charge Redistribution - Solutions

V DD

M M bl Φ p Out A M a B M b Φ M e
M
M
bl
Φ
p
Out
A
M
a
B
M
b
Φ
M
e

(a) Static bleeder

V DD M M Φ Φ bl p Out A M a B M b
V
DD
M
M
Φ
Φ
bl
p
Out
A
M
a
B
M
b
Φ
M
e
b Φ M e (a) Static bleeder V DD M M Φ Φ bl p Out

(b) Precharge of internal nodes

Secondary Precharge

• Solution: add secondary precharge transistors

– Typically need to precharge every other node

• Big load capacitance C Y helps as well

φ Y A x B
φ
Y
A
x
B

secondary

precharge

transistor

Domino Logic

In 1

In 2

In 3

V DD V DD V DD Φ M Φ p M p M r Out1
V DD
V
DD
V
DD
Φ
M
Φ
p
M
p
M
r
Out1
Out2
PDN
In 4
PDN
Static Inverter
with Level Restorer
M
Φ
M
e
Φ
e
Static inverters
between dynamic stages

Domino Gates

• Follow dynamic stage with inverting static gate

– Dynamic / static pair is called domino gate

– Produces monotonic outputs

Precharge Evaluate Precharge
Precharge
Evaluate
Precharge

φ

W

X

Y

Z

A

B

φ

φ

W

H X

C

Y

H
H

Z

=

A

B

domino AND

W X Y Z A B C φ dynamic static NAND inverter
W
X
Y
Z
A
B
C
φ
dynamic
static
NAND
inverter
φ φ X C
φ
φ
X
C

Z

Domino Logic - Characteristics

• Only non-inverting logic

• Very fast - Only 1->0 transitions at input of inverter

• Precharging makes pull-up very fast

• Adding level restorer reduces leakage and charge redistribution problems

• Optimize inverter for fan-out

Domino Optimizations

• Each domino gate triggers next one, like a string of dominos toppling over

• Gates evaluate sequentially but precharge in parallel

• Thus evaluation is more critical than precharge

• HI-skewed static stages can perform logic

 

φ

  φ  
 

S0

S1S0 S2   S3

S2S0 S1   S3

S0 S1 S2   S3
 

S3

S0 S1 S2   S3

D0

D1D0   D2   D3

 

D2D0 D1     D3

D0 D1   D2   D3
 

D3

D0 D1   D2   D3
       
H
H

Y

 
 
 

φ

  φ  
 

S4

S5S4 S6 S7

S6S4 S5 S7

S7S4 S5 S6

S4 S5 S6 S7

D4

D5D4   D6   D7

 

D6D4 D5     D7

 

D7D4 D5   D6  

D4 D5   D6   D7
 
 

Dual-Rail Domino

• Domino only performs noninverting functions:

– AND, OR but not NAND, NOR, or XOR

• Dual-rail domino solves this problem

– Takes true and complementary inputs

– Produces true and complementary outputs

sig_h

sig_l

Meaning

0

0

Precharged

0

1

‘0’

1

0

‘1’

1

1

invalid

Y_l

φ inputs f f φ
φ
inputs
f
f
φ

Y_h

Example: AND/NAND

• Given A_h, A_l, B_h, B_l

• Compute Y_h = A * B, Y_l = ~(A * B)

• Pulldown networks are conduction complements

φ A_h B_l B_h φ
φ
A_h
B_l
B_h
φ
= A * B, Y_l = ~(A * B) • Pulldown networks are conduction complements φ
= A * B, Y_l = ~(A * B) • Pulldown networks are conduction complements φ

Y_l

Y_h

= A*B

= A*B

A_l

Example: XOR/XNOR

• Sometimes possible to share transistors

φ A_h A_l A_l B_l B_h φ
φ
A_h
A_l
A_l
B_l
B_h
φ
XOR/XNOR • Sometimes possible to share transistors φ A_h A_l A_l B_l B_h φ A_h Y_l

A_h

XOR/XNOR • Sometimes possible to share transistors φ A_h A_l A_l B_l B_h φ A_h Y_l
XOR/XNOR • Sometimes possible to share transistors φ A_h A_l A_l B_l B_h φ A_h Y_l

Y_l = A xnor B

Y_h = A xor B

Domino Summary

• Domino logic is attractive for high-speed circuits

– 1.5 – 2x faster than static CMOS – But many challenges:

• Monotonicity

• Leakage

• Charge sharing

• Noise

• Widely used in high-performance microprocessors

np-CMOS (Zipper CMOS) V DD V DD Φ M p Φ M e Out1 In
np-CMOS (Zipper CMOS)
V DD
V DD
Φ
M
p
Φ
M
e
Out1
In 1
PUN
In 2
PDN
In 4
In 3
Out2
M
Φ
e
Φ
M
p

• Only 1-0 transitions allowed at inputs of PUN

• Used a lot in the Alpha design

np CMOS Adder

V V DD DD V V DD DD φ φ φ φ C i1 A
V
V
DD
DD
V
V
DD
DD
φ
φ
φ
φ
C i1
A
B
B
1
1
1
A 1
B
A 1
1
C i1
A
1
B 1
φ
C
φ
φ
i2
φ
V
V
DD
DD
V
DD
φ
φ
φ
B
A
C
0
i1
0
A 0
B
0
C i0
A
0
A
B
B
0
0
0
C
i0
S
φ
φ
φ
C
i0

Carry Path

S 1

0

CMOS Circuit Styles - Summary

CMOS Circuit Styles - Summary