SPCA506A1

USB A/V GRABBER

GENERAL DESCRIPTION The SPCA506A1 provides a single chip solution to the AV-Capture application. It includes image compression and data transaction units. The compressed data is transferred to the PC side via the USB bus. The

embedded USB controller is a hard-wired state machine. There is no need to use external microprocessors.

FEATURES Support Decoded TV/YUV 4:2:2 image inputs using Philips SAA7111A or SAA7113 or SAA7114, Rockwell BT835 or BT 827B / BT829B TV decoder chips High Speed Compression support real time image output YUV 4:2:0 Video mode: 640 x 480 352 x 288 320 x 240 240 x 180 176 x 144 160 x 120 15 - 20 fps 25 - 30 fps 30 fps 30 fps 30 fps 30 fps Snapshot mode: 640 x 480 YUV 4:2:0 data EDO DRAM interface: 1M x 16 or 256K x 16 PC Interface: USB with built in tranciever EP0: Default Endpoint, control type transaction EP1: Isochronous type transaction for video mode image data (interface 0) EP2: Isochronous type transaction for audio data (interface 1) USB Suspend mode available. Serial EEPROM: Vendor ID, Product ID, Revision#, Synchronous Serial Control interface 3.3V power supply 128 pins QFP packages (14 x 20 x 2.75mm)

Sunplus Technology Co., Ltd.

Rev.: 1.0

1999.12.21

SPCA506A1
BLOCK DIAGRAM GENERAL DESCRIPTION The system receives and processes image data from TV decoder chips. The image data is then further compressed by the Compression block and stored in the DRAM. The data is then read back from the DRAM and transmit to the USB bus via the USB controller. The Synchronous Serial Control blocks programs the TV decoder chips to generate the appropriate input image format. The detailed function of each block is described in the following subsection.

COMPRESSION CONTROLLER Input/Output Image Formats Input image: YUV 4:2:2 input image format. Output image: It may generate various output image formats as list in the following table: Mode 640 x 480 352 x 288 320 x 240 240 x 180 176 x 144 160 x 120 640 x 480 640 x 480 Image Type YUV 4:2:0 (compression supported) YUV 4:2:0 (compression supported) YUV 4:2:0 (compression supported) YUV 4:2:0 (compression supported) YUV 4:2:0 (compression supported) YUV 4:2:0 (compression supported) YUV 4:2:2 YUV 4:2:0

YUV 4:2:0 type images may be either compressed or non-compressed; while other type images will always be non-compressed.

Snap Control A snap picture may be obtained by pulling down the snapnn pin of the chip or by writing to an internal snap register in the chip. Besides, two alternating snap control schemes are implemented for snapping a picture: one is software dominated; the other is hardware dominated. The software dominated control scheme is designed for the application software which can not immediately adjust the display window size according to the image type in the property byte of the incoming image frame.

Software dominated control scheme (Un-toggle control): When software dominated control scheme is selected, 8 image types are defined. User may select any image type to play a motion picture. When the snap button is pressed, either by pulling down the snapnn pin or writing to the snap register, the IC will keeps playing motion pictures according to the image type selected . The only difference is the snap bit in the property byte for that image frame is set to 1. Then, the application software may detect this snap bit turn on and snap the image frame. Sunplus Technology Co., Ltd. 2 Rev.: 1.0 1999.12.21

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Hardware dominated control scheme (Toggle control): When hardware dominated control scheme is selected, 6 image types are defined as video modes to play motion pictures and 4 image types are defined as snap modes to capture a single image frame. User may select one image type for video mode and one for snap mode respectively. Video mode and snap mode may toggle dynamically during playing. The IC is default in video mode and playing motion pictures. When one of the snap buttons are pressed, the IC will stop playing motion pictures right after the current image frame is transferred. Then the system will output a still image frame according to the image type previously selected for snap mode. The snap bit in the property byte for this still image frame will be set as 1. After that, the system will immediately resume to play motion pictures according to the image type previously selected for video mode.

DRAM CONTROLLER The 1M x 16bit DRAM is used as the temporary buffer for the compression controller and as the ISO packet FIFO for the USB controller. The DRAM controller must schedule all the requests to satisfy the bandwidth and latency time requirements for various image operations in order to get better performance. The contents of the DRAM can also be accessed with the USB vendor commands. The procedure is described below. 1. set the starting row address 2. set the starting column address 3. set the return row address 4. set the return column address 5. set the prefetEn bit in the control port 1 register if the operation is read 6. access the DRAM data port The row and column addresses for the DRAM are internal generated by the chip.

USB CONTROLLER There are two USB pipes built-in the chip: the first one is the default pipe which is used to handle the standard and vendor commands. The other one is the ISO-IN pipe that is used to transmit the image data.

Pipe 0 The maximum packet size is 8 bytes for pipe 0. All standard commands except SET_DESCRIPTOR and SYNCH_FRAME are supported. All the USB descriptors, except vendor ID, product ID and device release number, are hardwired. The values of vendor ID, product ID and device release number, could be hardwired or loaded from an external serial EEPROM(AT93C66). The selection is done by an IO-trap pin, refer to IO-pin section for further details. The string descriptors are also stored in the serial EEPROM. The details about the data in the serial EEPROM are described in Section 4.7.

Sunplus Technology Co., Ltd.

Rev.: 1.0

1999.12.21

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Video ISO-IN pipe For the video ISO-IN pipe, the host may issue standard commands to change its maximum packet size. To achieve the optimal system performance, the user must adjust the alternative interface setting based on the image size and compression rate. The following table shows the maximum packet sizes for the available alternative interface settings.

Alternative Interface Setting 0 1 2 3 4 5 6 7

Maximum Packet Size for ISO IN Pipe (bytes) 0 128 384 512 640 768 896 1023

Video ISO Packet Property byte: Each image frame stream consists of a set of USB ISO packets. In the first USB ISO packet for an image frame stream, several bytes are defined as property bytes to record the image type, compression scheme, and snap approach for the image frame stream. Thus, software may identify each incoming image frame stream.

There are ten property bytes for the start of frame packet. They are sequence byte, property byte 1, property byte 2,.., property byte 8 and property byte 9. The other packets contains only the sequence byte. The value of the sequence byte in the first packet of an image stream is 0X00, followed by sequence byte 0X01, 0X02, 0X03, etc. The last value of the property byte is 0XFE. The value will wrap around to 0X00 when it reaches 0XFE. 0XFF is a special value for the property byte which marks a drop packet, i.e. no image data is in this packet.

Property Byte 1: Bit 4:0 5 6 Field ImageType Reserved SnapBit r Two alternating definitions for this bit may be selected by SnapControl field. Under software dominated snap control (Un-toggle control): When the hardware snap button or software snap button is pressed, this bit in Att r Description Refer to the compression part in the section Internal register description

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Bit Field Att Description the property byte of the next coming out image will be set to 1. It will become 0 for the next coming out image. Under hardware dominated snap control (Toggle control): When this bit is 1, the image type of the current coming out image will be one of the 4 snap modes; when this bit is 0, the image type of the current coming out image will be one of the 6 video modes. 7 SnapControl r Refer to the compression part in the section Internal register description

Property Byte 2: Bit 0 3:2 6:4 Field CompEnable TurnPoint3A Threshold3D Att r r r Description Refer to the compression part in the section Internal register description Refer to the compression part in the section Internal register description Refer to the compression part in the section Internal register description

Property Byte 3: Bit 2:0 6:4 Field Threshold2D Threshold1D Att r r Description Refer to the compression part in the section Internal register description Refer to the compression part in the section Internal register description

Property Byte 4: Bit 2:0 6:4 Field Quant3A Quant3D Att r r Description Refer to the compression part in the section Internal register description Refer to the compression part in the section Internal register description

Property Byte 5: Bit 2:0 6:4 Field Quant2D Quant1D Att r r Description Refer to the compression part in the section Internal register description Refer to the compression part in the section Internal register description

Property Byte 6: Bit 7:0 Field FramSequence Att r Description The input image frame sequence number

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Property Byte 7: Bit 0 Field EdgeMode Att r Edge enhancement: 0: disable 1 GammaEn r 1: enable Description

Gamma correction enable 0: disable 1: enable

AudioEn

The audio function 0: disable 1: enable

7:3

Reserved

Property Byte 8: Bit 7:0 Field GPIO Att r General purpose IO Description

Property Byte 9: Bit 7:0 Field Reserved Att Description

USB Power Control According to the USB specification 1.0, no USB device may require more than 100 mA when first attached, a configured bus-powered USB device attached to a self-powered hub may use up to 500 mA and all USB devices must support a suspended mode that requires less than 500 A. For the USB power budgeting, there are three states designed in the chip: unconfigured, full-speed and suspend. The chip behavior in the three states are described as follows:

Unconfigured: all output pins, except connecting to the USB transceiver and serial EEPROM pins, are not driven and all bi-directional pins, except the GPIO pins, are pulled-down to 0. Full-speed Suspend : all pins are normally operated. : all output pins, except connecting to the USB transceiver pins, are not driven and the serial EEPROM output pins and all bi-directional pins are pulled-down to 0. The internal clocks are gated and unchanged and the clock driver pin is disabled.

There is a newly adding bit at the bit 15 in the control port 0 to enable the DRAM control. The default value of this bit is zero that means the DRAM control is disabled. So the power for the DRAM must be turned off before this bit is enabled.

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SERIAL EEPROM CONTENT There is an interface to access the 256x16 serial EEPROM (93c66) that can be used to store some data about the device. Address 0 1 Purpose Vendor ID Product ID

I2C INTERFACE The i2c interface is used to program TV decoder IC(SAA7111). The write sequence: S Slave Address + wb ACKs Sub Address ACKs Data ACKs P

The read sequence: S Sr Or S S Slave Address + wb Slave Address + r ACKs ACKs Sub Address Data ACKs ACKm P P Slave Address + wb Slave Address + r ACKs ACKs Sub Address Data ACKs ACKm P

Where S is start condition, ACKs is acknowledge from slave, P is stop, Sr is repeat start condition, and ACKm is acknowledge from master.

TV INTERFACE TV interface is used to receive the digital output data from TV decoder. The format is CCIR 601/656 YUV 422. Both single channel and dual channels are supported.

Single channel (TV-Y) : Cb Y Cr Y Cb Y Cr Y Dual channels : TV-Y : Y0 Y1 Y2 Y3 . TV-UV : Cb0 Cr0 Cb1 Cr1 ..

In CCIR 601, the active signals (horizontal active or vertical active or data valid) are needed to inform the active region. In CCIR 656, the active signals can be extracted from data streams according to SAV/EAV code.

Sunplus Technology Co., Ltd.

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SPCA506A1
IO TRAP DESCRIPTION The Output pins ma[0], ma[1], ma[2] and ma[3] are used as IO-trap pins. These signals can be pulled high or low on the system board to configure the SPCA506A1 operation. The hardware setting is as follows:

Trap Pin ma[0] The vendor/product ID selection: 0: from the serial EEPROM 1: by hardwire ma[1] The USB transceiver selection: 0: internal 1: external ma[2] The interface 1 (audio) 0: disable 1: enable ma[3] test mode 0: normal mode 1: test mode

Function

INTERNAL REGISTER DESCRIPTION Vendor commands are used to access the internal registers that are categorized to ten groups that are selected by the bRequest byte in the setup packet. The register size in the first three groups are 16 bits and the register size in the other groups are 8 bits. The detailed description for vendor command is shown as follows:

bmReqType EEPROM Memory USB Control Global Control Compress Reserved Reserved Synchronous Serial Control TV Audio 0x41 / 0xc1 (*) 0x41 / 0xc1 0x41 / 0xc1 0x41 / 0xc1 0x41 / 0xc1 0x41 / 0xc1 0x41 / 0xc1 0x41 / 0xc1 0x41 / 0xc1 0x41 / 0xc1

bRequest 0 1 2 3 4 5 6 7 8 9

wValue data data data data data data data data data data

wIndex register index register index register index register index register index register index register index register index register index register index

WLength 0 / 2 (**) 0/2 0/2 0/1 0/1 0/1 0 or 8 / 1 or 8 0/1 0/1 0/1

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* : 0x41 for write , 0xc1 for read. ** : wLength specifies the data size in the DATA phase of an USB setup transfer. When writing to a register, the data is stored in the wValue. So the value of wLength is always zero. When reading a register, there are one, two or eight bytes data returned in the data phase. If burst writing to a register, the data will be transferred in the other data phase. So the value of wLength is eight.

EEPROM CONTROLLER REGISTER Mode read write write disable write enable Windex-High 8h00 8h01 8h02 8h03 Windex-Low access address access address dont care dont care

MEMORY CONTROLLER REGISTER DRAM Access Data Port (0) Bit 15:0 Field Data[15:0] Att r/w Description The host accesses the data of DRAM.

The Start Row Address of DMA (1) Bit 9:0 15:10 Field RowAdr Reserved Att r/w Description The starting row address to access DRAM.

The Start Column Address of DMA(2) Bit 9:0 15:10 Field ColAdr Reserved Att r/w Description The starting column address to access DRAM.

The Return Row Address of DMA (3) Bit 9:0 15:10 Field RowAdr Reserved Att r/w Description The return row address to access DRAM.

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The Return Column Address of DMA (4) Bit 9:0 15:10 Field ColAdr Reserved Att r/w Description The return column address to access DRAM.

USB CONTROL REGISTER Control (0) Bit 0 Field ISOEn Att r/w The ISO packet machine 0: disable 1: enable 1 PrefetEn r/w Prefetch DRAM enable for the USB host 0: disable 1: enable 15:2 Reserved Description

Test (1) Bit 0 Field BlkISODPkt Att r/w Block ISO drop packet 0: disable 1: enable 1 DPThrSel r/w Drop packet threshold selection: 0: the data in ISO FIFO is not greater than four 1: the data in ISO FIFO is not greater than one 15:2 Reserved Description

Vendor ID in Serial EEPROM (2) Bit 15:0 Field VID[15:0] Att r Description The vendor ID in the serial EEPROM

Product ID in Serial EEPROM (3) Bit 15:0 Field PID[15:0] Att r Description The product ID in the serial EEPROM

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GLOBAL CONTROL REGISTER Addr 0 Bit 0 Field IDSel Att r Description The vendor/product ID selection 0: auto load from the serial EEPROM 1: hardwire value 1 ExtTrxEn r USB transceiver selection 0: internal transceiver 4:2 5 Reserved Synchronous Serial ControlEn 6 AudioEn r/w r/w Synchronous Serial Control function 0: disable 1: enable 1: external transceiver

The audio function 0: disable 1: enable

7 1 0

Reserved BlkUSBReset r/w Block the USB reset to reset the device 0: disable 1: enable

BlkSuspend

r/w

Block USB suspend 0: disable 1: enable

2-3 4

Reserved DramOutEn

r/w r/w The DRAM controller output enable 0: disable 1: enable

IntRsmCntEn

r/w

Internal resume counter enable 0: disable 1: enable

7:6 2 3 7:0 6:0

Reserved Reserved GPIOO r/w r/w The general purpose I/O output data bit0: Synchronous Serial Control clock bit1: Synchronous Serial Control data other bit: GPIOO

6:0

GPIOOENN

r/w

The general purpose I/O output enable (low active) 0: output enable 1: output disable

6:0

GPIOI

The general purpose I/O input data bit1: Synchronous Serial Control data other bits: GPIOI

1:0

Reserved

r/w

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COMPRESS REGISTER Addr 0 Bit 4:0 Field ImageType Att r/w Description The image type to be transferred to PC host for display. Two alternating definitions for this register may be selected by SnapControl field.

Under software dominated snap control (Un-toggle control) Bits [3:0]: 0000: mode 0 --- 640x240 YUV 4:2:0 continuous processing. 0001: mode 1 --- 352x288 YUV 4:2:0, continuous processing 0010: mode 2 --- 320x240 YUV 4:2:0, continuous processing 0011: mode 3 --- 240x180 YUV 4:2:0, continuous processing 0100: mode 4 --- 176x144 YUV 4:2:0, continuous processing 0101: mode 5 --- 160x120 YUV 4:2:0, continuous processing 1000: mode 6 --- Reserved 1001: mode 7 --- 640x240 YUV 4:2:2, discrete processing 1010: mode 8 --- Reserved 1011: mode 9 --- 640x240 YUV 4:2:0, discrete processing else : Reserved Bits [4]: Reserved

Under hardware dominated snap control (Toggle control) Bits [2:0]: 000: video mode 0 --- 640x240 YUV 4:2:0 001: video mode 1 --- 352x288 YUV 4:2:0 010: video mode 2 --- 320x240 YUV 4:2:0 011: video mode 3 --- 240x180 YUV 4:2:0 100: video mode 4 --- 176x144 YUV 4:2:0 101: video mode 5 --- 160x120 YUV 4:2:0 else: reserved

Bits [4:3]: 00: snap mode 0 --- Reserved 01: snap mode 1 --- 640x240 YUV 4:2:2 10: snap mode 2 --- Reserved 11: snap mode 3 --- 640x240 YUV 4:2:0 7:5 Reserved 12 Rev.: 1.0 1999.12.21

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SPCA506A1
Addr 1 Bit 0 Field SnapControl Att r/w Description 0: Software dominated snap control (Un-toggle control) 1: Hardware dominated snap control (Toggle control) 1 HwSnapButnSta r The status for the hardware snap button Set : when the hardware snap button is pressed Cleared : when the register is read 2 HwSnapButnVldChk r/w Hardware snap button valid check 0: Disable 1: Hardware snap button valid only when it keeps more than 2.6ms 3 SwSnapButton w When 1 is written to this bit, the hardware will emulate the behavior just like the hardware snap button pressed. When 0 is written, no effect. When read, always return 0. 4 Dram1M r/w 0: means DRAM 256Kx16. 1: means DRAM 1Mx16. (The Compress unit may process the image in the larger DRAM buffer region to get better image quality) 5 6 Reserved TVFieldProcess r/w r/w 0: frame mode: process both fields for each frame. This mode doesnt support 640x240 TV output. 1: field mode: process only one field for each frame. 7 2 0 Reserved Line8Image r/w 0: normal 1: only 8 lines of processed data is output by the compress unit for each image frame, whatever the image type is set. 1 HFiltDram r/w 0: normal 1: only horizontal processing is activated by the compress unit for each image frame 7:2 7:3 8 7:0 0 Reserved Reserved CompEnable r/w 0: without compression 1: with compression 7:6 9 1:0 Reserved TurnPoint3A r/w 3A band normalization 00: T=0 01: T=32 10: T=64 11: T=96

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Addr Bit 6:4 Field Threshold3D Att r/w 000: threshold = 0 001: threshold = 2 010: threshold = 4 011: threshold = 8 100: threshold = 16 101: threshold = 32 else: threshold = 0 a 2:0 6:4 b 2:0 Threshold2D Threshold1D Quant3A r/w r/w r/w Refer to Threshold3D field. Refer to Threshold3D field. 000: quantization factor = 1 001: quantization factor =2 010: quantization factor = 4 011: quantization factor = 8 100: quantization factor = 16 else: quantization factor = 1 6:4 c 2:0 6:4 Quant3D Quant2D Quant1D r/w r/w r/w Refer to Quant3A field. Refer to Quant3A field. Refer to Quant3A field. Description

SYNCHRONOUS SERIAL CONTROL REGISTER Addr 0 Bit 7:0 Field DATA[7:0] Att r/w Description The data buffer for Synchronous Serial Control transfer. Writing this buffer will initiate Synchronous Serial Control write sequence. 1 2 7:0 7:0 ADDR[7:0] PREFETCH[0] w w The register address Writing this bit will initiate Synchronous Serial Control read sequence Synchronous Serial RSTA[1] Controls repeat start condition when rsta is high, otherwise Synchronous Serial Control will stop then start.(only work in Synchronous Serial Control read) 3 7:0 BUSY[0] r Busy is high when Synchronous Serial Control read or write. 4 7:0 SLA[7:0] w The slave address 8h00 1h0 1h0 8h00 1h0 Default 8h00

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Note: 1. For write programming: write SLA -> write ADDR -> write DATA 2. For read programming: write SLA -> decide RSTA -> write ADDR -> write PREFETCH -> polling BUSY -> read DATA

TV-IN REGISTER Addr 0 Bit 7:0 Field Parm0[0] Att r/w Description Select PAL or NTSC TV system. High for PAL and low for NTSC. Parm0[1] Select single channel or dual channels operating mode. High for signal channel and low for dual channels. Parm0[2] Select external field signal or internal generated field signal. High for external field and low for internal field. Parm0[3] Parm0[5:4] Invert field signal. High is active. Select first pixel of Cb Y Cr Y in single channel or Cb Cr in dual channels. Parm0[6] Parm0[7] 1 7:0 Parm1[0] r/w Reserved Add/sub 128 for Tvi output data. Low is active Active region is decided by hdvalid and vdvalid when bit is set, otherwise hdvalid and dvalid are used. Parm1[1] Pixel rate clock is generated from double pixel rate clock when bit is set. Parm1[2] Field signal is decoded from ccir656 data when bit is set. Parm1[3] Active signal is decoded from ccir656 data When bit is set. Parm1[4] Parm1[5] Parm1[7:6] 2 7:0 Parm2[7:0] r/w Active region is decided by hdvalid when bit is set. Vdvalid will not be used when bit is set. Test mode control Reserved 8h3d Default 8h42

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AUDIO CONTROL REGISTER Control (0) Bit 0 1 Field AudioEn AudOutReg Att r/w r/w Description When high, the audio function is enabled. When low to high, the value in the output address and data (only in the write mode) will be transmitted 2 3 AudInRegClr WRstCodec r/w r/w When high, the valid bit for the audio in register will be cleared. When high, the audio reset pin will be forced to the low state and the audio will be into warm reset state. 4 CRstCodec r/w When high, the audio sync pin will be forced to the high state and the audio device will be into cold reset state. 5 ATETest r/w When high, the audio data out pin will be forced to the high state and the audio device will be into ATE test state. The audio reset pin must be forced to low state before the audio data out pin is in high state and must be forced to high state after the audio data out pin is from low to high. 6 7 AudFIFOTest Reserved r/w When high, the CPU can directly read or write audio FIFO.

Output Address(1) Bit 7:0 Field AudOutAddr Att r/w 7: ( 1 = read, 0 = write) 6:0 The output address to read/write audio register Description

Write Data Low byte(2) Bit 7:0 Field AudWrData Att r/w Description The data to write audio register (low byte)

Write Data High byte(3) Bit 7:0 Field AudWrData Att r/w Description The data to write audio register (high byte)

Input Address(4) Bit 6:0 7 Field AudInAddr Reserved Att r Description The register address in audio input frame

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Input Data Low Byte(5) Bit 7:0 Field AudInData Att r Description The register data in audio input frame (low byte)

Input Data High Byte(6) Bit 7:0 Field AudInData Att r Description The register data in audio input frame (high byte)

Status(7) Bit 0 1 Field AudOutBusy AudInVld Att r r Description When high, it indicates the process to out audio register is still going. When high, it indicates there is valid data in the audio input address and data registers and the following input register data will be skipped. 7:2 Reserved

PIN DESCRIPTION Mnemonic uvdd dm dp uvss tvuv[0]/ dpo PIN No.

1 2 3 4 5

Type Pusb B B Pusb BL

PIN Description

Initial

Suspend

Register Enable

AP Consider.

TV UV data bus / test signals /External USB transceiver dpo

OUT when

OUT when

ma[1] trap 1 ma[1] trap 1

tvuv[1]/ dmo

BL

TV UV data bus / test signals /External USB transceiver dmo

OUT when

OUT when

ma[1] trap 1 ma[1] trap 1

tvuv[2]/ usboenn

BL

TV UV data bus / test signals /External USB transceiver usboenn

OUT when

OUT when

ma[1] trap 1 ma[1] trap 1

tvuv[3]/ suspend

BL

TV UV data bus / test signals /External USB transceiver suspend

OUT when

OUT when

ma[1] trap 1 ma[1] trap 1

tvuv[4]/ dpi

IH

BH TV UV data bus / test signals /External USB transceiver dpi

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PIN No.
10

Mnemonic tvuv[5]/ dmi

Type IL

PIN Description

Initial

Suspend

Register Enable

AP Consider.

BL TV UV data bus / test signals /External USB transceiver dmi

tvuv[6]/ din

11

IL

BL TV UV data bus / test signals /External USB transceiver din

tvuv[7]

12

IL

BL TV UV data bus / test signals

gvdd gvss tvy[0:7]

13 14 15-22

Pglob Pglob IL BL TV Y data bus/ test signals

gvdd tvhref

23 24

Pglob ILS TV horizontal reference signal

tvvref

25

ILS

TV vertical reference signal

tvfield tvdvalid tvck

26 27 28

ILS ILS IL IC2x2

TV field odd/even TV data valid signal TV clock (x1, 13.5M Hz)

tvckk

29

IL IC2x2

TV clock (x2, 27M Hz)

tvvd tvhd

30 31

ILS ILS

TV vertical sync signal TV horizontal sync signal

dvdd dvss gpio[0]/ scl

32 33 34

Pint Pint BS General purpose IO port / Synchronous Serial clock Tri Tri Rgpio, Ri2c External pull high

gpio[1]/ sda

35

BS

General purpose IO port / Synchronous Serial data

Tri

Tri

Rgpio, Ri2c

External pull high

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PIN No.
36-38

Mnemonic gpio[2:4]

Type BS

PIN Description

Initial

Suspend Out 0

Register Enable Rgpio

AP Consider. External pull low used to turn off power

General purpose IO port Out 0

ovss ovdd gpio[5:6]

39 40 41-42

Pio Pio BS General purpose IO port Out 0 Out 0 Rgpio External pull low used to turn off power

ma[0:3]

43-46

DRAM address Trap function: ma[0] -- 0: ID select from EEPROM; 1: ID select from internal default settings ma[1] -- 0: internal USB transceiver; 1: external USB transceiver ma[2] -- reserved ma[3] -- reserved

Tri

Tri

Rdram

Hardware trap pin external pull high/low tri-state during DRAM power off

ma[4:9]

47-52

TO

B DRAM address

Tri

Tri

Rdram

Tri-state during DRAM power off

rasnn

53

TO

DRAM row address strobe

Tri

Tri

Rdram

Tri-state during DRAM power off

dvdd dvss casnn

54 55 56

Pint Pint TO DRAM column address Tri strobe Tri Rdram Tri-state during DRAM power off Tri Tri Rdram Tri-state during DRAM power off Tri Rdram Tri-state during DRAM power off

moenn

57

TO

DRAM data output enable

mwenn

58

TO

DRAM data write enable Tri

md[0:5]

59-64

BL5

DRAM data

Tri, L

Tri, L

Rdram

Tri-state during DRAM power off

ovss

65

Pio

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PIN No.
66 67-76

Mnemonic ovdd md[6:15]

Type Pio BL5

PIN Description

Initial

Suspend

Register Enable

AP Consider.

DRAM data

Tri, L

Tri, L

Rdram

Tri-state during DRAM power off

dvdd dvss ecs

77 78 79

Pint Pint BL EPROM chip select Tri, L EPROM will be tristated during power-on reset period; while not tri-stated during suspend

esk edi edo test[4] aurstnn

80 81 82 83

TO TO IL TO

EPROM clock EPROM data input EPROM data output Audio reset to Codec

Tri Tri

Tri

Tri

Tri-state during audio chip power off

test[3] ausync

84

TO

Auiod sync to Codec

Tri

Tri

Tri-state during audio chip power off

test[2] audin test[1] aubclk test[0] audout

85

IL5

Audio data input from Codec

86

IL5

Audio bit clock from Codec

87

TO

Audio data output to Codec

Tri

Tri

Tri-state during audio chip power off

xtalin xtalout dvdd dvss rstnn

88 89 90 91 92

XI XO Pint Pint IS

Crystal pad Crystal pad Oscil. Out 1

Global reset signal to the chip

External pull high

snapnn

93

IS

Snapshot signal

External pull high

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SPCA506A1
PIN No.
94 95 96-99 100 101-102 103 104-110 111 112-116 117 118 119-128

Mnemonic nc nc nc ovdd nc ovss nc ovdd nc gvdd gvss nc

Type ILS ILS TO Ptg TO Ptg TO Ptg TO Pglob Pglob IL

PIN Description External VD External HD Reserved Tri

Initial

Suspend

Register Enable

AP Consider.

Tri

Rtg

Reserved

Tri

Tri

Rtg

Reserved

Tri

Tri

Rtg

Reserved

Tri

Tri

Rtg

Reserved

Note. PAD type symbol definition: I: O: B: P: XI: input (need external pull high/low) output bi-direction (need external pull high/low) power pad crystal input pad TO: tri-state output BL: bi-direction, pull low BS: bi-direction, smith trigger

BL5: bi-direction, pull low, 5V tolerant Ptg: power pad for output Pio: power pad for I/O buffer Pint: power pad for internal core logic Pglob: power pad for both I/O buffer & internal core logic Pusb: power pad for USB

XO: crystal output pad IL: IH: IS: input, pull low input, pull high input, smith trigger

ILS: input, pull low, smith trigger

AC/DC CHARACTERIZATION ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Supply Voltage relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VT VDD IOUT PD TOPT TSTG Value -0.4 to 4.0 -0.4 to 4.0 50 0.2 0 to +70 -55 to 125 Unit V V mA W C C

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SPCA506A1

RECOMMENDED DC OPERATING CONDITIONS Parameter Supply Voltage Input low voltage Input high voltage Symbol VDD VIL VIH Min. 3.1 -0.3 0.7VDD Typ. 3.3 Max. 3.45 0.3VDD VDD+10% Unit V V V

DC CHARACTERISTICS TA = 0 C - 70 C, VDD = 3.3V Symbol VOL 5%, VSS = 0V Min. Typ. Max. 0.4 Units V Test Condition 4mA buffer IOL = 4mA

Parameter Output low voltage

8mA buffer IOL = 8mA

12mA buffer IOL = 12mA VOH Output high voltage 2.4 V 4mA buffer IOH = -4mA

8mA buffer IOH = -8mA

12mA buffer IOH = -12mA IDD (unconfigured) IDD (normal) IDD (suspend) IIL Input leakage current 10 A VIN = 0V Power supply current 10 uA Power supply current 100 mA fop = 48MHz Power supply current 80 mA fop = 48MHz

Notes: (1) All DC electrical characteristics are measured at 25 C

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SPCA506A1
AC CHARACTERISTICS 1. DRAM Single Read Timing : RASNN
tRCD tRP

CASNN MA OENN MD
tASR tRAH row address tASC column address

tCAS tCAH

tROD tCAC valid data

tROD

Symbol tRCD tRP tCAS tASR tRAH tASC tCAH tROD tCAC

Parameter RAS to CAS delay RAS recovery time CAS pulse width Address to RAS setup time RAS to address hold time Address to CAS setup time RAS to address hold time RAS to OE delay CAS to valid data delay

Min. 10 -

Typ. 60 40 20 40 40 20 20 40 -

Max. 30

Units ns ns ns ns ns ns ns ns ns

Notes

2. DRAM Page Mode Read Timing : RASNN

tCP

CASNN
row address column address 1 column address 2

MA OENN MD

valid data 1

valid data 2

Symbol tCP

Parameter CAS recovery time

Min. 23

Typ. 20

Max. -

Units ns Rev.: 1.0

Notes

Sunplus Technology Co., Ltd.

1999.12.21

SPCA506A1
3. DRAM Single Write Timing : RASNN
tRCD tRP

CASNN
tASR tRAH row address tASC column address tDS

tCAS

tCAH

MA

tDH valid data

MD WRNN

Symbol tRCD tRP tCAS tASR tRAH tASC tCAH tDS tDH

Parameter RAS to CAS delay RAS recovery time CAS pulse width Address to RAS setup time RAS to address hold time Address to CAS setup time RAS to address hold time data to CAS setup time data to CAS hold time

Min. -

Typ. 60 40 20 40 40 20 20 20 20

Max. -

Units ns ns ns ns ns ns ns ns ns

Notes

4. DRAM Page Mode Write Timing : RASNN

tCP

CASNN
row address column address 1 tDS tDH column address 2 tDS valid data 2 tDH

MA

MD WRNN

valid data 1

Symbol tCP tDS tDH

Parameter CAS recovery time data to CAS setup time data to CAS hold time

Min. 24

Typ. 20 20 20

Max. -

Units ns ns ns Rev.: 1.0

Notes

Sunplus Technology Co., Ltd.

1999.12.21

SPCA506A1
5. Refresh Cycle Timing : CASNN
tCSR tCAS tCHR

RASNN

Symbol tCAS tCSR tCHR

Parameter CAS low pulse width CAS to RAS setup time RAS to CAS hold time

Min. -

Typ. 80 40 40

Max. -

Units ns ns ns

Notes

6. Serial EEPROM Timing :

ECS
tCSS tSKH tSKL tCSH tCS

ESK
tDIS tDIH

EDI
tPD0 tPD1 tDF

EDO (Read)
tSV tDF

EDO (Program)

Symbol tSKH tSKL tCS tCSS tDIS tCSH tPD1 tPD0 tSV tDF

Parameter ESK High Time ESK Low Time Minimum ECS Low Time ECS Setup Time EDI Setup Time ECS Hold Time Output Delay to 1 Output Delay to 0 ECS to Status Valid ECS to EDO in Z

Min. 0 0 0 0

Typ. 2.5 2.5 5 2.5 2.5 2.5 -

Max. 2.5 2.5 5.0 5.0

Units us us us us us us us us us us

Notes

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SPCA506A1
PACKAGE ASSIGNMENT AND DIMENSION PACKAGE Assignment

ovss nc nc nc nc nc nc nc ovdd nc nc nc nc nc gvdd gvss nc nc nc nc nc nc nc nc nc nc

103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 122 124 125 124 126 127 128

nc nc ovdd nc nc nc nc nc nc snapnn rstnn dvss dvdd xtalout xtalin audout aubclk audin ausync aurstnn edo edi esk ecs dvss dvdd md15 md14 md13 md12 md11 md10 md9 md8 md7 md6 ovdd ovss 111 99999999998888888888777777777766666 000 98765432109876543210987654321098765 210 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 md5 md4 md3 md2 md1 md0 mwenn moenn casnn dvss dvdd rasnn ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 gpio6 gpio5 ovdd ovss 128 pin package 123456789 11111111112222222222333333333 01234567890123456789012345678

Sunplus Technology Co., Ltd.

gpio4 gpio3 gpio2 gpio1/sda gpio0/scl dvss dvdd tvhd tvvd tvckk tvck tvdvalid tvfield tvvref tvhref gvdd tvy7 tvy6 tvy5 tvy4 tvy3 tvy2 tvy1 tvy0 gvss gvdd tvuv7 tvuv6/din tvuv5/dmi tvuv4/dpi tvuv3/suspend tvuv2/usboenn tvuv1/dmo tvuv0/dpo uvss dp dm uvdd
Global power/ground IO buffer power/ground internal cell power/ground USB cell power/ground

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SPCA506A1
PACKAGE Dimension
D D1 D2

E1

E2

SUNPLUS SPCA506A1
YYWW

A2

Symbol A A2 E E1 E2 D D1 D2 e b Unit: millimeter

Min. 2.5 17.20 14.00 12.50 23.20 20.00 18.50 0.50 0.17

Nom. 2.72 17.20 14.00 12.50 23.20 20.00 18.50 0.50 0.20

Max. 3.4 2.9 17.20 14.00 12.50 23.20 20.00 18.50 0.50 0.27

NOTE: SUNPLUS TECHNOLOGY CO., LTD reserves the right to make changes at any time without notice in order to improve the design and performance and to supply the best possible product.

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SPCA506A1
DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHER, SUNPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. SUNPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. reference purposes only. Please note that application circuits illustrated in this document are for

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