International Journal of Computer Trends and Technology (IJCTT) volume 4 Issue 7July 2013

A Comparative Study of 7T SRAM Cells

Mr. Kariyappa B S1, Mr. Basavaraj Madiwalar2, Mrs. Namitha Palecha3
1

Professor, 2M.Tech Student (VLSI Design & Embedded Systems), 3Assistant Professor, Dept. of ECE. RVCE Bengaluru, INDIA.

Abstract: - Memories are integral part of most of the digital devices and hence reducing power consumption of memory is very important in improving the system performance, efficiency and stability. In this paper a novel 7T SRAM cell is introduced and it is compared with the two existing 7T SRAM cells. The novel 7T SRAM cells power consumption is good compared to the 7T SRAM cell-1. The novel 7T SRAM cell has power reduction of 22.03% and SNM improvement of 2.32 times when compared to 7T SRAM cell-1 and 3.3 times better SNM compared to 7T SRAM cell-2. Schematics are drawn using virtuoso ADE (Analog Design Environment) of Cadence and all simulations are carried out using Cadence Spectre analyzer with 90nm Technology file at 1.8V Vdd. Keywords: - Single bit line, 7T-SRAM cell, low power, read stable, SRAM (Static Random Access Memory), SNM (Static Noise Margin), RNM (Read Noise Margin) and HSNM (Hold State Noise Margin).

write power consumption. To write "1", BLb is discharged to "0" with comparable power consumption to a conventional write. The write circuit will not discharge one of the bit lines for every write operation and the activity factor of discharging BLb is less than "1". During read operation, the cell behaves like a conventional 6T SRAM cell and N7 is kept on.

I.

INTRODUCTION

Most of the embedded and portable devices use SRAM (Static Random Access Memory) [3]. The SRAM can be designed using different types of cells (Ex. 6T SRAM cells, 7T SRAM cells, 8T SRAM cells etc.). Standard CMOS (Complementary Metal Oxide Semiconductor) 6T SRAM cell is used as conventional SRAM cell. It uses two bit-lines and a word line for both read and write operations. The 6T SRAM cell shows poor stability [4, 5] at small feature sizes. It also consumes lot of power. During read operation, the stability drastically decreases due to the voltage division between the access and driver transistors. 8T and 9T SRAM cells provide very high noise margins but they require more power and more area. In this paper a novel 7T SRAM cell is compared with two existing 7T SRAM cells in terms of their power consumption, delay and Static Noise Margins (SNMs). The existing 7T SRAM cells are shown in Fig 1 & Fig 2, and novel 7T SRAM cell is shown in Fig 3. A. 7T SRAM Cell-1 The 7T SRAM cell-1 [1] is shown in Fig 1. The 7T SRAM Cell-1 write concept depends on cutting off the feedback connection between the two inverters, before the write operation. The feedback connection and disconnection are performed through an extra NMOS transistor N7. The cell only depends on BLb to perform a write operation. The write operation starts by turning N7 off to cut off the feedback connection. BLbar transfers complement of the input data. The SRAM cell resembles like two cascaded inverters. BLb transfers the complement of input data to Qb this energies inv1, to develop Q, which intern drives inv2 and changes Q. Both BL and BLb are pre-charged "high" before and after each read/write operation. When writing "0", BLb is kept "high" with negligible

Fig 1: 7T SRAM Cell-1

B. 7T SRAM Cell-2

Fig 2: 7T SRAM Cell-2

The 7T SRAM Cell-2 [2] is shown in Fig 3. The 7T SRAM Cell-2 consists of 7 transistors. It is same as 6T SRAM cell with 7 th transistor in diode configuration between back to back converted inverter latch and power supply. Both read and write operations of the cell are same as that of conventional 6T SRAM cell. II. NOVEL 7T SRAM CELL Main objective of proposing this new 7T SRAM cell is to have good Read Stability and Static Noise Margins (SNMs). Novel 7T SRAM cell is shown in Fig 3. Novel SRAM cell is made up of seven transistors. This 7T SRAM cell uses single bit line (BL), a word line (WL), and a read line (RL).

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International Journal of Computer Trends and Technology (IJCTT) volume 4 Issue 7July 2013
C Hold operation of novel 7T SRAM cell

During hold state, Q and Qb nodes of 7T SRAM cell maintain the stored data until the power is available from the power supply. If data stored is 1, then Q=Vdd and Qb=0V. If data stored is 0, then Q=0V and Qb=Vdd. III. SIMULATION RESULTS A Comparison of novel 7T SRAM cell & 7T SRAM cell-1

Here novel 7T SRAM cell and 7T SRAM cell-1 are compared in terms of their power consumption, delay and SNMs. A.1 Power comparison between novel 7T SRAM cell and 7T SRAM cell-1 The power comparison between novel 7T SRAM cell and 7T SRAM cell-1 is shown in table 1. In all the read and write operation novel 7T SRAM cell consumes less power compared to 7T SRAM cell-1.
TABLE 1: POWER COMPARISON BETWEEN NOVEL 7T SRAM CELL & 7T SRAM CELL-1

Fig 3: Novel 7T SRAM cell

While writing into the cell, bit line (BL) and word line (WL) are used, where read line is not used (inactive). While reading from the cell bit line (BL) and read line (RL) are used, where word line (WL) is not used (inactive). For any operation novel 7T SRAM cell uses single bit line and word line or read line, that is only two lines for any operation. Since 7T SRAM cell uses only one bit line, power required for charging and discharging of one more bit line will be reduced. Hence usage of only one bit line reduces the power required to charge and discharge the bit lines to approximately half. The power consumption from charging the bit line decreases by approximately a factor of 2 because only one bit line is charged during a read operation instead of two. The bit line is charged during a write operation about half of the time instead of every time when a write operation is required, here equal probability of writing 0 and 1 has been assumed. The novel 7T SRAM cell uses two transistors N4 and N5 with read line (RL) for read operation. A Write operation of novel 7T SRAM cell

Operation WRITE 0 WRITE 1 READ 0 READ 1

7T SRAM cell-1 (uW) 8.11 7.572 8.322 9.526

Novel 7T SRAM Improvements cell (uW) 7.29 22.03% 7.73 17.33% 7.11 17.52% 6.70 21.36%

A.2 Delay comparison between novel 7T SRAM cell and 7T SRAM cell-1 The delay comparison between novel 7T SRAM cell and 7T SRAM cell-1 is shown in table 2. The performance of novel design in case of write operation is less compared to 7T SRAM cell-1 but the read performance is good.
TABLE 2: DELAY COMPARISON BETWEEN NOVEL 7T SRAM CELL & 7T SRAM CELL-1

Operation WRITE 0 WRITE 1 READ 0 READ 1

While writing, the data need to be written will be loaded on bit line (BL) and then word line (WL) will be activated. Strong access transistor N3 allows bit line to overpower the cell, so that required data will be written into the cell. To write 1 into the cell, the bit line (BL) is charged to Vdd. If the data need to be written is 0, then bit line should be at logic low, and then word line (WL) is pulled to Vdd. In write mode read line (RL) will be inactive (i.e. at logic 0). B Read operation of novel 7T SRAM cell

7T SRAM cell-1 (ps) 73.937 44.78 36.49 22.92

Novel 7T SRAM cell (ps) 85.7 139.3 35 0

A.3 SNM comparison between novel 7T SRAM cell and 7T SRAM cell-1 The Static Noise Margin comparison [6, 7] between novel design & 7T SRAM cell-1 is shown in table 3 and corresponding graphs in Fig 4. Static Noise Margins of novel designs are substantially good. There is 2.32 times improvement in read SNM and 1.17 times in hold SNM compared to 7T SRAM cell-1.
TABLE 3: SNMS COMPARISON BETWEEN NOVEL 7T SRAM CELL & 7T SRAM CELL-1

To read data from the cell, initially bit line (BL) is being pre-charged to Vdd. After pre-charging the bit line read line (RL) is activated. Depending upon whether the bit line (BL) discharges or holds the held charge, data stored in the 7T SRAM cell can be decided. If BL discharges after pulling the read line (RL) to Vdd, it indicates 7T SRAM cell is storing 0 in it. If bit line holds the held charge then the data stored is 1. In read mode WL is inactive (i.e. at logic 0).

SNM RSNM HSNM

7T SRAM cell-1 0.250 V 0.510 V

Novel 7T SRAM cell 0.580 V 0.595 V

Improvements 2.32 times 1.17 times

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International Journal of Computer Trends and Technology (IJCTT) volume 4 Issue 7July 2013

RSNM of 7T SRAM cell-1

HSNM of 7T SRAM cell-1

RSNM of novel 7T SRAM cell

HSNM of novel 7T SRAM cell

Fig 4: SNM Comparison of novel 7T SRAM cell and 7T SRAM cell-1

RSNM of 7T SRAM cell-2

HSNM of 7T SRAM cell-2

RSNM of novel 7T SRAM cell

HSNM of novel 7T SRAM cell

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Fig 5: SNM Comparison of novel 7T SRAM cell and 7T SRAM cell-2

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B Comparison of novel 7T SRAM cell & 7T SRAM cell-2 novel 7T SRAM cell. The cell works faithfully in worst conditions, if its SNM is very good otherwise the cell is susceptible to very small noise and may corrupt the data. The speed of novel 7T SRAM cell is a bit less compared to other two 7T cells but its SNM is 2.3 times high and 3.3 times high as compared to 7T SRAM cell-1 and 7T SRAM cell-2 respectively. The high SNM of novel 7T SRAM cell makes it very immune to noise and helps in faithful storage of written data. REFERENCES
[1] Anie Jain, Shyam Akashe, Optimization of low power 7T SRAM cell in 45nm Technology, IEEE Second International Conference on Advanced Computing & Communication Technologies. 978-0-7695-4640-7/12 2012, pp.324-327. [2] Shyam Akashe, Shishir Rastogi, Sanjay Sharma, Specific Power Illustration of Proposed 7T SRAM with 6T SRAM Using 45 nm Technology, International Conference on Nanoscience, Engineering and Technology (ICONSET), Chennai, India, 10.1109/ICONSET.2011.6167982,21111 2011, pp.364-369. [3] Sanjeev K. Jain/ Pankaj Agarwal, A Low Leakage and SNM Free SRAM Cell Design in Deep Sub micron CMOS Technology, 19th International Conference on VLSI Design (VLSID06)1063-9667 2006 IEEE. [4] Paridhi Athe and S. Dasgupta, A Comparative Study of 6T, 8T and 9T Decanano SRAM cell, 978-1-4244-4683-4/09 2009 IEEE. [5] Arash Azizi Mazreah, Mohammad Reza Sahebi, Mohammad Taghi Manzuri, S. Javad Hosseini, A Novel Zero-Aware Four-Transistor SRAM Cell for High Density and Low Power Cache Application, 978-0-7695-3489-3/08 2008 IEEEDOI 10.1109/ICACTE.2008. [6] B. Alorda, G. Torrens, S. Bota and J. Segura, Static-Noise Margin Analysis during Read Operation of 6T SRAM Cells, unpublished. [7] Seevinck, E., List, F.J., Lohstroh, J. Static-Noise Margin Analysis of MOS SRAM Cells, IEEE Journal of Solid-State Circuits, SC-22, 5 (Oct. 1987), 748-754.

Here novel 7T SRAM cell and 7T SRAM cell-2 are compared in terms of their power consumption, delay and SNMs. B.1 Power comparison between novel 7T SRAM cell and 7T SRAM cell-2 The power comparison between novel 7T SRAM cell and 7T SRAM cell-2 is shown in table 4. The novel 7T SRAM cell consumes more power compared to 7T SRAM cell-2 but 7T SRAM cell-2 lacks in good SNMs as shown in table 6. The cell which has small SNMs is more susceptible for noises and dont ensure the protection of data. Therefore 7T SRAM cell-2 design is not a good SRAM cell design.
TABLE 4: POWER COMPARISON BETWEEN NOVEL 7T SRAM CELL & 7T SRAM CELL-2

Operation WRITE 0 WRITE 1 READ 0 READ 1

7T SRAM cell-2 (uW) 3.135 3.135 3.3166 3.3166

Novel 7T SRAM cell (uW) 7.29 7.73 7.11 6.70

B.2 Delay comparison between novel 7T SRAM cell and 7T SRAM cell-2 The delay comparison between novel 7T SRAM cell and 7T SRAM cell-2 is shown in table 5. The performance of novel design in case of write operation is less compared to 7T SRAM cell-2 but the read performance comparable.
TABLE 5: DELAY COMPARISON BETWEEN NOVEL 7T SRAM CELL & 7T SRAM CELL-2

Operation WRITE 0 WRITE 1 READ 0 READ 1

7T SRAM cell-2 (ps) 66.259 66.066 22.85 22.86

Novel 7T SRAM cell (ps) 85.7 139.3 35 0

B.3 SNM comparison between novel 7T SRAM cell and 7T SRAM cell-2 The Static Noise Margin [6, 7] comparison between novel design and 7T SRAM cell-2 is shown in table 6 and corresponding graphs in Fig 5. SNMs of novel designs are significantly good. There is 3.31 times improvement in read SNM and 1.35 times in hold SNM compared to 7T SRAM cell-2.
TABLE 6: SNMS COMPARISON BETWEEN NOVEL 7T SRAM CELL & 7T SRAM CELL-2

SNM RSNM HSNM

Conventional 6T SRAM cell 0.175 V 0.440 V

Novel 7T SRAM cell 0.580 V 0.595 V

Improvements 3.31 times 1.35 times

IV. CONCLUSIONS The power consumption of novel 7T SRAM cell lies between existing 7T SRAM cell-1 and cell-2. The proposed 7T SRAM cell gives better SNM compared to existing 7T SRAM cell-1 and cell-2. The 7T SRAM cell-2s speed and power consumptions are good but its SNM is very poor compared to the

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