03 Assembly Techniques and Packaging

UNIVERSITI TUNKU ABDUL RAHMAN
Assembly Techniques and Packaging
Dr. Lim Soo King 05/15/2012
Chapter 3 Assembly Techniques and Packaging .............................4

3.0 Introduction ................................................................................................ 4 3.1 Assembly Technologies .............................................................................. 4
3.2.1 Electrical requirements ....................................................................................... 9 3.2.2 Mechanical and Thermal properties ................................................................ 13 3.2.3 Cost ...................................................................................................................... 16
3.3 Packaging Level Integration ................................................................... 16

3.3.1 Interconnect Levels ............................................................................................ 17 3.3.1 Interconnect Level 1 - Die-to-Package-Substrate............................................ 18 3.3.2 Interconnect Level 2 - Package Substrate to Board........................................ 20 3.3.3 Multi-Chip Modules - Die to Printed Wire Board .......................................... 22
3.4 Assembly Techniques and Processes ...................................................... 24

3.4.1 Wafer Preparation ............................................................................................. 26 3.4.2 Die Attach ........................................................................................................... 26
3.4.2.1 Eutectic Die Attach .......................................................................................................... 27 3.4.2.2 Epoxy Die Attach ............................................................................................................. 28
3.4.3 Wire Bonding...................................................................................................... 28 3.4.4 Molding/Glass Seal ............................................................................................. 29 3.4.5 Post Mold Cure/Leak Check ............................................................................. 31 3.4.6 Solder Dip/Tin Plate........................................................................................... 31 3.4.7 Trim/Form .......................................................................................................... 33 3.4.8 Inspection ............................................................................................................ 33
Exercises .......................................................................................................... 33 Answers of Exercises ...................................................................................... 34 Bibliography ................................................................................................... 36
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Figure 3.1: Figure 3.2: Figure 3.3: Figure 3.4: Figure 3.5: Figure 3.6: Figure 3.7: Figure 3.8: Figure 3.9: Figure 3.10: Figure 3.11: Figure 3.12: Figure 3.13: Figure 3.14: Figure 3.15: Figure 3.16: Figure 3.16: Figure 3.18: Figure 3.19: Figure 3.20: Figure 3.21: Figure 3.22: Figure 3.23: Figure 3.34:
Figure 3.25: Figure 3.26:
Variety of Package types for both plastic and hermetic surface mount and through-hole mount ............................................................................................ 5 A hermetic package showing the integrated circuit is decoupled from external environment ....................................................................................................... 6 A plastic package showing the integrated circuit is not decoupled from external environment ......................................................................................... 6 A plastic package showing the integrated circuit is not decoupled from external environment ......................................................................................... 7 Rents constant for varies class of chip and system figure ................................ 8 Dielectric constant of common packaging materials ....................................... 10 Cross sectional structure for impedance control. (a) Microstrip line, (b) Strip line, and (c) coplanar structure......................................................................... 11 Typial types of noise; (a) cross talk noise and (b) switching noise ................. 13 Cross sectional view of multi-layer lead frame package and the heat transfer mechanism ....................................................................................................... 15 Integrated circuit packaging level ................................................................... 17 Interconnect hierarchy in traditional integrated circuit packaging .................. 18 Wiring bonding connecting pad and lead ........................................................ 18 Typical conductance and inductance of package type and wire ...................... 19 Automated tap bonding (a) polymer with imprinted wire pattern and (b) die attach using solder bump ................................................................................. 19 Flip-chip bonding ............................................................................................. 20 Printed circuit board mounting approach. (a) through-hole mounting and (b) surface mounting .............................................................................................. 20 Commonly use package (1) leadless carrier, (2) DIP, (3) PGA, (4) small outline IC, (5) quad flatpack, and (6) PLCC .................................................... 21 Parameters of various chip carriers .................................................................. 22 Ball grid array packaging; (a) cross-section, (b) photo of PGA bottom .......... 22 An Avionics processor module. Courtesy of Rockwell International ............. 23 Generic electronics packaging assembly sequence for plastic and ceramic package ............................................................................................................ 26 The basic structure of a silicon device die attach with a metal preform .......... 27 Structure of ceramic dual inline package (cerdip) showing the base, the lead frame and a lid with sealing glass .................................................................... 30 Schematics of a multi-pot transfer-mold system showing small mold compound tablets with each large enough to fill a few cavities containing plastic strips ..................................................................................................... 31 Molded plastic package strip showing short between tips of the lead, tight bar and guide pin hole ............................................................................................ 32 The formed molded plastic dip package strip shows that tight bar has not been removed............................................................................................................ 32
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Chapter 3 Assembly Techniques and Packaging _____________________________________________

3.0 Introduction
Assembly techniques and packaging involve process of choosing the right type of package for a particular integrated circuit type and assemble the integrated circuit in the form of die into package that can be used for application.
3.1 Assembly Technologies

There are many assembly technologies available in todays assembly of integrated circuit into package device that can be used to insert into printed wire board PWB for application. The most common assembly technologies are the plastics and hermetic assembly technologies. The plastic assembly can be subdivided into various package style both for surface mount SM and through-hole TH mount assembly techniques. Plastic package styles can be plastic dual inline package PDIP, plastic quad flat package PQFP, single outline package SOP, plastic leadless chip carrier PLCC, small outline integrated circuit SOIC etc. The technology to assemble these package various especially the wire bond, mold, and plating operation. The overview of the package types is shown in Fig. 3.1. Note that no all available package styles are shown. Hermetic assembly technology is basically used to assemble high reliability integrated circuit that are used in industrial, military, and outer space applications. In this case, the integrated circuit is decoupled from external environment by a vacuum-tight enclosure. Common packages that are assembled using this technology are ceramic dual inline package CDIP, pin grid array PGA, ball grid array BGA etc. An A typical hermetic package with a silicon chip placed in the cavity of a ceramic-based package and wedge-bonded to make electrical connections to the terminals on the package is shown in Fig. 3.2.
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03 Assembly Techniques and Packaging
Figure 3.1: Variety of Package types for both plastic and hermetic surface mount and through-hole mount -5-
Figure 3.2: A hermetic package showing the integrated circuit is decoupled from external environment
Plastic assembly technology is usually used to assembly high volume, low cost integrated circuit. The integrated circuit or die is not decoupled from external environment. The die is in contact with expoxy resin, whereby in long run environment contaminant can penetrate the plastic to reach the integrated circuit causing reliability issue. However, with todays technology, plastic package device begins gain acceptable for housing high reliability product. A typical plastic package structure consisting of a silicon die, a metal lead frame, and a plastic molding compound is shown in Fig. 3.3.
Figure 3.3: A plastic package showing the integrated circuit is not decoupled from external environment -6-
Since many of them are used in electronic application, memory device usually is low cost. The need for low cost memory device has been driving the trend for cheaper plastic package. A variety of SM plastic packages such as SOJ, SOP, and thin SOP TSOP has been developed for industrial use, Except for TSOP, these packages have typically 2 mm thick body. TSOP packages have 1-mmthick plastic body suitable for compact application. As the chip occupancy continues to grow and the stringent requirements, this imposes have led to considerable changes in package structures. The lead-on-chip LOC structure, in which wire interconnection within the package are made above the die circuitry surface is notable. In conventional packages for older-generation devices, such as that these shown in Fig. 3.2 and Fig. 3.3, the interconnection is made only in the periphery and outside the die area. Exploiting an additional area for the interconnections and reducing wire length. A typical lead-on-chip LOC package is shown in Fig. 3.4. Here the tips of the lead frame extend over the chip surface, and Au wires are stitch-bonded to the lead frame tips to connect them with the chip bonding pads, which are located in the interior of the chip area. The LOC structure increases the chip occupancy to more than 70% of the package area. The structure provides die design flexibility because it allows the pads to be located on the chip in almost any position. It also allows the placement of substitutes for additional inner lead portions or bus-bars that work as alternatives to power and ground Al metallizations on the die circuitry. The bus-bars are numerous in some high-speed memory designs, since they can enhance the electrical performance of electrical performance of the device without increasing die size.
Figure 3.4: A plastic package showing the integrated circuit is not decoupled from external environment -7-
3.2 Packaging Design

Integrated circuit package plays a fundamental role in the operation and performance of a component. Besides providing a mean of bringing electrical signal and voltage supply via wires in and out of the silicon die, it also removes heat generated by the circuit and provides mechanical support. It also protects the integrated circuit against environmental conditions such as humidity and heat. Furthermore the package has a major impact on the performance and power dissipation of the integrated circuit like the microprocessor and signal processor. This influence is getting more pronounced as technology scaling down progressed due to reduction of internal signal delays and on-chip capacitance. Up to 50% of the delay of a high-performance computer is due to packaging delay caused by inductive and capacitive parasitic from packing material. The increasing complexity of circuit integrated into a single die also translates into a need for ever more input-output pins. This is because the number of connections is roughly proportional to the complexity of the circuitry on the chip. This relationship was first observed by E. Rent of IBM, who translated it into an empirical formula called Rents rule. This formula relates the number of input/output pins P to the complexity of the circuit as measured by the number of gates. P = kG (3.1)
where k is the average number of I/Os per gate, G the number of gates, and the Rent exponent. varies between 0.1 and 0.7. The value is strongly dependent on the application area, architecture, and organization of the circuit, as shown in Fig. 3.5. Chip/System Static memory Microprocessor Gate array High speed computer - chip High speed computer -circuit 0.12 0.45 0.50 0.63 0.25 K 6.00 0.82 1.90 1.40 82.0
Figure 3.5: Rents constant for varies class of chip and system figure
It is clearly shown that microprocessors display a very different input/output behavior compared to memories. The observed rate of pin-count increase for integrated circuits varies between 8% to 11% per year and it has been projected that packages with more than 2,000 pins will be required by the year 2010. For
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all these reasons, traditional dual-in-line, through-hole mounted packages have been replaced by other approaches such as surface-mount, ball grid array, and multichip module techniques. It is useful for the circuit designer to aware of the available options, and their advantages and disadvantages. Owing to its multi-functionality, a good package must comply with a large variety of requirements namely the electrical, mechanical, thermal, and cost requirements.
3.2.1 Electrical requirements

As the speed of integrated circuit increases, their noise margin decreases. Thus, electricl design for package must be carefully considered. The pins should exhibit low capacitance - both inter-wire and to the substrate, resistance, and inductance. Large characteristic impedance should be tuned to optimize transmission line behavior and observe that intrinsic integrated circuit impedances are high. Packages with a design geometry larger than the silicon can significantly affect the electrical performance of the packaged chips. Several electrical performance criteria are important such as minimum signal delay, signal-reflection control, and noise reduction, including simultaneous switching noise and cross talk. These criteria, often discussed in PWB design, which is also applied to the package. They are mutually dependent and require trade off. Signal Delay The signal delay time td is defined by equation (3.2). td =
l l = c / r
(3.2)
where l is the length of signal line, v is the velocity of sigal, c is the velocity of light, and r is the dielectric constant of the surrounding material. High-speed operation requires smaller td. The ratio of td to the cycle time usually dominates the system performance. In package construction, a short signal line including bonding wire length and lead length in small dielectric material typically polyimide resin is preferred. Table 3 lists the dielectric constants of common packaging materials. An excessively small dielectricconstant of the surrounding material induces signal reflections that degrade
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operating speed. Hence, an optimum dielectric value is required. The dielectric constant of the common packaging material is shown in Fig. 3.6. Materials Al2O3 AlN Mold compound Polyamide Si GaAs SiO2 Glass ceramic Glass epoxy Dielectric Constant at 1.0MHz 9.6 10.2 8.7 3.9- 4.3 3.5 11.7 12.9 3.9 3.9- 7.8 4.2
Figure 3.6: Dielectric constant of common packaging materials
Signal Reflection A mismatched impedance causes signal reflections when a signal is transmitted from a driver to a receiver through a transmission line. In CMOS VLSI/ULSI devices, multiple reflections occur at the driver and receiver ends when the output impedance of the output buffer is smaller than that of the transmission line. These reflections cause a ringing phenomenon that may slow down operation or cause the circuit to malfunction. These reflections cannot be treated lightly when the relationship exists as shown in equation (3.3).
l> ct r 0.35 r
(3.3)
where l is the signal line length, c is the velocity of the light, r is the dielectric constant of the surrounding material, v is the critical frequency, and tr is the signal fall) time. The equations show that a shorter signal line l is required for high-speed operation that needs a smaller package size. Larger package constructions have longer signal lines that cannot be dealt with as lumpedelement circuits but it must consider distributed-element circuits. Longer wires, longer via hole connects that have larger impedance-mismatch potentials, should be avoided if possible or matched-impedance designs should be used instead. Leading edge package such as themulti-lead frame plastic packages, and some other multi-layered packages containing strip, microstrip, or coplanar constructions provides better impedance matching. Figure 3.7 illustrates the strip, microstrip, and coplanar structures used for impedance control.
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(a) (b) (c) Figure 3.7: Cross sectional structure for impedance control. (a) Microstrip line, (b) Strip line, and (c) coplanar structure
The characteristic impedances Zo of strip, microstrip, and coplanar structures are expressed by equation (3.4), (3.5), and (3.6) respectively.
Zo = 60 4b ln r 0.67 W (0.8 + t / W )
strip
(3.4)
Zo =
87 5.98h ln r + 1.41 0.8W + t
microstrip
(3.5)
Zo =
1 + S /(2 W + S) o ln 2 ( r + 1) / 2 1 S /(2 W + S)
coplanar
(3.6)
where r is the dielectric constant of the dielectric material, t and W are the thickness and width of the conductor, and h and b are the thicknesses of the dielectric material beneath and surrounding the conductor respectively. For a typical coplanar structure such as a symmetrical double-strip, where o (equal to 120) is the characteristic impedance of free space. S is the gap between the two lines and W is the width of the line. Assumptions are that the conductor lines are infinitely thin (t = 0), the dielectric material is infinitely thick (h = ), and the gap widths range is 0.173 < S/(2W + S) < 1. Noise Two typical types of noise are cross-talk noise and simultaneous switching noise (I noise) are found in integrated circuit. Cross-talk noise as shown in Fig. 3.8(a) occurs when a line is undesirably affected by another line that is placed very close to it because of the electromagnetic coupling between the two lines. The noise, coupled by Cm, Lm, or both (m: mutual) between the two lines,
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increases in proportion to the signal-voltage or current gradient and the accoupling strength. Cross-talk noise is a more serious problem in VLSI/ULSI packaging intended to handle higher speeds, larger signal counts, and the resulting narrow signal-line spacings. Major counter measures in package design are shorter parallel signal runs, closer ground or power planes, and lower dielectric-constant materials.
(a)
(b) - 12 -
03 Assembly Techniques and Packaging Figure 3.8: Typial types of noise; (a) cross talk noise and (b) switching noise
Simultaneous switching noise, one of the most practical electrical design problems, particularly in CMOS ASIC devices, occurs when many output buffers switch simultaneously. Figure 3.8(b) illustrates the mechanism. When an output buffer switches from high to low, transition current i flows from the power line VCC into the load capacitance Cl inducing the noise voltage given by equation (3.8).
Vn = L g di dt
(3.8)
where Vn is the induced voltage, Lg is the inductance of the power lead, and di/dt is the derivative of current with respect to time. In addition, when a line switches from low to high, an electric charge stored in the load capacitance flows into the ground line through the transmission line, inducing the same noise voltage as shown in equation (3.9). If j line is switching simultaneouslythen Vn is given by
Vn = L g
j
di dt
(3.9)
3.2.2 Mechanical and Thermal properties

Package should be designed in such the heat removal rate should be as high as possible. Mechanical reliability requires a good matching between the thermal properties like the coefficient of thermal expansion CTE of the integrated circuit and the chip carrier. Long term reliability requires a strong connection from die to package as well as from package to printed circuit board. As the power consumption of integrated circuits rises, it becomes increasingly important to efficiently remove the heat generated by the die. A large number of failure mechanisms in integrated circuit are accentuated by increase of temperature. Examples are leakage in reverse biased diodes, electromigration, and hot electron trapping. To prevent failure, temperature of the die must be kept within certain ranges. The temperature range for commercial graded devices is between 0 and 70C. Military parts are more demanding and require a temperature range varying from -55 to 125C. The cooling effectiveness of a package depends upon the thermal conduction of the package material, which consists of the package substrate and
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body, the package composition, and the effectiveness of the heat transfer between package and cooling medium. As for the microprocessor device and other high performance device such video device used in graphic card of a computer, thermal interface material TIM is used to reduce thermal impedance between the device and heat sink. TIM is a type of conductive paste used to fill any void or irregularity between the device and heat sink. Standard packaging approaches use still or circulating air as the cooling medium. The transfer efficiency can be improved by adding finned metal heat sinks to the package. More expensive packaging approaches, such as those used in mainframes or super computers, force air, liquids, or inert gases through tiny ducts in the package to achieve even greater cooling efficiencies. As an example, a 40-pin DIP has a thermal resistance of 38C/W and 25C/W for natural and forced convection air. This means that a DIP can dissipate 2 watts (3 watts) of power with natural (forced) air convection, and still keep the temperature difference between the die and the environment below 75C. For comparison, the thermal resistance of a ceramic PGA ranges from 15 to 30C/W. Since packaging approaches with decreased thermal resistance are prohibitively expensive, keeping the power dissipation of an integrated circuit within bounds is an economic necessity. The increasing integration levels and circuit performance make this task nontrivial. An interesting relationship shown in equation (3.9) has been derived by Nagata. It provides a bound on the integration complexity and performance as a function of the thermal parameters.
N G T tp E
(3.9)
where NG is the number of gates on the chip, tp the propagation delay, T the maximum temperature difference between chip and ambient environment, the thermal resistance between them, and E the switching energy of each gate. Fortunately, not all gates are operating simultaneously in real systems. The maximum number of gates can be substantially larger, based on the activity coefficient in the circuit. For instance, it was experimentally derived that the ratio between the average switching period and the propagation delay ranges from 20 to 200 in mini- and large-scale computers. Nevertheless, equation (3.9) demonstrates that heat dissipation and thermal concern present an important limitation on circuit integration. Design
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approaches for low power that reduce either E or the activity coefficient are rapidly gaining importance. Lets consider from the aspect of the thermal resistance ja of a package as shown in Fig. 3.9.
Figure 3.9: Cross sectional view of multi-layer lead frame package and the heat transfer mechanism
The thermal resistance of a package is defined

ja = Tj Ta P
(3.10)
where ja in 0C/W is the junction to ambient thermal resistance, Tj is the average chip or junction temperature, Ta is the ambient temperature, and P is the power dissipation. Figure 3.9 is also a simplified heat-transfer model of a packaged die, where heat is transferred from the die to the surface of the package by conduction and from the package surface to the ambient by convection and radiation. In most applications, the temperature difference between the case or the package surface and the ambient is small. Thus, radiation can be neglected. Conduction heat transfer through the package terminals can be significant, particularly in highI/O VLSI/ULSI packages. However, if one neglects it for simplification, the overall thermal resistance in this model can be considered as the sum of two thermal components, which are jc and ca and is defined
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03 Assembly Techniques and Packaging ja = jc + ca = Tj Tc P + Tc Ta P
(3.11)
where jc is the junction to case thermal resistance, ca is the case to ambient thermal resistance, and TC is the average case temperature. jC is relatively insensitive to the ambient and is mainly a function of package materials and geometry. ca depends on the package geometry, the package orientation in the application, and the conditions of the ambient in the operating environment whether heat transfer is free or by forced-convection. Heat transfer is classified into three categories conduction, convection, and radiation. We shall not discuss here.
3.2.3 Cost
Cost is always one of the most important requirements. Ceramic package has a superior performance over plastic package but it is also substantially more expensive. Increasing the heat removal capacity of a package also tends to raise the package cost. The least expensive plastic package can dissipate up to 1.0W of heat. More expensive but still cheap plastic package can dissipate up to 2.0W. Higher heat dissipation requires more expensive ceramic package. Chips dissipating over 50.0W require special heat sink attachment. Extreme techniques such as fans and blowers, liquid cooling hardware, or heat pipes, are needed for higher dissipation levels. Packing density is a major factor in reducing the cost of the printed circuit board. The increasing pin count either requires an increase in the package size or a reduction in the pitch between the pins. Both have a profound effect on the cost of package.
3.3 Packaging Level Integration

As circuit integration proceeds on the die, it also proceeds in the packaging through interactions among several levels of packaging. Generally, packaging exclusive of the final system construction is classified into three levels, as shown in Fig. 3.10. Final system requirements determine a specific selection of the packaging method or how to combine the levels. Types 1 through 4 show the major methods that have been used in the industry. Type 1 is the most common choice. In type 1, the die is first packaged as a single chip and then packaged at the third level, typically at the PWB level. Types 2 and 3, usually called multi-chip-module MCM technologies, are used in high performance systems, typically in mainframe computer. In type 2, the die is single-diepackaged as in type 1, and the packaged dices are then packaged at the second
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level onto a smaller substrate; this forms a functionally larger and geometrically smaller unit and utilizes the finer multilayer wiring of the substrate. The substrate is attached to a larger mother board in the third-level packaging. Type 3 is similar to type 2 in that it uses a smaller substrate as an intermediary stage. However, bare chips are attached directly to the substrate, usually providing a superior electrical and geometrical performance but with some disadvantages, such as more difficult testability, increased cost, and lower yield. Type 4 is the simplest way of packaging, where bare dices are attached directly to the system board. The brief descriptions of the various type packaging level integrations are mentioned in the sub-sections below.
Figure 3.10: Integrated circuit packaging level
3.3.1 Interconnect Levels

The traditional packaging approach uses a two-level interconnection strategy. The die is first attached to an individual chip carrier or package. The package body contains an internal cavity where the chip is mounted. These cavities provide ample room for many connections between chip and leads. The leads compose the second interconnect level and connect the chip to the external interconnect medium, which is normally the printed circuit board. Complex systems contain even more interconnect levels, since boards are connected together using backplanes or ribbon cables. The first two layers of the interconnect hierarchy are illustrated in the drawing of Fig. 3.11.
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Figure 3.11: Interconnect hierarchy in traditional integrated circuit packaging
The interconnect techniques used at levels one and two of the interconnect hierarchy are shown here.
3.3.1 Interconnect Level 1 - Die-to-Package-Substrate

Traditionally wire bonding is the technique of choice to provide an electrical connection between die and package. In this approach, the backside of the die is attached to the substrate using glue with a good thermal conductance. Next, the chip pads are individually connected to the lead frame with aluminum or gold wire. An example of wire bonding is shown in Fig. 3.12. Although the wirebonding process is automated, it has some major disadvantages.
Figure 3.12: Wiring bonding connecting pad and lead
Wire must be attached serially one after the other. The lead time is longer with increasing pin counts. Larger pin counts make it substantially more challenging to find bonding patterns that avoid shorts between the wires. Bonding wire has inferior electrical properties such as a high individual inductance (5nH or more) and mutual inductance with neighboring signals. The inductance of a bonding
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wire is typically about 1.0nH/mm, while the inductance per package pin ranges between 7.0 and 40.0nH per pin depending on the type of package as well as the positioning of the pin on the package boundary. Typical values of the parasitic inductances and capacitances for a number of commonly used packages are summarized in Fig. 3.13. Package Type 68 pin plastic DIP 68 pin ceramic DIP 256 pin grid array Wire bond Solder bump Capacitance pF 4 7 1-5 0.5-1 0.1-0.5 Inductance nH 35 20 2-15 1-2 0.01-0.1
Figure 3.13: Typical conductance and inductance of package type and wire
The exact value of the parasitic component is hard to predict because of the manufacturing approach and irregular outlay. New attachment techniques are being used as a result of these deficiencies. In one approach is called Tape Automated Bonding TAB. The die is attached to a metal lead frame that is printed on a polymer film typically polyimide as shown in Fig. 3.14(a). The connection between chip pad and polymer film is wired by solder bump as shown in Fig. 3.14(b). The tape can then be connected to the package body using a number of techniques. One approach is using pressure connection.
(a) (b) Figure 3.14: Automated tap bonding (a) polymer with imprinted wire pattern and (b) die attach using solder bump
There are many advantages of the TAB process. Besides the process is highly automated, the sprockets in the film are used for automatic transport, and all wire connections are made simultaneously. The printed approach helps to
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reduce the wiring pitch, which results in higher lead counts. Elimination of the long bonding wires improves the electrical performance. Another approach is to flip the die upside down and attach it directly to the substrate using solder bumps. This technique, called flip-chip mounting, has the advantage of a superior electrical performance as shown in Fig. 3.15. Instead of making all the I/O connections on the die boundary, pads can be placed at any position on the chip. This can help to address the power and clock distribution problems, since the interconnect materials on the substrate are typically copper Cu or gold Au that have better quality than the aluminum (Al) on the chip.
Figure 3.15: Flip-chip bonding
3.3.2 Interconnect Level 2 - Package Substrate to Board

When connecting the package to the printed circuit board PCB, through-hole mounting has been the packaging style of choice. A PCB is manufactured by stacking layers of copper and insulating epoxy glass. In the through-hole mounting approach, holes are drilled through the board and plated with copper. The package pins are inserted and electrical connection is made with solder as shown in Fig. 3.16(a). The traditional package in this class is the dual-in-line package DIP. The packaging density of the DIP degrades rapidly when the number of pins exceeds 64. This problem can be alleviated by using the pingrid-array PGA package that has leads on the entire bottom surface instead of only on the periphery. PGA package can extend to large pin counts over 400 pins.
(a) (b) Figure 3.16: Printed circuit board mounting approach. (a) through-hole mounting and (b) surface mounting
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The through-hole mounting approach offers a mechanically reliable and sturdy connection. However, the setback is the packaging density. For mechanical and sturdy reasons, a minimum pitch of 2.54mm between the through-holes is required. Even with this pitch, PGAs with large numbers of pins would also substantially weaken the printed circuit board. In addition, through-holes limit the board packing density by blocking lines that might otherwise have been routed below them, which results in longer interconnections. PGAs with large pin counts hence require extra routing layers to connect to the huge number of pins. Although the parasitic capacitance and inductance of the PGA are slightly lower than DIP, their values are still substantially large. These shortcomings of the through-hole mounting can be solved by using the surface mount technique. A chip is attached to the surface of the board with a solder connection without requiring any through-holes as shown in Fig. 3.16(b). Consequently, surface mount increases packing density due to elimination of through-holes mounting that provides more wiring space and mechanically strengthens the PCB. The lead pitch is reduced and chips can be mounted on both sides of the board. The negative effects of the surface mount are many. The connection makes the connection of printed circuit board weak. It is also cumbersome to mount a component on a board that requires expensive mounting equipment, difficult for board repair, and finally testing of board is more complex because the package pins are no longer accessible at the backside of the board. Signal probing harder or even impossible. A variety of surface mount packages is currently in use with different pitch and pin count parameters. Four of these packages are shown in Fig. 3.16: the small-outline package SOIC with gull wings, the plastic leaded package PLCC with J-shaped leads, the leadless chip carrier LCC, and quad flat pack QFP.
Figure 3.16: Commonly use package (1) leadless carrier, (2) DIP, (3) PGA, (4) small outline IC, (5) quad flatpack, and (6) PLCC - 21 -
An overview of the most important parameters for a number of packages is shown in Fig. 3.18. Package Type Dual in Line DIP Pin Grid Array PGA Small Outline IC SOIC Plastic Leadless Chip Carrier PLCC Leadless Chip Carrier LCC Typical Lead Spacing 2.54mm 2.54mm 1.27mm 1.27mm 0.75mm Maximum Lead Count 64 >300 28 124 124
Figure 3.18: Parameters of various chip carriers
Even surface mount packaging is unable to satisfy the quest for evermore higher pin counts. This is worsened by the demand for power connections in high performance chips, operating at low supply voltages, require as many power and ground pins as signal I/O. When more than 300 I/O connections are needed, solder balls replace pins as the preferred interconnect medium between package and board. An example of such a packaging approach, called ceramic ball grid array (BGA) is shown in Fig. 3.19. Solder bumps are used to connect both the die to the package substrate and the package to the board. The area array interconnect of the BGA provides constant input/output density regardless of the number of total package I/O pins. A minimum pitch between solder balls as low as 0.8mm can be obtained, and packages with multiple 1000s of I/O signals are feasible.
(a) (b) Figure 3.19: Ball grid array packaging; (a) cross-section, (b) photo of PGA bottom
3.3.3 Multi-Chip Modules - Die to Printed Wire Board

The deep hierarchy of interconnect levels in the package is becoming unacceptable in modern complex circuit designs with higher levels of
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integration, large number of signals, and performance requirements. There is a need to reduce the number of levels. At the meantime, attention is focused on the elimination of the first level in the packaging hierarchy, which is eliminating die to package level by mounting the die directly on the wiring backplanes board or substrate. It offers a substantial benefit when performance or density is a major concern. This packaging approach is called multichip module MCM. As the result, there is a substantial increase in packing density as well as improved performance. A number of the previously mentioned die mounting techniques can be adapted to mount dice directly on the substrate. This includes wire bonding, Tape Automated Bonding TAB, and flip chip, although the later two are preferable. The substrate itself can be varying over a wide range of materials depending upon the required mechanical, electrical, thermal, and cost requirements. Materials of choice are epoxy substrates similar to printed circuit boards, metal, ceramics, and silicon. Silicon has the advantage of presenting a perfect match in mechanical and thermal properties with respect to the die material. The main advantages of the MCM approach are; it increases packaging density and and devices performance. An example of an MCM module implemented using a silicon substrate; commonly dubbed silicon-on-silicon is shown in Fig. 3.20. The module that implements an avionics processor module and is fabricated by Rockwell International contains 53 ICs and 40 discrete devices on a 2.2x2.2 substrate with aluminum polyimide interconnect.
Figure 3.20: An Avionics processor module. Courtesy of Rockwell International - 23 -
The interconnect wires of the module are only an order of magnitude wider than what is typical for on-chip wires because similar patterning approaches are used. The module itself has 180 I/O pins. Performance is improved by the elimination of the chip to carrier layer with variety of parasitic components, and through a reduction of the global wiring lengths on the die, a result of the increased packaging density. For instance, a solder bump has an assorted capacitance and inductance of only 0.1pF and 0.01nH respectively. The MCM technology can also reduce power consumption significantly, since large output drivers and associated dissipation become redundant due to the reduced load capacitance of the output pads. While MCM technology offers some clear benefits, its main disadvantage is economic. This technology requires some advanced manufacturing steps that make the process expensive. The approach is only justifiable when either dense housing or extreme performance is essential. In the near future, this argument might become obsolete as MCM approaches proliferate.
3.4 Assembly Techniques and Processes

This section describes the basic assembly processes and techniques used for assembly ceramic and plastic packaged VLSI device. The processes cover a number of assembly steps from wafer preparation through die attach, including wire bonding, encapsulation/molding, stabilization bake/post mold bake, temperature cycle to tin plating/solder plating, trim/form, and inspection. Student will learn these process steps based on the generic assembly sequence shown in Fig. 3.21 and at the same time understanding the physics of technique for process step. The generic assembly process steps are mainly for ceramic and plastic packaged integrated circuit or die. The first step is the preparation of wafer step, which basically cuts and separates the die from the wafer. The second process step is the die attach. It is a process step that bonding the die to the paddle of the package. The third step is the wire bonding, which is the process of connecting the bond pad on the die to the lead of the package. This step allows the die to be connected to external world. Encapsulation is the step involves closing the die from the interference of external contaminant and protecting from damage etc. The encapsulation can be done by mean of molding for the plastic package or glass seal the lid of the package to the hermetic ceramic package. Post mold cure or baking process is a necessary step to cross linked the plastic resin material to provide hardening effect. Owing to high temperature process, lead of package would be tarnished due to heat. The next process step is either tin plate
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or solders plate, which involves removing the oxide and plating the leads for preventing oxidation and providing good solderability connecting contact to the circuit board. The second last process step involves removing the shorting bar from the hermetic package, or trims and forms the plastic package. The last process step is an inspection step that involves removing of the non-compliance device such as lead problem, package crack etc from the from the production batch.
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03 Assembly Techniques and Packaging Figure 3.21: Generic electronics packaging assembly sequence for plastic and ceramic package
3.4.1 Wafer Preparation

Thickness of the fabricated wafer is normally around 650m. It needs to be thinned before the assembly begins. Depending on the package style that the integrated circuit to be housed, it can be thinned to approximately 400m. The thinning is necessary to reduce thermal stress due to mismatch of the coefficient of thermal expansion CTE between the silicon die and the packaging material. Again depending on the type of packaging material, the back-side of the wafer may require metallization deposition consisting of multilayer metallic elements like gold-nickel-silver Au-Ni-Ag or titanium-nickel-silver Ti-Ni-Au in order from silicon side. This helps in thermal conduction between the silicon die and the package, and provides the superior adhesion strength and electrical connection. Every integrated circuit in the wafer is probed electrically to check its functionality. The malfunction dice are marked with a drop of red ink that they can be sorted out during die attach or die bonding process. Different color inking schemes may be adopted to distinguish between commercial/industrial compliance die and military compliance die. One of the schemes is to ink the die with green color for commercial/industrial compliance die, no color is to be used for military compliance die, and red color for fail die. The probed wafer is then adhesively mounted to a tape that has been preassembled to a frame using a wafer dispenser. The frame is then mounted on the dicing machine with a diamond blade to cut the scribe line for separating the dice. The thickness of diamond blade is typically 25m thick rotating at a speed of 20,000rpm cuts the wafer from 90.0% to 100.0% saw-through allowing dicing street as narrow as 60m, which is closed to the width of scribe line of between dice. 100.0% saw-though is necessary for VLSI devices, which have large area because it reduces the chance of chipping at the edge during die separation breaking process. In the modern VLSI assembly, the 100% sawthrough dice allow automatic picking of good dice with the aid of optical visual system during die attach.
3.4.2 Die Attach

It is a process of attaching the die permanently to the paddle of lead frame or ceramic package. One of the important conditions of the die attachment process and several other processes are the requirements of high temperature and
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cooling down to room temperature. This would cause thermal stress due to the difference of coefficient of thermal expansion CTE of the silicon die and material of package. The results are crack on the die and metallization peeling off. Material that has CTE close to that of silicon crystal is preferable in package construction. Choosing the packaging materials that have CTE the same as that of silicon would be ideal reducing thermal stress to zero. In real situation, there is no such material that can provide perfect match with the silicon. However, in the industrial ceramic Al2O3 substrate and Alloy 42 (42% nickel-58% iron alloy) lead frame have been used for many years due to close TCE match for hermetic-ceramic package and plastic package. However, Alloy 42 is no longer the only choice in todays assembly. Copper alloy lead frame is preferred today for logic and microprocessor devices because copper alloy has approximately ten times the thermal conductivity of Alloy 42. It allows better heat transfer from the die to package via die attach material. 3.4.2.1 Eutectic Die Attach Figure 3.22 illustrates the fundamental aspect of a die attach. Eutectic chip die attach is metallurgically attached from the die to substrate material typically made from Alloy 42 or attached to a ceramic substrate (90-99.5% Al2O3). Metallization is often required on the back of the chip so that it is wettable by die attach perform. The perform is a thin sheet of thickness less than 0.05m consisting of solder-bonding alloy such as 98% gold-2% silicon. The paddle and lead of the ceramic package is usually plated with gold, while the paddle and lead of the alloy 42 lead frame or copper alloys lead frame is plated with silver.
Figure 3.22: The basic structure of a silicon device die attach with a metal preform
During the die attach, the preform is placed on the paddle heated to about 3700C. Mechanical scrubbing is done so that the preform melts and reacts with silicon to form an Au-Si composition bond between the backside of the die and the substrate of the ceramic. The bonding is considered complete when the AuSi composition structure becomes rich in silicon.
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3.4.2.2 Epoxy Die Attach Silver filled epoxy adhesive is the choice of polymer based material for die attach. The silver filler usually would flake that makes epoxy electrically conductive and thermally conductive to allow good thermal path between die and the rest of the package. In VLSI assembly, epoxy is fed onto the substrate material through a multi-nozzle or single nozzle dispenser to ensure the required bond line thickness is created avoiding void. The back side of the die often does not require metallization because epoxy provides better adhesion with bare silicon or silicon dioxide. The process time of die attach usually is 1 to 2 seconds at room temperature. The epoxy is thermosetting polymers, after the die attach, it must be cured at elevated temperature to complete the die bond. The cure conditions range from 1250C to 1750C and require 1 to 2 hours.
3.4.3 Wire Bonding

Wire bonding is the most common method for connecting the bond pads on the die to the leads of the package. Aluminum or gold wires are usually the choice because they bond well to the bond pads on the die and to the metallized part of the package forming Au-Al and Al-Ag metallurgical diffused materials. Gold or aluminum wire of diameter 25 to 30m is balled and wedge bonded by thermosonic or thermocompression, where the ball is bonded to the bond pad made of aluminum and wedge-bonded at the lead plated with either gold or silver. The temperature of wire bonding for thermosonic ranges from 1500C to 2500C, while for thermocompression process, the temperature ranges from 3000C to 3500C. The metallurgical diffusion primary follows equation X2 = Dt
D = D 0 exp( Q / RT )
(3.12) (3.13)
where X is the diffusion thickness, D is the diffusion constant, t is the storage time, D0 is the frequency factor, Q is the activation energy, R is the gas constant, and T is the storage absolute temperature. Gold and aluminum form a variety of inter-metallic with Au-Al first formed and gradually change to Au-Al4 that will degrade the bond strength.
- 28 -
Following equation (3.12) and (3.13), Au-Al inter-metallic growth would be severed at elevated temperature especially the temperature of molding and hermetic glass seal. Thus, aluminum-aluminum wiring bonding at bond pad is preferred for high reliable products. Besides, using gold and aluminum wires to interconnect bond pads of the die to lead of package, copper bond wire is also used in todays modern VLSI assembly due to a few obvious reasons. They are cost, electrical and thermal conductivity, less inter-metallic growths, and better reliability of bond at elevated temperature. Copper costs 90% less than gold. It is obvious in terms of cost of assembly. It costs less. Copper wire has electrical resistivity of 0.017x10-4-cm, which is about 30% better than the resistivity of gold, which is 0.022x10-4-cm. The low electrical resistivity of copper results in better electrical performance in particular for bonding high current device. Copper has thermal conductivity of 395m-1K-1, which 25% better than the thermal conductivity of gold, which is 316Wm-1K-1. Thus, copper wire dissipates heat within the package faster than gold wire. Thus, it minimizes the thermal stress. Copper has a lower tendency to form inter-metallic compound with aluminum. Unlike gold, it forms inter-metallic compound with aluminum especially at elevated temperature due to inter-diffusivity of gold and aluminum (bond pad). It can create voids at the bond interface that would weaken the bond and can lead to bond lifting as well as other wire bond problems.
3.4.4 Molding/Glass Seal

Upon completion of wire bonding, the next operation is either molding or glass seal process, which depending on the package style used. Glass seal refractory technology relies on glass sealing a lead between two pressed ceramics as illustrated in Fig. 3.23 using low temperature glass. The glass used for glass sealing is PbO-ZnO-B2O3 type. Sealing is usually done at temperature above 4000C in an oxidizing ambient to avoid deoxidizing the metallic components of the glass that would degrade the electrical insulation. For VLSI device, sealing at temperature greater than 4000C would cause additional thermal diffusion at the junction of transistor that would shift slightly the electrical characteristics of the die. Thus, choosing glass-sealing technology for sealing must be carefully.
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Figure 3.23: Structure of ceramic dual inline package (cerdip) showing the base, the lead frame and a lid with sealing glass
Plastic encapsulation involves a number of techniques. For an example, in globtop-coating, the post wire bonded die is coated with liquid plastic resin and the plastic are cured for the cross liking. In VLSI plastic packaging, a pre-molding technique is sometimes used. This technology is the plastic equivalent of the refractory ceramic cavity package. The package is molded together with a lead frame forming a plastic body and cavity, whereby the die is attached and bond pads to lead are wire bonded. The post molding technology is a transfer molding method using thermosetting epoxy resins to mold around the frame-die assembly to form package body. The molding process has to be controlled carefully because this process is relatively harsh that the die and bond wire are exposed to viscous molding material that may cause wire sweeping or lifted wire. The molding material that is epoxy resin is made by condensing epichlorohydrin with bisphenol-A to produce a material called Epoxy-A. An excess of epichlorohydrin was used to leave epoxy groups on each end of low molecular weight polymer. Today NOVOLAC epoxy is general preferred due to its higher functionality that makes heat resist. The molding compound is usually pre-heated and transferred into pots of large multi-cavity mold. After it enters the pot, the molding compound melts under pressure and heat, flows to fill the mold cavities containing frame strips with their attached dice. For molding of VLSI die, which has large area, longer bond wire, the multi-pot molding as shown in Fig. 3.24 is preferred aiming to reduce damage of wire due to viscosity of the mold compound and incomplete mold due to partial cross linking.
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Figure 3.34: Schematics of a multi-pot transfer-mold system showing small mold compound tablets with each large enough to fill a few cavities containing plastic strips
3.4.5 Post Mold Cure/Leak Check

For plastic packaged device, post mold cure or baking process is a necessary step to cross linked the plastic resin material to provide hardening effect. The curing is normally done in an oven set at temperature 1500C for three hours of curing time. As for the hermetic package, cure is not necessary for the package. For ceramic packaged device, leak test is usually done to check if there is any glass seal problem or micro-crack of the ceramic package. The leak tests are divided into gross leak and fine leak tests. The gross leak test is easy. It is done by immersing the ceramic package into water like the way we check the leak of a car wheel. Fine leakage is done by placing the ceramic devices in the pressure compressed chamber containing radioactive source for 1 to 2 hours. The devices are then checked for fine leak with a particle counter. If the counter shows count result, it means that there is fine leak due to micro-crack whereby it cannot be visually detected by naked eyes.
3.4.6 Solder Dip/Tin Plate

Owing to high temperature process, lead of package would be tarnished due to heat. Thus, it is necessary to remove the oxide before either solder dip or tin plate is done depending on package type. The leads of plastic package are
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normally solder dipped, while the leads of hermetic package is normally tin plated or solder plated. Solder dip or tin plate is necessary to protect the base metal of the package from oxidation in order to preserve its solderability. For plastic device, upon removing the oxide and extra mold fresh, the short between the tips of the lead between adjacent packages is removed as shown in Fig. 3.25 and the package is formed to the desire shape as shown in Fig. 3.26 for plastic dual in-line DIP package. The device strips are dipped with solder flux and then into solder bath so that solder will cover the non-oxidized bare-leads of the plastic device. As for the ceramic package, it is normally tin plated or solder plated via electrolysis. It is normal electrolysis process, whereby the hermetic devices are hung in a bracket at the negative electrode of the plating bath filled with electrolyte.
Figure 3.25: Molded plastic package strip showing short between tips of the lead, tight bar and guide pin hole
Figure 3.26: The formed molded plastic dip package strip shows that tight bar has not been removed
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3.4.7 Trim/Form
One already knows that generally the device is assembled either in plastic package style or hermetic package style. The leads of the device are shorted with a tight bar with the aims to prevent lead bending and also to protect the die from damage due to electrostatic discharge ESD so that every lead is at same potential with no potential difference for electron discharge that would damage the die. The short between the tips of the leads is trimmed off using puncher. The device is then formed according to the package style such the dual inline package DIP as shown in Fig. 3.26. Take for an example, the lead of the package is formed into gull-wing style for single outline package SOP. For plastic package, trim and form are performed before solder dip process. As for the hermetic package, form is normally not necessary, while trim is done after tin plating or solder plating process to remove the shorting bar connecting the tips of all leads.
3.4.8 Inspection
The tight bar of the plastic device is removed to singulate device. Inspection is done to sort out non-conformance device such as lead defect, package crack, package chip, insufficient solder coverage etc. before loaded into tube. The tube or tray loaded devices is then transferred to test operation for initial and final tests.
Exercises
3.1. Why is it necessary to measure the physical parameter of a fabricated integrated circuit? Calculate the current transfer distance (li) if the contact resistivity is 2.0x10-7cm2 and the resistivity of silicon is 100/ . If the physical contact area of the n+ diffusion region is 1.0mx0.5m, using the result of question 9.2, calculate the contact resistance. Using a cross-bridge Kelvin structure with a 1.0m x 1.0m contact, the current is found to be 10.0A through the contact and the voltage difference across the contact is 320V, find the contact resistivity of this contact.
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3.2.
3.3.
3.4.
3.5.
State the reason necessary to have coefficient of thermal expansion matching materials for package and silicon die. Why aluminum wire bonding is preferred than gold wire bonding? If the Au-Al bond diffusion thickness is increased by 1.0m during 1500C time-temperature storage operation, calculate the period of time. You may use D0 = 2.2x10-4m2/s, Q = 134kJ/mol and R= 8.31J/mol-K to help you in the calculation. For VLSI device plastic molding, state the reason why multi-pot molding is necessary. State the reasons why the leads of the package are normally shorted together in a assembly operation.
3.6. 3.7.
3.8.
3.9.
3.10. Calculate the number of gates that can be included on a logic-array chip which is to be assembled in 120 I/O package assuming that k = 4.5 and = 0.5. 3.11. An integrated circuit has 800 gates, its nominal propagation delay for a transistor is 5.0x10-15s, its junction to ambient maximum temperature difference is 550C, and junction to ambient thermal resistance is 1000C/W. Calculate the activation energy of each gate of this circuit. 3.12. State the reason why it is necessary to have heat sink for conducting away extra heat from the package of integrated circuit?
Answers of Exercises
3.1. It is necessary because the manufacturer would like to integrated circuit is fabricated in accordance to the specifications. The current transfer length (li) is equal to li =
C 2.0 x10 7 = = 0.447m. S 100
3.2. 3.3.
The area of current flow is 0.447mx0.5m = 2.235x10-9cm2. Given that the contact resistivity C = 2.0x10-7cm2, the contact resistance RC is 2.0x10-7cm2/2.235x10-9cm2 = 89.48.
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03 Assembly Techniques and Packaging

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UNIVERSITI TUNKU ABDUL RAHMAN

Assembly Techniques and Packaging

Dr. Lim Soo King 05/15/2012

Chapter 3 Assembly Techniques and Packaging .............................4

3.3 Packaging Level Integration ................................................................... 16

3.4 Assembly Techniques and Processes ...................................................... 24

Figure 3.25: Figure 3.26:

Chapter 3 Assembly Techniques and Packaging _____________________________________________

3.1 Assembly Technologies