1

ANAND INSTITUTE OF HIGHER TECHNOLOGY, KAZHIPATTUR. DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING CS2202: DIGITAL PRINCIPLES AND SYSTEM DESIGN Staff Name : V.A.Amala Shiny,N.Sophia Sindhuja, S.Shoba Branch/Sec: Common to CSE & IT/ A&B Date: 06.07.11 Year/Semester: II/ III PART-A 1. Code Conversion [Dec 2011; Nov 2010(R08), Nov 2010, Apr 2010(R08), Apr 2008, May 2006, Nov 2006, May 2006]

i). Perform the following code conversions: (1010 .10 )16 (?)2 (?)8 (?)10
(1010.10)16 = ( )10

(1010.10)16 = ( 4112.0625)10 (1010.10)16 = ( )2

AIHT

DEPARTMENT OF ECE

DPSD

(4112)10= (1000000010000)2 (0.0625)10 = ( )2 0.0625 x 2= 0.1250 0.125 x 2 = 0.250 0.25 x 2 = 0.50 0.5 x 2= 1 (0.0625)10 = ( 0.0001)2 (4112.0625)10 = (1000000010000.0001)2 3). Octal equivalent (1000000010000.0001)2= (10020.01)8

ii) Find the octal equivalent of hexadecimal number AB.CD (AB.CD)H = 10161+11160+1216-1+1316-2 = 160+11+0.75+0.05 =(171.8)10

[Nov 2010(R08)]

0.88=6.4 0.48=3.2 0.28=1.6 (171.8)10= (253.631)8 iii)Convert (0.513)10 to octal 0.5138= 4.104 0.1048= 0.832 [Nov 2010]

AIHT

DEPARTMENT OF ECE

DPSD

3
0.8328= 6.656 0.6568= 5.248 (0.513)10= (0.4065)8 iv) Convert the (153.513)10 to Octal. [Apr 2010(R08)]

0.513 x 8 = 4.104 0.104 x 8 = 0.832 0.832 x 8 = 6.656 Ans: 231.406 v) Convert the following number from one base to other (65.342)8=( )7
= (6 81 ) + (5 8 0 ) + (3 8 1 ) + (4 8 2 ) + (2 8 3 ) = 48 + 5 + 0.375 + 0.0625 + 0.0039 = (53.44)10

[Apr 2008]

0.44 7 = 3.08 0.08 7 = 0.56 0.56 7 = 3.92

Ans=(104.303)7 vi) Convert (2C9)16 to decimal.

= (2 16 2 ) + (12 161 ) + (9 16 0 ) = 512 +192 + 9 = (713)10

[May 2006]

vii) Determine the decimal value of the fractional binary number 0.1011
= (1 2 ) + (0 2
1 2

[Nov 2006]

) + (1 2

) + (1 2

= 0.5 + 0 + 0.125 + 0.0625 = (0.6875)10

viii) Convert (1010111010)2 to Hexadecimal. =(0010 1011 1010)2 =(0010 1011 1010)2 = (2BA)16 2. Simplification of Boolean function [Apr 2010(R08), Nov 2008, Nov 2008, Apr 2008, Nov 2007, May 2007, Nov 2011(R10)] ] i) (a) (x + y)(x + y)

[May 2006]

[Apr 2010(R08)] = x.x + x.y +xy + y.y = x + x.y+xy = x(1+y+y) = x(1+1) =x xy +xz+yz (since x.x=x & y.y = 0)

(b)

AIHT

DEPARTMENT OF ECE

DPSD

4
= xy + xz + (x+x)yz = xy + xz + xyz + xyz = xy(1+z) + xz(1+y) = xy + xz ii) Simplify (x+y)(x+y) to a minimum number of literals =xx+xy+xy+yy = x+xy+xy since A.A=A, AA=0 =x+x(y+y) =x+x since A+A=1 =x iii) Find the minterm of xy+yz+xyz. =xy(z+z)+yz(x+x)+xyz =xyz+xyz+xyz+xyz+xyz =xyz+xyz+xyz+xyz iv) Convert the following function into sum of product term (AB+C)(B+CD) =AB+ABCD+BC =AB(C+C)(D+D)+ABCD+BC(A+A)(D+D) =ABC(D+D)+ABC(D+D)+ ABCD+BCA(D+D)+BCA(D+D) =ABCD+ABCD+ABCD+ABCD+ABCD+ABCD+ABCD v) Find the complements for the following functions a. F1=xy+xy b. F2=(xy+yz+xz)x a. F1 =(xy+xy)= (xy).(xy)= (x+y).(x+y) b. F2=((xy+yz+xz)x)= (xy+xyz+xz)= (xy).(xyz).(xz) = (x+y).(x+y+z).(x+z) vi) Simplify the following Boolean function: a) x (x+y) b)xy+xz+yz a) x(x+y)= xx+xy= 0+xy= xy b) xy+xz+yz = xy+xz+yz(x+x)=xy+xz+xyz+xyz = xy(1+z)+xz(1+y)= xy+xz vi) Simplify the expression ((AB +ABC)+A(B+AB)) . = ((A(B+BC))+A(B+A)) =((A(B+C))+AB+A) =((AB)+(AC)+AB+A) =((A+B).(A+C)+A) =((A+BC)+A) =(1+BC) = =0. 3. Binary Arithmetic [Apr 2011(R08);Apr 2010, Nov 2009(R08), Nov 2009(R08), Nov 2008, May 2007] [May 2007] [Nov 2007]

[Nov 2008]

[Nov 2008]

[Apr 2008]

[Nov 2011(R10)]

AIHT

DEPARTMENT OF ECE

DPSD

5
i) Represent the decimal numbers 200 and 200 using 2's complement binary form. 2s complement of 200 = 0011001000 2s complement of -200 = 1100110111+1 = 1100111000 ii) Perform subtraction by twos complement method : 100-110000. 1s complement of 110000 = 001111 2s complement of 110000 = 010000 100 010000 010100 + [Nov 2009(R08)] [Apr 2011(R08)]

[Apr 2010]

Ans: 010100 iii) Perform subtraction using 1s complement (11010) 2 (10000)2. 11010 1s complement of 10000 01111 101001 Since carry present add the carry to 01001 Ans: 01010 iv) Perform 9s and 10s complement subtraction between 18 and -24. 10s complement subtraction 18 76 94 10s complement of 94 is(-6) 9s complement of 93 is(-6) 9s complement subtraction

[Nov 2009(R08)] 18 75 93

v) What is the largest binary number that can be expressed with 12 bits? What is the equivalent decimal and hexadecimal? [Nov 2008] (1111 1111 1111)2 =(4095)10 =(FFF)16 vi) How many bits are needed to represent decimal values ranging from 0 to 12,500? 15 bits(110000110110100) 4. Signed Binary Numbers [May 2007] [Dec 2011]

State the different ways for representing the signed binary numbers. There are three different ways to represent the signed numbers. For example a signed magnitude, -9 is represented as Signed magnitude representation : 10001001 Signed -1s complement representation : 1111011 Signed -1s complement representation : 11110111

AIHT

DEPARTMENT OF ECE

DPSD

6 In signed magnitude,-9 is obtained from +9 by changing the sign bit in the leftmost position from 0 to 1.In signed -1s complement, -9 is obtained by complementing all the bits of +9, including the sign bit. The signed -2s complement representation of -9 is obtained by taking the 2s complement of the positive number including the sign bit.
5.Boolean Theorems [Nov 2010(R08), Apr 2005; Nov 2010, Nov 2009,Nov 2006 ] i) State and prove consensus theorem [Nov 2010(R08), Apr 2005] The consensus theorem can be stated as follows: XY + XZ + YZ = XY + XZ The consensus theorem can be used to eliminate redundant terms from Boolean expressions. Proof XY + XZ + YZ = XY + XZ + (X+X)YZ = XY + XZ + XYZ + XYZ = XY(1+Z) + XZ(1+Y) = XY + XZ ii) State and prove De-Morgans law. The complement of sum equals the product of the complements. NOT (P OR Q) = (NOT P) AND (NOT Q) Proof: [Nov 2010, Nov 2009,Nov 2006]

The complement of a product equals the sum of the complements. NOT (P AND Q) = (NOT P) OR (NOT Q) Proof;

6. Write the truth tables of logical AND and XOR gates

[Apr 2011(R08)]

7. State the Duality principles?

[Apr 2010]

AIHT

DEPARTMENT OF ECE

DPSD

7
Duality principle states that every algebraic expression deducible from the postulates of Boolean algebra remains valid if the operators and identity elements are interchanged. According to Duality principles OR and AND operators are interchanged and replace 1s by 0s and 0s by 1s. 8. Draw the logic diagram for the Boolean expression ((A+B)C)D using NAND gates. ((A+B)C)D = ((A+B).C)D = (A.B+C)D [Nov 2009(R08)]

9. Name the various types of number systems with their bases and give an example for each. [Nov 2009] Decimal-Base10 Binary-base 2 Octal-base 8 Hexadecimal base 16 123 1010 47 AD

10. What are the advantages of tri-state gates? [Nov 2009] The whole concept of the third state (Hi-Z) is to effectively remove the device's influence from the rest of the circuit. If more than one device is electrically connected, putting an output into the Hi-Z state is often used to prevent short circuits, or one device driving high (logical 1) against another device driving low (logical 0). Three-state buffers can also be used to implement efficient multiplexers, especially those with large numbers of inputs. In particular, they are essential to the operation of a shared electronic bus. 11. What are minterms? [Apr 2008] A product term containing all the K variables of the function in either complemented or uncomplemented form is called a Minterm. Minterms are also called standard product. 12. What are error detecting codes? [Nov 2007] Error detecting codes are used for tracing out the errors in the code words. Most commonly used error detecting codes are parity check, check sums. 13. What is the advantage of gray codes over the binary number sequence? [May 2007] The advantage of the Gray code over binary number is that only one bit in the code group changes when going from one number to the next. 14 . What are the drawbacks of K-Map method? If the number of variables increases the table size increases and complex to solve. 15. What is the feature of Grey code? [Nov 2007] [May 2006]

AIHT

DEPARTMENT OF ECE

DPSD

8
In Grey code, only one bit changes when going from one step to next which means that only one bit will change each time the decimal number is incremented. Due to this the error is reduced during the transition from one number to the next. It is also called Cyclic or Reflected code. 16.Why NAND and NOR gates are called universal gates? [Nov 2006] NAND and NOR gates can be connected to perform any logic operation, so they are called Universal gate 17. Find the minimum expression of Y= (0,1,3,5,6,7,10,14,15) [Nov 2011(R10)]

Y = AC + BCD +ABD + ABCD

UNIT-II 1. Arithmetic operation of combinational logic [Apr 2011(R08), Nov 2010, Nov 2009(R08),Nov 2005; Nov 2010(R08);Apr 2010; May2007, May2006 ; Nov 2011(R10)] i). Draw the logic diagram of half adder [Apr 2011(R08), Nov 2010, Nov 2009(R08),Nov 2005]

ii) Define Look ahead carry addition [Nov 2010(R08)] Carry look ahead adder is also called Parallel adder or fast adder because it attains high speed in addition operation. A carry look-ahead adder improves speed by reducing the amount of time required to determine carry bits. iii) Obtain the Boolean functions for the outputs of half subtractor. [Apr 2010] x Y Difference Barrow 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0

AIHT

DEPARTMENT OF ECE

DPSD

Difference = xy + xy = x xor y Barrow = xy vi) What is a full adder? Full-Adder: A B C S 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1

[May2007, May2006] CO 0 0 0 1 0 1 1 1

2. Hardware Description Language [Dec 2011;Apr 2011(R08);Nov 2010; Apr 2010(R08); Nov 2007; May2007; Nov 2008] i) List the modeling techniques available in HDL There are three modeling techniques in HDL. i) Data flow model ii) Structural model iii) Behavioural model

[Dec 2011]

ii). Write the HDL description of the following circuit

[Apr 2011(R08)]

module circuit(x,y,A,B,C); input A,B,C; output x,y; wire e,y; and g1(e,A,B); not g2(y,C); or g3(x,e,y); endmodule iii). Give any two features of hardware description language(HDL) [Nov 2010] 1. HDL is used to represent and document digital systems in a form that can be read by both humans and computers. 2. The language content can be stored and retrieved easily and processed.

AIHT

DEPARTMENT OF ECE

DPSD

10
iv) What do you mean by HDL? [Apr 2010(R08)] A hardware description language is a language that describes the hardware of digital systems in a textual form. It resembles a programming language, but is specifically oriented to describing hardware structures and behavior. It can be used to represent logic diagrams, Boolean expressions and other more complex digital circuits. HDL is used to represent and document digital systems in a form that can be read by both humans and computers. v) What is logic synthesis in HDL? [Nov 2007] Logic synthesis is a process of deriving a list of components and their interconnections (called netlist) from the model of a digital system described in HDL. The gate level netlist can be used to fabricate an integrated circuit or to layout a printed circuit board vi) What are the modeling techniques available to build HDL module? i)Gate level modeling using instantiation of primitive gates and user-defined modules. ii)Data flow modeling using continous assignment statements with keyword assign. iii)Behavioral modeling using procedural assignment statements with keyword always. [May2007]

vii) What is the difference behavioral modeling and dataflow modeling? [Nov 2008] Data flow modeling uses a number of operators that act on operands to produce desired results Behavioral model represents digital circuits at a functional and algorithmic level. It is used mostly to describe sequential circuits. 3.Compare serial and parallel adder S.No 1. 2. 3. SERIAL ADDER Serial adder uses shift registers Serial adder requires only one full adder circuit and a carry flip flop Serial adder is a sequential circuit [Nov 2010(R08)] PARALLEL ADDER Parallel adders uses registers with parallel load Number of full adders in parallel adder is equal to the number of bits in the binary number Excluding the registers parallel adder is a combinational circuit

4. Distinguish between the combinational and sequential logic circuits. [Apr 2010(R08), Apr 2010, Nov 2009(R08), Nov 2007] S.No Combinational Circuits Sequential Circuits 1. Output at any time instant depends on the Output at any time instant depends on the input input present at that time instant. present at that time instant and also on the past output. 2. Faster than sequential circuit. Low speed. 3. Memory unit is not required. Memory unit like flip flops, latches are required. 4. Does not require clock pulse. Synchronous sequential circuits always require clock pulse, whereas Asynchronous sequential circuits do not require. 5. Easy to design. Design is not easy.

AIHT

DEPARTMENT OF ECE

DPSD

11

5. Parity generator. [Apr 2010, Nov 2007] i). Write the Boolean function for 3-bit even parity generator and draw the circuit. [Apr 2010] INPUT Parity Generator 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1 Output = xyz+xyz+xyz+xyz = x xor y xor z

ii) Draw the circuit diagram for 3 bit parity generator

[Nov 2007]

6. How is division operation performed using a subtractor? By repeated subtraction For example to divide 25 by 5: Binary equivalent of 25 is 11001 Binary equivalent of 5 is 101 By Subtracting 11001 101 [1] 10100 101 .[2] 01111 101 .[3] 1010 101 [4] 0101 101 .[5] 0 Hence 25 divided by 5 is obtained as 5 by repeated subtraction

[Nov 2009]

7. With block diagram show how full adder can be designed using 2 half adders and 1 gate. [Dec 2011]

AIHT

DEPARTMENT OF ECE

DPSD

12

8. Draw the full adder circuit as a collection of two half adder

Nov 2011(R10)

9. A circuit is to be designed that has one control line and three data lines. [Nov 2011(R10)] When one of the data lines has a 1 on it. No more than one data line will ever have a 1 on it. When the control line is low, the circuit will output a 0, regardless of what is on the data lines. Answer: A B C D O/P 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 0 1 1 0 AIHT DEPARTMENT OF ECE DPSD

13 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 1 0 0 0

Y = ABCD + ABCD +ABCD

UNIT-III 1. Encoder and Decoder [Nov 2010(R08),Apr 2008, May 2007; Apr 2010(R08), Apr 2010] i) Define priority encoder [Nov 2010(R08),Apr 2008, May 2007] Priority encoder is an encoder circuit that includes the priority function. The operation of the priority encoder is such that if two or more inputs are equal to 1 at the same time, the input having the highest priority will take precedence. ii) What is an encoder? List its applications. [Apr 2010(R08), Apr 2010] Encoder is a combinational logic circuit, that output lines generate the binary code corresponding to the input value. It is a digital circuit. It has 2n input lines and n output lines. Applications: 1. It is a digital circuit, can be used for code conversion 2. Used in decimal to BCD encoding 2. Multiplexer and Demultiplexer

i) Define decoder. Draw the block diagram and truth table for 2 to 4 decoder. [Dec 2011] A decoder is a combinational circuit that conveys binary information from n input lines to a maximum of 2n unique output lines.

AIHT

DEPARTMENT OF ECE

DPSD

14

ii). Determine the size and number of multiplexers required to implement a full adder. [Apr 2011(R08)] [Apr 2011(R08);Nov 2010; Apr 2010(R08); Nov 2008; Apr 2008; May 2007; May 2007; [Nov 2011(R10)] To implement a full adder two 2:1 multiplexers are required. iii). Implement the following function using suitable multiplexer F(x,y) = m(0,1) [Nov 2010]

iv) What is multiplexers? [Apr 2010(R08)] Multiplexers is a combinational circuit with many inputs but only one output. By applying control signals we can steer any inputs to the output. Multiplexers is called as data selector, because the output bit depends on the input data bit that is selected. v) Construct a 16X1 multiplexer with two 8X1 multiplexer and 2X1 multiplexer. [Nov 2008]

[Apr 2008] vi) What is a demultiplexer? Demultiplexer is a circuit that receives the information on a single line and transmits this information on one of 2n possible output lines. The selection of specific output line is controlled by the values of n selection

AIHT

DEPARTMENT OF ECE

DPSD

15
lines. vii) Mention any two applications of multiplexers. i)Data routing ii) Parallel to serial conversion iii)Operation sequencing iv)Logic function generation viii) Write the logic equation and draw the internal logic diagram for a 4 to 1 MUX? [May 2007]

[May 2007]

ix) The input frequency of a 7497 binary rate multiplier is 64 K Hz. What will its output be if the multiplier word is 1011? x) Implement a digital circuit that statistics the following : F (A, B, C) = S (0, 2, 3, 4, 7), d (A, B, C) = (1)

[Nov 2011(R10)] [Nov 2011(R10)]

Y = A + BC + BC

3. Compare a decoder with a demultiplexer. DECODER A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines. There are no selection lines but the instantaneous bit combination of the incoming signal decides which output line will activate

[Apr 2010, Nov 2009(R08)] DEMULTIPLEXER A demultiplexer is a logic circuit with one input and many outputs

There are n selector lines in demux which decides which output to be activated momentarily

AIHT

DEPARTMENT OF ECE

DPSD

16
instantaneously

Decoder with enable input can function as a demultiplexer

Demultiplexer IC can behave like a decoder

4. Memory and programmable logic(PROM, PAL, PLA) [Apr 2011(R08);Nov 2010; Nov 2009(R08); Apr 2008;Nov 2006; Nov 2006] i) Determine the number of address lines required for 512 bytes of memory and for a 2KB memory. [Apr 2011(R08)] 512 Bytes = 2^9 Hence number of address lines required for 512 bytes of memory = 9 2KB = 2^11 Hence number of address lines required for 2KB of memory = 11 ii). State the difference between PAL and PLA S.No 1. 2. 3. PAL Programmable AND and fixed OR array Cheaper Simple to use [Nov 2010][Dec 2011] PLA Programmable AND and programmable OR array Costlier Complex than PAL

iii). What is programmable logic array? How does it differ from ROM? [Nov 2009(R08)] In some cases the number of dont care conditions is excessive, it is more economical to use a second type of LSI component called a PLA. In PLA both AND and OR arrays can be programmed. A PLA is similar to a ROM in concept; however it does not provide full decoding of the variables and does not generates all the minterms as in the ROM. iv) what is the maximum range of a memory that can be accessed using 10 address lines? [Apr 2008] =210 = 1024 v). What is RAM? [Nov 2006] RAM is a memory in which each memory location can be addressed directly at random without first addressing other memory location occurring earlier. vi). What are the types of ROM. 1. Masked ROM. 2. Programmable Read only Memory 3. Erasable Programmable Read only memory. 4. Electrically Erasable Programmable Read only Memory. 5. HDL for Combinational circuits [Nov 2006]

AIHT

DEPARTMENT OF ECE

DPSD

17
[Nov 2010(R08); Nov2009; Nov 2007] i). Write a dataflow description of a 2-to-1 line mux using a conditional operator. module mux(A,B,Sel,Out); input A,B,Sel; output Out; assign Out = Sel? A: B; endmodule ii).What is HDL? [Nov 2010(R08)]

[Nov2009]

A hardware description language is a language that describes the hardware of digital systems in a textual form. It resembles a programming language, but is specifically oriented to describing hardware structures and behavior. iii). What is gate level modeling? [Nov 2007] In this type of representation a circuit is specified by its logic gates and their interconnection. It provides a textual description of a schematic diagram. 6. Draw the logic diagram of 4bit even parity checker [Nov 2008]

7. When an overflow condition will encounter in an accumulator register? [Nov 2007] The number of bits that hold the number is finite that contains n+1 bits cannot be accommodated. UNIT-IV 1. Latches and Flip Flops [Dec[2011];Apr 2011(R08); Apr 2011(R08); Nov 2010; Apr 2010; Apr 2010(R08); Apr 2010(R08); Nov 2009; Nov 2008; Apr 2008; Nov 2007; May 2007, Nov 2005; May 2007; Nov 2006; May2006]

i). Write down the characteristic equation for JK and T flip flops. Characteristic equation for JK flipflop D= JQ +KQ Characteristic equation for T flipflop D= T+Q = TQ+TQ
i). Write the state transition table of J-K flip-flop. [Apr 2011(R08)]

AIHT

DEPARTMENT OF ECE

DPSD

18

ii) Express the next state characteristics of D and SR flip- flops.

[Apr 2011(R08)]

iii). Draw the logic diagram of SR latch implemented using NAND gates

[Nov 2010]

iv). What is the idea behind master slave JK Flip Flop?

[Apr 2010]

To begin with, the master is positive edge triggered and the slave is negative edge triggered. The master is set according to J and K while the clock is high, the content of master are then shifted into the slave while the clock goes low. v) Differentiate Flip-Flops from Latches? [Apr 2010(R08)]

The main difference between latches and flip-flops is in the method used for changing their state. The flip-flops samples its inputs and changes its outputs only at time determined by clock signal. The latch checks all of its inputs accordingly at any time independent of a clock signal.

vi). Draw the excitation table and state diagram for JK and SR flip-flop. EXCITATION TABLE

[Apr 2010(R08)]

AIHT

DEPARTMENT OF ECE

DPSD

19

STATE DIAGRAM JK Flip-Flop

SR Flip-Flop

vii). What is Triggering? What is the need for a trigger in a flip-flop? [Nov 2009] The state of flip-flop is switched by a momentary change in the input signal. This momentary change is called a trigger. viii). Write down the characteristic table of JK flip-flop Qn J K Qn+1 0 0 0 0 [Nov 2008]

AIHT

DEPARTMENT OF ECE

DPSD

20
0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 1 1 0 1 0 [Apr 2008]

ix). Draw the logic diagram for T Flip flop

x). Draw the logic diagram for D-type latch.

[Nov 2007]

xi). How can a D flip flop be converted in to a T flip flop? The excitation table for this conversion is given by Input Present state T Q(t) 0 0 0 1 1 0 1 1 __ ___ D= T Q(t) +T Q(t) Next state Q(t+1) 0 1 1 0

[May 2007, Nov 2005] Flip flop input D 0 1 1 0

xii). What is meant by the term edge triggered? [May 2007] The momentary change is called as the trigger and the transition it causes is said to trigger the flip flop. A clock pulse goes through two transition from 0 to 1 and the return from 1 to 0. Edge triggering occurs at the edge of each clock pulse. xiii). How does a J-K flip flop differ from an S-R flip-flop in its basic operation. [Nov 2006] J-K flip-flopis a improved or modified form of S-R flip-flop because it has the advantage that it cannot be forced in to an intermediate state by applying both input high.There fore it is the most versatile and widely used flip-flop and it is the ideal memory element to be employed when it s required to count. xiv). What is the memory elements used in a clocked sequential circuit? J-K flip-flop S-R flip-flop D flip-flop T flip-flop xv) Given a 8 bit data word 01011011, generate the 13 bit composite word for the Hamming code that corrects single errors and detects double errors. 2. Write the HDL code for D flip flop using behavioral model [May2006]

[Nov 2011(R10)]

[Nov 2010]

AIHT

DEPARTMENT OF ECE

DPSD

21
module D_FF(Q, D,CLK); output Q; input D, CLK; reg Q; always@ (posedge CLK) Q= D; Endmodule 3. Differentiate Moore and Mealy circuit models S.No Moore model 1. Output depends only on present state and not on input 2. More hardware required 3. [Nov 2010(R08), Nov 2008]] Mealy model Output is derived from present state as well as from input Less hardware is required to solve any problem

4. Shift Registers i). What are the applications of shift registers [Nov 2010(R08), Nov 2009; Nov 2008] [Nov 2010(R08), Nov 2009]

1. Shift registers are used to interface digital systems situated remotely from each other 2. It can be used to count the number of pulses entering into a system as ring counter or switched tail counter 3. It can also generate prescribed sequence repetitively or detect a particular sequence from data input 4. It can also help in reduction of hardware by converting parallel data feed to serial one. 5. Rotation of data ,multiplication and division , also these are useful for serial transmission of data. ii). With 16-bit shift register, how many timing signals can be generated? 216 timing signals can be generated [Nov 2008]

5. Counters

[Dec 2011; Apr 2011(R08); Apr 2008; May 2007; Nov 2006; Nov 2011(R10)] i). How many flip flops are required for designing synchronous MOD60 counter? [Dec 2011]

ii) Draw the timing diagram showing the output of a 2 stage synchronous counter with respect to its clock signal. [Apr 2011(R08)]

AIHT

DEPARTMENT OF ECE

DPSD

22

iii). What is modulo-N counter? Counter which counts upto N states is called modulo N counter. iv). How many states are there in a 3-bit ring counter? What are they? There are 6 states in a three bit ring counter they are 000, 001, 010, 100, 101, 110

[Apr 2008]

[May 2007]

v). Define Synchronous counter. [Nov 2006] In this type there is no connection between output of first flip-flop and clock input of the next.All the flip-flops are clocked Simultaneously. vi) Draw a 4- bit binary synchronous counter with D flip flops

[Nov 2011(R10)]

UNIT-V 1. Races [Nov 2010,Nov 2006; Nov 2010(R08); Apr 2010(R08); Apr 2010; Apr 2010; Nov 2009(R08),May 2005; Nov 2009; Nov 2011(R10)] i).What are cycles and races? [Nov 2010,Nov 2006] Races exist in asynchronous sequential circuit when two or more binary state variables change during a state transition. Races can be avoided by directing the circuit through intermediate unstable states with unique state variable change when a circuit goes through a unique sequence of unstable states, it is said to have a cycle. ii). What is meant by critical race [Nov 2010(R08)] Consider an example, if state variables must change from 00 to 11 the difference in delays may cause the first variable to change faster than the second. which result state changes its sequence from 00 to 10 and then 10 to 11. If second variable changes faster than first then 00 to 01 and then to 11. If the final stable state that the circuit reaches does not depend on the order in which the state variables change, the race is called Critical race. iii). What is race conditions? [Apr 2010(R08)]

A condition occurring in a asynchronous sequential circuit due to different path delays when transition take place requiring more than one state to change simultaneously is called race condition. iv). Is it essential to have race free assignment? Justify. [Apr 2010]

Yes, it is essential because if state assignment is not proper it leads to critical race. For example, if state variables must change from 00 to 11, the difference in delay may cause the first variable to change faster than the second, which result state changes its sequence from 00 to 10 and then 10 to 11. If second variable changes

AIHT

DEPARTMENT OF ECE

DPSD

23
faster than first then 00 to 01 and then to 11. If it is possible to end up in two or more different stable states depending on the order in which the state variable change, then it is critical race. v). Does race condition exist in synchronous or asynchronous sequential circuit? Why? [Apr 2010] Race condition exists in asynchronous sequential circuits. For asynchronous circuit, several state changes may occur in response to a single input change thereby resulting in race condition. vi). What is race around condition? [Nov 2009(R08),May 2005] In the JK latch, the output is feedback to the input, and therefore changes in the output results change in the input. Due to this in the positive half of the clock pulse if J and K are both high then output toggles continuously. This condition is known as race around condition.

vii) What are Race free assignment? [Nov 2009] Race free assignment of binary variables to each stable state is necessary to prevent critical races. Hence in order to ensure that a transition table has no critical races, it is necessary to test each possible transition between two stable states and verify that the binary state variables change one at a time. To simplify above case: Three row flow table, Four row flow table and multiple row methods are used.

vii) Find a critical race free state assignment for the reduced flow table shown.

[ Nov 2011(R10)]

2. What is an implication table? [Nov 2010] The implication table is a chart that consists of squares, one for every possible pair of states that provide spaces for listing any possible implied states. Using implication table it is possible to determine all pairs of equivalent states.

3. Hazards [Apr 2011(R08); Nov 2010(R08); Apr 2010(R08); Nov 2009; Apr 2008; May 2007; May 2007; Nov 2011(R10)] i) Define static and dynamic hazards? [Apr 2011(R08)] Static Hazard: It is of two types static 1 hazards and static 0 hazards. Static 0 hazards causes the output to change momentarily to 1 when it should remain 0. Static 1 hazard causes the output to change to 0 when it should remain 1.

AIHT

DEPARTMENT OF ECE

DPSD

24
Dynamic Hazard: Dyanmic hazard causes the output to change three or more times when it should change from 1 to 0 or from 0 to 1. ii). What are the types of hazards? [Nov 2010(R08)] 1. Static 1 hazards 2. Static 0 hazards 3. Dynamic hazards 4. Essential hazards iii). What happens when a hazard happens in a logic circuit? [Apr 2010(R08)]

A logic circuit may malfunction because of occurrence of hazard condition in its combination part and unequal delays along two or more feedback paths that originate from the same input variable change. iv).What is a hazard free networks? Free of temporary false-output value v). What is a hazard in combinational circuits? [Apr 2008] Hazard is a unwanted transient i.e. spike or glitch that occurs due to unequal path or unequal propagation delays through a combinational circuit. vi). What is a hazard in combinational circuits? [May 2007] Hazards occur in combinational circuits, where they may cause a temporary false- output value. vii). What are hazards? [May 2007] A hazard is a condition where a single variable change produces a momentary output change when no output change should occur. Hazards are unwanted switching transients that may appear at the circuit because different paths exhibit different propagation delay. 4.What is meant by lockout condition? . [Nov 2009(R08)] [Nov 2009]

In a counter if the next state of some unused state is again an unused state and if by chance the counter happens to find itself in the unused states and never arrived at a used state then the counter is said to be in the lockout condition. 5.What are the steps for design of asynchronous sequential circuit? . 1. obtain a primitive flow table from the given design specifications. 2. Reduce the flow table by merging rows in the primitive flow table. 3. Obtain transition table by assigning binary state variables to each row of the reduced flow table. 4. Assign output values to the dashes associated with the unstable states to obtain the output maps. 5. Simplify the Boolean functions of the excitation and output variables and draw the logic diagram. 6.What are the advantages of debounce circuit? [Nov 2008] The debounce circuit is one that removes the series of pulses that result from a contact bounce and produces a single smooth transition of binary signal from 0 to 1 or from 1 to 0. 7. What are the assumptions made for fundamental mode circuit? [Apr 2008] [Nov 2009(R08)]

AIHT

DEPARTMENT OF ECE

DPSD

25
i) The output variables change only when the circuit is stable ii) Only one input variable can change at a given time iii) Inputs are levels and not pulses. 8. What are the assumptions made for pulse mode circuit? (i) The input variables change only when the circuit is stable. (ii) The width of the pulses is long enough for the circuit to respond to the input 9. What is an Asynchronous sequential circuit. In this type of counter flip-flops are connected in such a way that output of 1st flip-flop drives the clock for the next flip-flop. flip flop .All the flip-flops are Not clocked simultaneously. 10. Draw a circuit that has no static hazards and implement the boolean function F (A, B, C, D) = S (0,2,6, 7, 8, 10, 12) [May2007, Nov 2007]

[May 2006]

[Nov 2011(R10)]

Y = BD + ACD +ABC + ACD PART-B UNIT-1 1. Karnaugh Map and Tabulation Method (Quine McCluskey method) [Dec 2011;Nov 2010; Nov 2010(R08), Nov 2009(R08); Apr 2010(R08);Apr 2010; Apr 2010; Nov 2009; Apr 2008; Apr 2008; Nov 2007; Nov 2007; May 2007; May 2007; Nov 2011(R10) ]

(i) Simplify the following Boolean function F using Karnaugh map method: (i) F(A, B, C, D)= (1,4,5,6,12,14,15) (4) (ii) F(A, B, C, D) = (0,1,2,4,5,7,11,15) (4) (iii) F(A, B, C, D) = (2,3,10,11,12,13,14,15) (4) (iv) F(A, B, C, D) = (0,2,4,5,6,7,8,10,13,15) (4) (ii) simplify the following Boolean expressions to a minimum number of literals: (i) AC + ABC + AC (2)

[Dec 2011]

[Dec 2011]

AIHT

DEPARTMENT OF ECE

DPSD

26 (ii) XYZ + XY + XY Z (2) (iii) XY + YZ + XY Z (2) (iv) A B + ABD + AB D + ACD + ABC (5) (v) BD + BC D + A BCD (5)
iii) a) Simplify the following function using Karnaugh map F(w,x,y,z) = (0,1,2,4,5,6,8,9,12,13,14) b) Simplify the following function using tabulation method F = (0,1,2,8,10,11,14,15) iv) Simplify the following Boolean expression using Quine McCluskey method . [Nov 2010]

[Nov 2010(R08), Nov 2009(R08)] F=m(0,9,15,24,29,30)+d(8,11,31) v). Determine the prime implicants of the Boolean function by using the tabulation method F(w,x,y,z) = (1,4,6,7,8,9,10,11,15) vi). Simplify the following using K map and implement with 2level NAND gate circuit F(a,b,c,d)= ab + abd + abd + acd + abc vii). a) Simplify the following Boolean function by means of tabulation method P(a,b,c,d,e,f) = (6,9,13,18,19,25,27,29,41,45,57,61) b) Simplify xy + yz + xz to a minimum number of literals viii) Simplify the following expression y=m1+m3+m4+m5+m8+m9+m10+m11+m12+14 using [Apr 2010] 1) Karnaugh map 2) Quine McCluskey method ix) Using the tabulation method simplify the Boolean function F(w,x,y,z)= (2,3,4,6,7,11,12,13,14) which has the dont care conditions d(1,5,15). x) Using tabulation method simplyfy the boolean function [Apr 2008] [Nov 2009] [Apr 2010(R08)] [Apr 2010]

F(w,x,y,z)=(0,1,8,11,12,15,20,21,22,24,29,31) which has the dont care conditions d(9,18,30). xi) a)Simplyfy the boolean function using k-map method: F(w,x,y,z)=(0,2,6,8,10,12,14) [Apr 2008] b) Perform the subtraction on the following numbers using the 9,s complement of the subtrahend 1. 5763-3145 2. 59-9876 3. 5200-561 xii) Simplify the Boolean function using variable entered mapping method and implement using gates F(w,x,y,z)= (0,2,4,6,8,10,12,14) [Nov 2007] xiii) Using tabulation method simplify the Boolean function [Nov 2007]

AIHT

DEPARTMENT OF ECE

DPSD

27
F(w,x,y,z)=(1,2,3,5,9,12,14,15) which has the dont care conditions d(4,8,11). xiv) Reduce the Boolean function using K-map technique and implement using gates f(w,x,y,z)= (0,1,4,8,9,10) which has the dont care conditions d(w,x,y,z)= (2,11). [May 2007] xv) Simplify the following Boolean function by using the tabulation method [May 2007] F= (0,1,2,8,10,11,14,15). xvi) Reduce the expression using Quine McCluskey method. [Nov 2011(R10)] F(x1 ,x2, x3, x4,x5 ) = m 1 2 3 4 5 , , , , (0, 2, 4, 5, 6, 7, 8, 10, 14, l7, l8, 21, 29, 31) + d (11, 20, 22). 2. Boolean algebra and theorems [Apr 2010(R08);Nov 2009(R08); Nov 2009; May 2007;May 2006] i) a)Simplify the following Boolean function F together with dont care condition d and then express the simplified function in sum of min terms [Apr 2010(R08)] F(w,x,y,z)= (1,3,7,11,15) + d(0,2,4) b) Implement the following Boolean function with NAND gates F(x,y,z)= (1,2,3,4,5,7) ii) i) Implement Boolean expression for EXOR gate using NAND and NOR gates. ii)Prove that (AB+C+D)(C+D)(C+D+E)=ABC+D. iii)Using 2s complement perform (42)10-(68)10. iii) i) Use Boolean theorems and simplify the following: 1)ABC+ABC+ABC+ABC+ABC+ABC 2)(A+B+C)(A+B+C)(A+B+C)(A+B+C) ii)State and prove the various Boolean Theorems. iv). i) Simplify the following Boolean function F(w,x,y,z)= (1,3,7,11,15)that has the dont care conditions d(w,x,y,z)= (0,2,5). ii)State and prove consensus theorem. v) . a)State Duality principle. Give relevant example. b)i) Simplify the Boolean function F(x,y,z)=(0,2,4,5,6). ii) Simplify the Boolean function F(x,y,z)=(0,2,5,7). [May 2006] [May 2007] [Nov 2009(R08)] [Nov 2009]

vii) Explain the conversion of regular expression into canonical expression

and their simplification in SOP and POS forms. 3. (i) Convert (1947 )10 into its equivalent octal and hexadecimal representations. (ii) Perform (147-89 ) using 2's complement binary arithmetic. 4. (i) Minimize the following expression using Karnaugh map. Y = ABCD + ABCD + AB CD + AB CD + AB CD . (ii) State and prove the De Morgan's theorems.

[Nov 2011(R10)] [Apr 2011(R08)] [Apr 2011(R08)]

5. a) Use 2s complement and 1s complement to perform M-N with the given binary numbers

AIHT

DEPARTMENT OF ECE

DPSD

28
M=1010100 N=1000100 Also compare their computational complexity. b) Prove the following theorem using Boolean algebraic postulates 1) x + x = x 2) x . x = x 3) x + 1 = 1 6. Determine the minterm sum of products form of the switching function f= (0,1,4,5,6,11,14,15,16,17,20-22,30,32,33,36,37,48,49,52,53,59,63) 7. What are Universal gates? Represent all the gate operations with universal gates. 8. Give the Boolean function F=xy+xy+yz a) Implement it with AND, OR and inverter gates b) Implement it with OR and inverter gates c) Implement it with AND and inverter gates 9. a) Find the prime implicants for the following function and determine which are essential F(w,x,y,z)=(0,2,4,5,6,7,8,10,13,15) b) Draw a NAND logic diagram that implements the complement of the function F(A,B,C,D)=(0,1,2,3,4,8,9,12) 10. a) Convert the following hexadecimal numbers to decimal. i)(1C) 16 ii)(A85) 16 iii) (E5) 16 iv)(B2F8) 16 b) List out any basic rules that are used in Boolean algebra expression. [Nov 2009] [Nov 2008]

[Nov 2010]

[Nov 2010(R08)]

[Nov 2008] [Nov 2006]

UNIT II 1. Circuits for arithmetic operations [Nov 2010; Nov 2010; Nov 2010(R08); Apr 2010(R08); Nov 2009(R08); Nov 2009,Nov2007; Nov 2009; Nov 2008; May 2007;May 2006] i) a) Design a full adder using only NAND gate [Nov 2010] b) Write HDL code to realize a full adder ii). a) Design a 3 bit adder with carry look ahead [Nov 2010] b) Design a 2 bit by 2 bit binary multiplier iii). Design a full adder and subtractor using NAND and NOR gates respectively [Nov 2010(R08)] iv). a) Design a full adder circuit with necessary diagram [Apr 2010(R08)] b) Write the HDL description of the circuit specified by the following Boolean function X= AB + C Y= C v). With neat diagram explain BCD subtractor using 9s complement and 10s complement method. [Nov 2009(R08)] vi). Design a full adder and a full subtractor and implement it with a suitable decoder. [Nov 2009,Nov2007]

vii). What is a Combinational circuit? Explain with various circuit of how arithmetic operations are performed? [Nov 2009] viii). a) Design a 4bit combinational circuit incrementer- A circuit that adds one to a 4bit binary number? Use half adders for the problem [Nov 2008]

AIHT

DEPARTMENT OF ECE

DPSD

29
b) Design a combinational circuit that generates the 9s complement of a BCD digit ix). Construct a full adder circuit and write a HDL program module for the same. x).Give the truth table ,logic diagram for a Full-Adder circuit and discuss the same. [May 2007] [May 2006]

2. i) Design a combinational circuit that comprises only of NOR gates for the following expression giving the input output relation. [Apr 2011(R08)] Y = AB C + AC + B C . (ii) Draw the schematic of a full adder circuit and give its truth table. 3. Code conversion: [Dec 2011;Apr 2011(R08); Nov 2010(R08); Apr 2010(R08); Apr 2010; Apr 2008; Apr 2008; Nov 2007; May 2007; Nov 2006; Nov 2011(R10)] i).(i) Design a BCD to Excess-3 code converter using truth table and K-Map simplification. (ii) Draw the schematic of a magnitude comparator and give its truth table. ii) Realize a BCD to excess 3 code conversion circuit starting from its truth table [Nov 2010(R08)] iii). Design a combinational logic diagram for BCD to excess 3 converter [Apr 2010(R08)]

iv) Design a BCD to 7 segment decoder that converts a decimal digit in BCD to an appropriate code for the selection of segments in the display indicator used for displaying the decimal digit in a familiar form using a minimum number of NAND gates. Use the segment designations as given in the figure [Apr 2010]

v).i. Design a combinational circuit to convert gray code to BCD [Apr 2008] ii.What are the design procedures of combinational circuit. vi).i. Design a combinational circuit to convert BCD code to Excess-3 code [Apr 2008] ii. Design a 3bit adder. vii). i. design a combinational circuit to convert gray code to BCD. [Nov 2007] viii). Design a network of AND and OR gates to convert excess 3 code to 8-4-2-1 BCD code. [May 2007 ix).Explain the procedure for converting Binary to Grey code number and Grey code to Binary number with samples. [Nov 2006] 4. Analyse the combinational circuit shown in figure find the Boolean functions for the outputs as a function of inputs and explain the circuit operation [Apr 2010]

AIHT

DEPARTMENT OF ECE

DPSD

30

5.. i) Explain the gray code to binary converter with the necessary diagram. ii) Design a half subtractor circuit. 6. Explain with necessary diagram a BCD to 7 segment display decoder. 7.a) Design a combinational circuit with three inputs and one output .The output is 1 when the binary value of the inputs is less than three. The output is zero otherwise. b) Design a code converter that converts a decimal digit from 8,-4,-2,-1 code to BCD. 8. Design a 4 bit magnitude comparator to compare two 4 bit numbers. 9..i)Design a combinational circuit to convert BCD to gray code ii) Design a 4 bit subtractor. 10. .i)Design a combinational circuit to convert Excess-3 code to BCD code. ii)Design a 2bitX2bit multiplier.

[Nov 2009(R08)] [Nov 2009]

[Nov 2008] [Nov 2007] [May 2007] [May 2007]

11. Design a combinational circuit that multiplies by 5 an input decimal digit [Nov 2011(R10)] represented in BCD. The output is also in BCD. Show that the outputs can be obtained from the input lines without using any logic gates. 12. A circuit receives only valid 5211 or 8421 BCD information and provides [Nov 2011(R10)] two output lines X and Y. Design the circuit such that X will provide an output anytime a valid 8421 BCD code appears at the input and Y will provide an output anytime a valid 5211 BCD code appears at the input.

13.Consider the combinational circuit shown in Figure 1 [Dec 2011] (i) Derive the Boolean expressions for 1 T through T4. Evaluate the outputs F1 and F2 as a function of the four inputs. (4) (ii) List the truth table with 16 binary combinations of the four input variables. Then list the binary values for T1 through T4 and outputs F1 and F2 in the table. (4) (iii) Plot the output Boolean function obtained in part (ii) on maps and show that simplified Boolean expressions are equivalent to the ones obtained in Part (i) Figure 1.

14. (i) With suitable block diagram explain Binary multiplier. (ii) Write a detailed note on carry propagation. AIHT DEPARTMENT OF ECE

[Dec 2011]

DPSD

31

UNIT-III 1.Decoder [Dec 2011]

(i) Construct a 5 to 32 line decoder with four 3 to 8 line decoders with enable and a 2 to 4 line decoder. Use block diagrams for components [Dec 2011]
2. Multiplexer and Demultiplexer [Apr 2011(R08);Nov 2010(R08); Nov 2009; Nov 2008; Nov 2008; Apr 2008; Nov 2007; May 2006; Nov 2011(R10)] i).(i) Design a combinational logic using a suitable multiplexer to realize the following Boolean expression. Y = AD + B C + BCD [Apr 2011(R08)] (ii) Compare and contrast between encoders and multiplexers ii) a) Define Multiplexer [Nov 2010(R08)] b)Implement the following Boolean function using 8:1 MUX F(A,B,C,D)= ABD + ACD + BCD + (AC)D iii) i) Explain how HDL is used for combinational circuits. ii) Explain the functionality of a multiplexer to get 12 outputs. iv). a)A 8X1 multiplexer has inputs A,B and C connected to the selection inputs S2,S1, and S0 respectively. The data inputs I0 to I7 are as follows I1=I2=I7=0; I3=I5=1;I4=D and I6=D. Determine the Boolean function that the multiplexer implements. [Nov 2008] b) Write the HDL dataflow description of a quadrapul -2 to -1 line multiplexers with enable v). a) Using the conditional operator (?:), write a HDL dataflow description of a 4bit adder subtractor of unsigned numbers [Nov 2008] b) Implement the Boolean function F=(0,1,3,4,8,9,15) using a multiplexer vi).i.Implement the boolean function using 4:1 multiplexer. [Apr 2008] F(W,X,Y,Z)=(1,2,3,6,7,8,11,12,14) ii. A combinational circuit is defined by the functions F1=(1,3,5) F2=(5,6,7) Implement the circuit with a PLA having 3 inputs, 3 product terms and two outputs vii). Implement the boolean function using 8:1 multiplexer F(A,B,C,D)= ABD+ACD+BCD+ACD viii).i) Implement the following function with a multiplexer. F(A,B,C,D)=(0,1,3,4,8,9,15). ii)A combinational circuit is defined by the functions: F1(A,B,C)= (3,5,6,7) F2(A,B,C)= (0,2,4,7) ix) Implement the following Boolean function with a 4 X 1 multiplexer and external gates. [Nov 2007] [May 2006] [Nov 2009]

[Nov 2011(R10)]

AIHT

DEPARTMENT OF ECE

DPSD

32
Connect inputs A and B to the selection lines. The input requirements for the four data lines will be a function of variables C and D. these values are obtained by expressing F as a function of C and D for each of the four cases when AB=00, 01, 10 and 11. These functions may have to be implemented with external gates. F(A,B,C,D)= S (1,3,4, 11, 12, 13, 14, 15)

2. Memory and Programmable logic [Apr 2011(R08); Nov 2010(R08); Apr 2010(R08); Apr 2010; Nov 2009(R08); Nov 2007; May 2007; May 2007] i) (i) Write short notes on the basic configuration of the three types of programmable Logic Devices. (ii) Draw the signals of a 32 8 RAM with control input. Show the external connections necessary to have a 128 8 RAM using a decoder and replication of this RAM. [Apr 2011(R08)] ii). Implement the switching functions [Nov 2010(R08)] Z1= abde + abcde + bc + de Z2= (ac)e Z3= bc + de + cde + bd Z4= (ac)e + ce Using a 5X8X4 programmable logic array iii). We have found a minimum sum of products expression for each of two functions F and G, minimizing them individually(no sharing) [Apr 2010(R08)] F= WY + XYZ G= WXY + XY + WYZ a) Implement them with a ROM b) Implement them in the PLA using no more than 4 terms iv). Design a combinational circuit defined by the following Boolean function using a PAL [Apr 2010] W(A, B, C, D) = (2,12,13) X(A,B,C,D)= (7,8,9,10,11,12,13,14,15) Y(A,B,C,D)= (0,2,3,4,5,6,7,8,10,11,15) Z(A,B,C,D)= (1,2,8,12,13) v). a) Write the comparison between PROM, PLA and PAL. [Nov 2009(R08)]

b) Design BCD to Excess-3 converter and implement using PLA

AIHT

DEPARTMENT OF ECE

DPSD

33
vi). Explain the different types of ROM [Nov 2007] vii). A combinational circuit is defined by the functions [May 2007] F1(A,B,C)=(3,5,6,7) F2(A,B,C)=(0,2,4,7) implement the circuit with a PLA. viii). Using Rom, implement a combinational circuit which accepts a 3 bit number and generates an output binary number equal to the square of the input number. [May 2007] 3. Design a 4bit magnitude comparator and explain its operation 4. Design a 2 to 4 line decoder and write the HDL code 5. a)Design a 3:8 line decoder with necessary diagram b) Implement the given Boolean function using 4X1 multiplexer F(X,Y,Z)= (1,2,6,7) 6. a) Implement F(A,B,C)= (1,3,5,6) with the 4:1 multiplexer b) Write the HDL code for a 2:4 decoder c) Write notes on the different types of ROM 7. Explain with necessary diagram a BCD to 7 segment display decoder. 8. Design comparator. 9. Design a parity checker. [Nov 2009(R08)] [Nov 2009] [Nov 2009] [Apr 2010] [Nov 2010] [Nov 2010] [Apr 2010(R08)]

10. Construct a BCD adder circuit and write a HDL program module for the same [Apr 2008] 11. i) Implement the following Boolean function using 8:1 multiplexer. F(A,B,C,D)=ABD+ACD+BCD+ACD ii) What are the advantages of PLA over ROM? Explain the internal construction of PLA. [May 2007] 12. Distinguish between Encoder and Decoder circuits. Give example for the same. [Nov 2006] 13. Design a combinational circuit that compares two 4 bit numbers A and B [Nov 2011(R10)] to check if they are equal. The circuit has three output x, y, z so that x =1 if A = B and y = 1 if A < B and z = 1 if A > B.

14.Implement the following Boolean function with 16 1 multiplexer : [Dec 2011] F (A, B ,C, D) = (0, 1, 3, 4, 8, 9,15) , Use block diagram representation. (ii) Write HDL gate level description for 3 to 8 line decoder. (iii) With suitable timing diagram explain how Read operation is performed in Random access memory.

UNIT IV 1. Flip Flops: [Nov 2010; Nov 2010(R08) ; Nov 2010(R08);Apr 2010(R08); Nov 2010; Nov 2010(R08); Apr 2010(R08); Nov 2009(R08); Nov 2009; May 2006; Nov 2011(R10)]

i) Design a MOD 16 up counter using JK Flip flops.

[Dec 2011]

ii) Derive the reduced state table, characteristic equations and the sequential circuit (with JK flip flops and logic gates) for the following state diagram [Nov 2010]

AIHT

DEPARTMENT OF ECE

DPSD

34

iii). Design a clock sequential machine using T flip flops for the following state diagram. Use state reduction if possible. Also use straight binary state assignment [Nov 2010(R08)]

iv). Design a T flip flop from logic gates

[Nov 2010(R08)]

v). Design a synchronous sequential circuit using JK flip flop to generate the following sequence and repeat 0,1,2,4,5,6 vi) a) Explain the operation of a 4 bit serial-in serial-out shift register b) Design a 4bit synchronous counter with T flip flops vii). Using RS flip flop design a parallel counter which counts the sequence 000,111,101,110,001,010,000,. viii). What is the aim of state reduction? Reduce the given state diagram and prove that the both state diagrams are equal [Apr 2010(R08)] [Apr 2010(R08)] [Nov 2010]

[Nov 2010(R08)]

AIHT

DEPARTMENT OF ECE

DPSD

35

ix). i) Design a parity checker ii) Design s sequential circuit with JK flip-flop.

[Nov 2009(R08)]

x).Design and explain an asynchronous master slave JK flip flop and give its truth table. [Nov 2009] xi) a)Design an Asynchronous BCD down counter using J-K flip=flop and verify its operation [May 2006] b) What are Edge triggered flip-flops. Discuss. 2.State Reduction and State Assignment

i)With suitable example explain state reduction and state assignment.

3. Counters

[Dec 2011]

[Apr 2011(R08);Nov 2009(R08); Nov 2009(R08); May 2007; May 2007; Apr 2010; Apr 2010; Nov 2009(R08); Nov 2009; Nov 2009; Nov 2008; Nov 2008; Apr 2008; Apr 2008; Nov 2007; Nov 2007, May 2006; May 2007; May 2007] i) A synchronous counter with four JK flip-flops has the following connections : JA = KA=1 [Apr 2011(R08)]

AIHT

DEPARTMENT OF ECE

DPSD

36
JB= QA QD, KB= QA JC = KC =QAQB JD = QAQBQC, AND KD= QA Determine the modulus n of the counter, and draw the output waveforms of the same. ii) Design a synchronous counter using JK flip-flops to count the following sequence : 1-3-15-5-8-2-0-12-6-9. iii). Design and implement a Mod-5 synchronous counter using JK filp-flop. Draw the timing diagram also. [Nov 2009(R08)] iv). i) Design a comparator [Nov 2009(R08)] ii) Design a non sequential ripple counter which will go through the states 3,4,5,7,8,9,10,3,4 . Draw bush diagram also. v). Explain the operation of 4-bit binary ripple counter. vi). Explain the operation of BCD counter. [May 2007] [May 2007]

4. a)A sequential circuit with 2 D flip flops A and B, two inputs X and Y and one output Z, specified by the following next state and output equations [Apr 2010] A(t+1)= xy + xA B(t+1)= xB + xA z= B Draw the logic diagram of the circuit, derive the state table and derive the state diagram b) How do ripple counters differ from synchronous counters? Explain 5. a)Explain how shift registers are used in serial addition with a neat diagram b) Give the HDL description of master slave JK flip flop 6. i) Explain the working of master slave JK flip-flop. ii) Draw the diagram for a 3 bit ripple counter. [Nov 2009(R08)] [Nov 2009] [Apr 2010]

7.Explain how shift registers are useful in performing arithmetic operations. [Nov 2009] 8.a) Draw the logic diagram of a 4bit shift register with four D flip-flops and four 4X1 multiplexers with mode selection inputs s1 and s0. The register operates as follows.\ S1 S0 Register operation 0 0 No change 0 1 Complement 1 0 Clear to 0 1 1 Load parallel data b) Construct a JK flip-flop using D flipflop, a 2X1 multiplexer and an inverter. [Nov 2008]

AIHT

DEPARTMENT OF ECE

DPSD

37
9. a) Explain the differences among a truth table, a state table ,a characteristic table and an excitation table . Explain the difference among a Boolean expression, a state equation , a characteristics equation and a flip-flop input equation. b)A sequential circuit has two JK flip-flops A and B, two inputs x and y and one output z. The flip-flop input equations and circuit output equations are Jk=Bx+By Ka=Bxy Jb=Ax Kb=A+xy Z=Axy+Bxy i) Draw the logic diagram of the circuit\ ii) Tabulate the state iii) Draw the state diagram [Nov 2008] 10. Explain the different types of shift registers with neat diagram. [Apr 2008] 11. Design a sequence detector to detect the sequence 101011 [Apr 2008] 12. Construct a full subtractor circuit and write a HDL program module for the same. i. ii. Compare synchronous with asynchronous counters. Explain the behavioral model with suitable example. [Nov 2007]

13. i. A positive edge triggered flip-flop has two inputs D1 and D2 and a control input that chooses between the two. Write a HDL behavioral description of this flip-flop. ii. Construct and explain 4 stage Johnson counter. [Nov 2007, May 2006] 14. i) Explain the operation of D-Type Edge triggered flip-flop. ii) Write HDL code for the following Mealy sate diagram. [May 2007] 15. What are the general capabilities of universal shift register? And write the HDL code for the same. [May 2007] 16. Design the following non binary sequence counters as specified in each case. Treat the [Nov 2011(R10)] unused states as dont care conditions. Analyze the final circuit to ensure that it is self correcting. If your design produces a non self correcting counter, modify the circuit to make itself correcting. (i) Design a counter with the following repeated binary sequence: 0,1,2, 3, 4, 5, 6. Use JK flipflops. (ii) Design a counter with the following repeated binary sequence: 0,1,2, 4, 6. Use D flipflops. (iii) Design a counter with the following repeated binary sequence: 0,1,3, 5, 7. Use T flipflops. UNIT-V 1. Hazards [Dec 2010;Nov 2010; Nov 2010(R08); Apr 2010(R08); Apr 2010; Apr 2008; Nov 2007; May 2007; Nov 2011(R10)] i).What is an hazard? Analyze whether a hazard is present in the circuit represented by the following logic expression. If an hazard is present, give the hazard free circuit. [Nov 2010] Y= X1X2 + X2X3 ii). Find the static and dynamic hazard free realization for the following function using a)NAND gates b) NOR gates f(a,b,c,d)= m(1,5,7,14,15) [Nov 2010(R08)] iii). With suitable example and diagram explain the hazards in combinational and sequential logic circuits [Apr 2010(R08)] iv). a) Discuss in detail different types of hazards in digital circuits [Apr 2010] b) Discuss the need and operation of debounce circuit with a neat diagram v). Explain essential, static, and dynamic hazards in digital circuit. Give hazard-free realization for the following Boolean function.

AIHT

DEPARTMENT OF ECE

DPSD

38
F(I,J,K,L)=m(1,3,4,5,6,7,9,11,15) vi). i. Explain the need for key debounce circuit. ii. what is the objective of state assignment in asynchronous circuit? Give hazard free realization for the following boolean functions F(A,B,C,D)= M(0,1,5,6,7,9,11) vii). i)Give hazard-free realization for the following Boolean function F(A,B,C,D)=m(1,3,6,7,13,15) ii) Summarize the design procedure for asynchronous sequential circuit. [May 2007] [Nov 2007] [Apr 2008]

2. Reduction of state and flow tables [Nov 2010; Apr 2010(R08); Apr 2010; Nov 2009; Nov 2008; May 2007; May 2006; Nov 2009; Nov 2008] i).Derive the asynchronous sequential circuit specified by the following flow table x1x2 [Nov 2010]

ii). With necessary example and diagram explain the concept of reduction of state and flow table [Apr 2010(R08)] iii). a)Design a sequential circuit using RS flip flop for a state table given below using minimum number of flip flops. [Apr 2010] Present state Next state Output x=0 x=1 x=0 x=1 a A b 0 0 b C d 0 0 c A d 0 0 d E f 0 1 e A f 0 1 f G f 0 1 g A f 0 1 b) Draw the block diagram for asynchronous sequential circuit. List the steps involved in the design of the asynchronous sequential circuit iv) Explain how state reductions in flow tables is performed using asynchronous sequential circuits. [Nov 2009] v) a) with examples, explain the different types of races in Asynchronous sequential circuits

AIHT

DEPARTMENT OF ECE

DPSD

39
b) An asynchronous sequential circuit is described by the excitation and output functions Y=x 1x2+(x1+x2)y and z=y where Y and z are excitation and output functions respectively. 1. Draw the logic diagram of the circuit 2. Derive the transition table and output map 3. Obtain a two-state flow table 4. Describe the behavior of the circuit [Nov 2008] vi). An asynchronous network has two inputs and one output. The input sequence X1X2 =00, 01,11causes the output to become 1.The next input change then causes the output to return to 0. No other input sequence will produce a 1 output. Construct the state diagram using primitive flow table. [May 2007] vii).a)Design a circuit with inputs A and B to give an output Z equal to 1 when AB=11 but only if A becomes 1 before B, by drawing total state Diagram, primitive flow table and output map in which transient state is Included. [May 2006] b) Design a circuit with primary inputs A and B to give an output Z equal to 1 When A becomes 1 if B is already 1.Once Z=1 it will remain so until A goes to c ) Draw waveform diagram, total state diagram, primitive flow table for Designing the circuit. 3. (i) Explain the working principle of switch debounce logic. [Apr 2011(R08)] (ii) Determine whether the circuit is stable or not whose excitation function is given by y = (x1 y) x2 4. (i)Derive a circuit specified by the following flow table. [Apr 2011(R08)]

(ii) Determine whether the following circuit has a static hazard or not. If yes, design a hazard-free logic for the same input and output relation.

5. Design and explain Fundamental mode and pulse mode sequential circuits. [Nov 2009] 6. a) Explain the difference between asynchronous and synchronous sequential circuits. Define fundamental mode operation. Explain the difference between stable and unstable states. What is the difference between an internal state and the total state? b) With examples, explain different types of hazards in sequential circuits. [Nov 2008] 7. (a) (i) Reduce the number of states in the state table and tabulate the reduced state table. [Nov 2011(R10)]

AIHT

DEPARTMENT OF ECE

DPSD

40

(ii) Starting from state a of the state table, find the output sequence generated with an input sequence 01110010011. 8. (a) A traffic light is installed at a junction of railroad and road. The traffic light is [Nov 2011(R10)] controlled by two switches in the rails placed one mile apart on either side of the junction. A switch is turned on when the train is over it and is turned off otherwise. The train light changes from green (logic -0) to red (logic - 1) when the beginning of the train is one mile from the junction. The light changes back to green when the end of the train is one mile away from the junction. Assume that the length of the train is less than two miles. (i) Obtain the primitive flow table for the circuit. (ii) Show that the flow table can be reduced to four rows 7. Analysis of Asynchronous Sequential Circuits [Dec 2011; Apr 2008; Nov 2007; May 2007]

(i) Write a detailed note on Race free state assignment.

[Dec 2011]

ii). An asynchronous sequential circuit is described by the following excitation and output function. X=(Y1Z1W2)X+(Y1Z1W2), S=X 1. Draw the logic diagram of the circuit 2. Derive the transition table and output map 3. Describe the behavior of the circuit iii). An asynchronous sequential circuit described by the following excitation and output function [Apr 2008]

AIHT

DEPARTMENT OF ECE

DPSD

41
B=(A1B2)B+(A1+B2) C=B i. ii. Draw the logic diagram of the circuit. Derive the transition table and output map.

iii. Describe the behavior of the circuit. [Nov 2007] iv). An asynchronous sequential circuit is described by the following excitation and output function. Y=X1X2+(X1+X2)Y i) Draw the logic diagram ii) Derive the transition table and output map iii) Describe the behavior of the circuit. [May 2007] 8.a)Draw the fundamental mode Asynchronous circuits and explain in detail. b) Define the following terms. i) Critical-race ii) Non-Critical race iii) Hazards iv) Flow table 9. An asynchronous sequential circuit is described by the following excitation and output functions Y = x1x2'+(x1 + x2' )y Z=y (i) Draw the logic diagram of the circuit. (ii) Derive the transition table and output map. (iii) Obtain 2 state flow table. (iv) Describe in words the behavior of the circuit. [Nov 2006]

[Nov 2011(R10)]

10. With suitable design example, explain ASM Chart.

[Dec 2011]

Staff Signature

HOD

AIHT

DEPARTMENT OF ECE

DPSD