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Summary 921
Introduction 922
Modeling Details 922
Solution Highlights 924
Results 925
Modeling Tips 926
Pre- and Postprocess with SimXpert 927
Input File(s) 969
Video 970
CHAPTER 46 921
Thermal Stress Analysis of an Integrated Circuit Board
Summary
Title Chapter 46: Thermal Stress Analysis of an Integrated Circuit Board
Features Chaining thermal and stress analysis in one execution
Geometry
Chip
Leads
Case
Paste
14 x 14 x 3.22
Units: mm, N, C
Material properties
Material k W mm C E N mm 2 (1/C)
Lead frame 0.147 6.9x104 1.0x10-6
Chip 0.168 5.52x104 1.0x10-5
Case 0.0714 4.5x104 1.0x10-6
Paste 0.02016 2.0x103 1.0x10-5
Introduction
This example demonstrates the chaining of thermal and structural analysis in SOL 400 whereby the first step is a
nonlinear steady state thermal analysis subject to heat flux on the chip, convection and radiation boundary conditions,
and the second step is a nonlinear static analysis using the temperatures from the first step. The thermal stress analysis
chaining has always been available in the linear heat transfer to linear static analysis using param, heatstat,yes in the
SOL 101 run. However, it was not possible previously in Nastran to run a nonlinear heat transfer followed by the static
analysis in a single execution because SOL 101 is a linear heat transfer solution. The only alternative is to run a
nonlinear thermal analysis using SOL 153 and used the resulting temperature punch file as the input thermal load for
your stress analysis. The user can output a punch file by specifying TEMP(PRINT,PUNCH)=all in the first run. This
will create a punch file that consists of temperature for every grids in the model. In the thermal stress run he can use
the TEMP(LOAD)=1 in the case control to use the temperature load in the static run. Chaining of thermal and structural
analyses facilitates design studies based on:
1. changing the materials properties
2. changing the thermal boundary conditions
3. changing structure constraints
whereby the temperatures as well as the corresponding displacements are visualized in a single run.
Modeling Details
Bonded joints are used in the design of a circuit board. A change in temperature due to the equipment operation can
introduce stresses in joined materials of dissimilar thermal expansion coefficient. In this case we have chip heating
due to the applied power, causing thermal gradients in the different materials which, together with the fixed
displacements cause high stresses near the end of the lead frame.
The chip dimension (Figure 46-1) is 3.80 mm by 3.80mm with thickness equal to 0.7 mm. It is mounted on top of
adhesive (paste). The outer case dimension is 14 mm by 14 mm by 3.22 mm.
Chip
Figure 46-1 Chip, Paste, and Lead Frame (Nastran Test File: hybrid_radbc_unit.dat)
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Thermal Stress Analysis of an Integrated Circuit Board
14 x 14 x 3.22
A heat flux is applied to the top surface of the chip with heat flux equal to 0.025 W/(mm2oC). The top surface, bottom
surface and the sides (adjacent to the lead frame where it is fixed) of the case are subjected to convection heat loss.
Heat is convected to the environment at 70oC. The respective heat transfer coefficient for the top, bottom and sides
are 4.05x10-5 W/(mm2oC), 2.026x10-5 W/(mm2oC) and 7.00x10-5 W/(mm2oC). Finally there is a radiation loss on top
of the outer case to ambient environment of 40oC with emissivity equal to 0.8 and view factor is 1.0.
The structural boundary conditions include fixing the end of the lead frame as shown in Figure 46-3.
In running a thermal stress analysis, it is important to check you have specified a thermal coefficient of expansion on
the field 7 on the MAT1 bulk data entry. Otherwise, there will be no thermal expansion in your problem.
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It is important that you have a consistent set of units. In this case, the thermal conductivity has units of W/(mm2 K),
and therefore your Young's modulus should be in the unit of N/(mm2). This consistency also applies to the Stefan-
Boltzmann constant also used in the radiation boundary conditions with units of W/(mm2 K).
Solution Highlights
The following are highlights of the Nastran input file necessary to model this problem:
$! NASTRAN Control Section
NASTRAN SYSTEM(316)=19
$! File Management Section
$! Executive Control Section
SOL 400
CEND
ECHO = SORT
$! Case Control Section
TEMPERATURE(INITIAL) = 33
SUBCASE 1
$! Subcase name : NewLoadcase
$LBCSET SUBCASE1
ANALYSIS = NLSTAT
STEP 1
$LBCSET STEP1.1 Thermal
$! Step name : Thermal
ANALYSIS = HSTAT
SPC = 36
LOAD = 37
NLSTEP = 2
TSTRU = 38
THERMAL(SORT1,PRINT)=ALL
FLUX(PRINT)=ALL
STEP 2
$LBCSET STEP1.2 Structural
$! Step name : Structural
SPC = 11
ANALYSIS = NLSTAT
NLSTEP = 3
TEMPERATURE(LOAD) = 38
DISPLACEMENT(SORT1,PRINT,REAL)=ALL
STRESS(SORT1,PRINT,REAL,VONMISES,CORNER)=ALL
BEGIN BULK
$! Bulk Data Pre Section
PARAM SNORM 20.
PARAM K6ROT 100.
PARAM WTMASS 1.
PARAM LGDISP 1
PARAM TABS 273.15
PARAM* SIGMA 5.6699E-14
PARAM POST 1
$! Bulk Data Model Section
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Thermal Stress Analysis of an Integrated Circuit Board
There are two steps in this analysis. The first step is associated with the thermal boundary conditions as indicated with
ANALY=HSTAT. The second step is the thermal stress analysis and the structure boundary condition which the
ANALY=NLSTAT. The TEMP(load)=1 in the second step will allow the Step 2 to pick up the calculated temperature
from step 1 as the thermal load for the calculation of thermal stress. Please note that the param,lgdisp,1 is required
when chaining thermal and structural analyses. The TEMP(INITIAL)=9 points to the TEMPD,9,0.0 in the bulk data
section. This indicates the initial stress free temperature is at zero degrees. The thermal strain is then equal to the
product of the linear coefficient of thermal expansion times the change in temperature. In this example, the thermal
coefficient of expansion is constant, temperature dependency is also readily possible.
Following is the output from the thermal analysis and thermal stress analysis.
1 JUNE 11, 2010 MD NASTRAN 5/21/10 PAGE 896
0 SUBCASE 1 STEP 1
LOAD STEP = 1.00000E+00
T E M P E R A T U R E V E C T O R
POINT ID. TYPE ID VALUE ID+1 VALUE ID+2 VALUE ID+3 VALUE ID+4 VALUE ID+5 VALUE
6320 S 8.666747E+01 8.661747E+01 8.657528E+01 8.654037E+01 8.651233E+01 8.649082E+01
6327 S 8.697186E+01 8.687786E+01 8.679778E+01 8.672908E+01 8.667010E+01 8.661977E+01
6333 S 8.657732E+01 8.654223E+01 8.651408E+01 8.649251E+01 8.647716E+01
0 SUBCASE 1 STEP 2
LOAD STEP = 1.00000E+00
D I S P L A C E M E N T V E C T O R
Results
Modeling Tips
Always check consistency of units; the basic units are mm, N, and oC(K).
$watt/mm.C
MAT4 1 .147 1. 1.
$ Material Record : mat1.2
$ Description of Material :
MAT4 2 .168 1. 1.
$ Material Record : mat1.3
$ Description of Material :
MAT4 3 .0714 1. 1.
$ Material Record : mat1.4
$ Description of Material :
MAT4 4 .02016 1. 1.
$
CHAPTER 46 927
Thermal Stress Analysis of an Integrated Circuit Board
MAT1,1,6.9e4,,0.3,,1.0e-6
$ Material 2 : leadframe
MAT1,2,5.52e4,,0.3,,1.0e-5
$ Material 3 : new
MAT1,3,4.5e4,,0.3,,1.0e-6
$ Material 4 : paste
MAT1,4,2.0e3,,0.3,,1.0e-5
Units
a
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a. Tools: Options
b. Observe the User Options Window
c. Select Units Manager
d. For Basic Units, specify the model units:
e. Length = mm; Mass = g; Time = s; Temperature = celsius, Force = N
f. Click OK
a b
c e
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c
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b c
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Material Properties
b
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b
d
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Element Properties
b
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f
.
b . g
h
g
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c
b
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e
f
g
f
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a. Observe the entire model with normal heat flux on the chip and free convection on the top
of the case
a
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Thermal Stress Analysis of an Integrated Circuit Board
f
g
h
g
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CHAPTER 46
a. Observe the entire model with normal heat flux on the chip and free convection on the top
and two sides of the case
a
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Thermal Stress Analysis of an Integrated Circuit Board
e
f
g
f
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CHAPTER 46
a. Observe the entire model with normal heat flux on the chip and free convection on the top,
two sides, and bottom of the case
a
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a
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c
d
.
e
f
g
h
i
j
k
e
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Thermal Stress Analysis of an Integrated Circuit Board
a. Observe the entire model with normal heat flux, free convection, and radiation to space
on the case
a
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CHAPTER 46
d
CHAPTER 46 947
Thermal Stress Analysis of an Integrated Circuit Board
a. Create a structural pinned lbc constraint at the toe of the lead frame
b. LBCs tab: Constraints/Pin
c. For Name, enter Pinned Constraint_Toe_Lead
d. Use Model Views: Left or Front
e. For Entities screen, select the toe lead frame nodes
f. Click OK
e e
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a
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Thermal Stress Analysis of an Integrated Circuit Board
c
d
g
h
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f
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b
c
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f
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e
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b
c
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d
c
f
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e
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b c
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d
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c d
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a
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a. To display the structural results for the R3.2 release of SimXpert, use an .op2 file
b. Double click on Solver Control
c. Select Output File Properties
d. For Binary Output, select OP2
e. Click Apply
f. Click Cost
f
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c
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a. Before attempting to attach the .op2 file, detach the .xdb file
b. File: Detach Results file
c. Select ch46.xdb
d. Select OK
e. Click Yes
b
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d
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f
d e
c
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Input File(s)
File Description
nug_46.dat MD Nastran chaining thermal and thermal stress test file.
Ch46.SimXpert SimXpert data corresponding to above
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Video
Click on the image or caption below to view a streaming video of this problem; it lasts approximately 28 minutes and
explains how the steps are performed.