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05/04/2012

Sistemi Digitali per lElaborazione Numerica

Domande a scelta multipla (2 punti ciascuna)
La risoluzione assoluta di una rappresentazione Q16.15 in complemento a 2 (cio ogni parola occupa 32 bit, di cui 16 per la parte intera e il segno e 16 per la parte frazionaria)... ( )a pari a quella di un numero floating point a singola precisione ( )b inferiore a quella di un numero floating point a singola precisione ( )c superiore a quella di un numero floating point a singola precisione Un numero in precisione multipla occupa 4 byte. Se lequivalente rappresentazione esadecimale di questi 4 byte A, B, C e D, allora in quale ordine verr salvato in memoria?... ( )a ABCD ( )b DCAB ( )c dipende dallorganizzazione big endian or little endian del sistema Una memoria ROM di tipo Flash: ( )a deve essere periodicamente rinfrescata per preservare il contenuto ( )b generalmente pi veloce di una memoria RAM ( )c si basa un transistor a gate flottante Una connessione seriale asincrona... ( )a necessita di un header iniziale ( )b adatta a trasmettere dati ad elevato bit rate ( )c necessariamente di tipo unidirezionale (half duplex) In una FSM di ( )a luscita ( )b luscita ( )c luscita Se si ( )a ( )b ( )c Mealy: una funzione dello stato presente e degli ingressi una funzione del solo stato presente pu essere codificata nella parola di stato

sta utilizzando come tool di debug un In Circuit Simulator non sono permessi hardware breakpoint un programma di monitor deve girare sul sistema target (DUT) necessario luso di una emulator probe che sostituisca la CPU

Il fenomeno della memoria implicita in VHDL... ( )a pu avvenire solamente allinterno di un process ( )b non pu essere usato per implementare un registro ( )c permette di sintetizzare circuiti sequenziali pi veloci dei corrispettivi combinatori

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Domande aperte (3 punti ciascuna)

1) Si consideri il seguente frammento di codice ASM per il dispositivo Microchip PIC18F452 e se ne descriva il comportamento e si dica se generer codice oggetto rilocabile o no: org 0 Delay1 res 1 Delay2 res 1 Start: CLRF PORTD CLRF TRISD CLRF Delay1 CLRF Delay2 MainLoop: BTG PORTD,RD1 Delay: DECFSZ Delay1,1 GOTO Delay DECFSZ Delay2,1 GOTO Delay GOTO MainLoop end 2) Si consideri il diagramma UML della figura seguente. Se ne descriva il tipo e se ne commenti il significato.

3)

Si descrivano le principali differenze tra dettagliando larchitettura interna di entrambe.

una

FPGA

una

CPLD,

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05/04/2012

Digital System for Signal Processing

Multiple choice questions (2 points each one)
The absolute resolution of a Q16.15 fractional notation in 2s complement (i.e. each word occupies 32 bits with 16 digits for integer part and sign and the remaining 15 for the fractional part)... ( )a it is equal to that of a single precision floating point number ( )b is less than that of a single precision floating point number ( )c is higher than that of a single precision floating point number A multiple precision number occupies 4 bytes. If the hexadecimal equivalent of these 4 bytes are A, B, C and D, then when this float is stored in memory in which of the following order do these bytes gets stored?... ( )a ABCD ( )b DCAB ( )c depends on big endian or little endian system organization A ( ( ( flas ROM memory: )a it has to be refreshed on a regular basis in order to store data )b generally speaking it is faster than a DRAM )c it exploits a floating gate transistor

An asynchronous serial link... ( )a needs a header ( )b can ensure very high transfer rate ( )c it must be a half duplex connection In a ( )a ( )b ( )c If we ( )a ( )b ( )c Mealy FSM: the output is a function of the present state and of the inputs the output is a function of the present state only the outputs can be encoded in the state bits are using an In Circuit Simulator hardware breakpoints are not allowed a monitor program musr reside on the target system (DUT) an emulator probe substituting the CPU is strictly needed

The implicit memory of VHDL... ( )a occurs only within a process ( )b cannot be used to infer a register ( )c allows to synthesize faster sequential circuit than combinatorial ones

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05/04/2012

Questions (3 points each one)

1) Consider the following snippet of ASM code for the Microchip PIC18F452 device; describe its behavior and tell if the output object code is relocatable or not:

org 0 Delay1 res 1 Delay2 res 1 Start: CLRF PORTD CLRF TRISD CLRF Delay1 CLRF Delay2 MainLoop: BTG PORTD,RD1 Delay: DECFSZ Delay1,1 GOTO Delay DECFSZ Delay2,1 GOTO Delay GOTO MainLoop end

2)

Consider the UML diagram of the figure below, commenting the type and describing the meaning..

3)

Describe main differences between an FPGA and a CPLD, detailing internal architecture of both of them.

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05/04/2012

Cognome __________________

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05/04/2012

Digital System for Signal Processing

ANSWERS

Multiple choice questions (2 points each one)

The absolute resolution of a Q16.15 fractional notation in 2s complement (i.e. each word occupies 32 bits with 16 digits for integer part and sign and the remaining 15 for the fractional part)... ( )a it is equal to that of a single precision floating point number (*)b is less than that of a single precision floating point number ( )c is higher than that of a single precision floating point number A multiple precision number occupies 4 bytes. If the hexadecimal equivalent of these 4 bytes are A, B, C and D, then when this float is stored in memory in which of the following order do these bytes gets stored?... ( )a ABCD ( )b DCAB (*)c depends on big endian or little endian system organization A flas ROM memory: ( )a it has to be refreshed on a regular basis in order to store data ( )b generally speaking it is faster than a DRAM (*)c it exploits a floating gate transistor An asynchronous serial link... (*)a needs a header ( )b can ensure very high transfer rate ( )c it must be a half duplex connection In a (*)a ( )b ( )c If we ( )a (*)b ( )c Mealy FSM: the output is a function of the present state and of the inputs the output is a function of the present state only the outputs can be encoded in the state bits are using an In Circuit Simulator hardware breakpoints are not allowed a monitor program must reside on the target system (DUT) an emulator probe substituting the CPU is strictly needed memory of VHDL... only within a process be used to infer a register to synthesize faster sequential circuit than combinatorial ones

The implicit (*)a occurs ( )b cannot ( )c allows

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05/04/2012

Questions (3 points each one)

1) Consider the following snippet of ASM code for the Microchip PIC18F452 device; describe its behavior and tell if the output object code is relocatable or not: org 0 Delay1 res 1 Delay2 res 1 Start: CLRF PORTD CLRF TRISD CLRF Delay1 CLRF Delay2 MainLoop: BTG PORTD,RD1 Delay: DECFSZ Delay1,1 GOTO Delay DECFSZ Delay2,1 GOTO Delay GOTO MainLoop end According to the MPASM Help (referenced above), the org directive allows the user to set the program origin for subsequent code at the address defined in expr (0 in this case). Thus, the code is not relocatable. The res directive reserves two memory bytes for variables Delay1 and Delay2. Then the actual code starts. The variables are set to 0; PORTD PIN 1 will be used and the whole port is cleared and set as an output port. Once the port is set up correctly, PIN 1 is toggled. Then, a delay loop is performed. The decfsz instruction subtracts the requested amount (second argument) from the file register (F) provided (first argument) and then checks the value of that register. If it is 0, the following instruction is ignored. This delay loop is actually a nested loop. Since Delay1 was 0 at the start, decrementing 1 from this 8 bit register turns it into 255. The goto instruction then moves the program flow back to the decfsz instruction. This continues until Delay1 reaches 1. When decfsz runs again, Delay1 becomes 0. As promised, the following goto instruction is skipped so the second decfsz instruction is run, subtracting 1 from Delay 2. Delay 2 was also 0 and becomes 255. The following goto instruction brings it back to the FIRST decfsz instruction, causing Delay1 to be decremented another 255 times before decrementing another 1 from Delay2. Once the delay code is finished (the second goto is skipped because Delay2 turns to 0), the goto MainLoop instruction is executed and the cycle begins again 2) Consider the UML diagram of the figure below, commenting the type and describing the meaning..

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This diagram shows an inheritance hierarchy a series of classes and their subclasses. Its for an imaginary application that must model different kinds of vehicles such as bicycles, motor bike and cars. All Vehicles have some common attributes (speed and colour) and common behaviour (turnLeft, turnRight). Bicycle and MotorVehicle are both kinds of Vehicle and are therefore shown to inherit from Vehicle. To put this another way, Vehicle is the superclass of both Bicycle and MotorVehicle In our model MotorVehicles have engines and license plates. Attributes have been added accordingly, along with some behaviour that allows us to examine those attributes MotorVehicles is the base class of both MotorBike and Car, therefore these classes not only inherit the speed and colour properties from Vehicle, but also the additional attributes and behaviour from MotorVehicle Both MotorBike and Car have additional attributes and behaviour which arespecific to those kinds of object. 3) Describe main differences between architecture of both of them. an FPGA and a CPLD, describing

CPLD - Complex Programmable Logic Device CPLDs are similar to SPLDs except that they are significantly higher capacity. A typical CPLD is the equivalent of two to 64 SPLDs. A CPLD typically contains from tens to a few hundred macrocells. A group of eight to 16 macrocells is typically grouped together into a larger function block. The macrocells within a function block are usually fully connected. If a device contains multiple function blocks, then the function blocks are further interconnected. Not all CPLDs are fully connected between function blocks-this is vendor and family specific. Less that 100% connection between function blocks means that there is a chance that the device will not route or may have problems keeping the same pinout between design revisions. In concept, CPLDs consist of multiple PAL-like logic blocks interconnected together via a programmable switch matrix. Typically, each logic block contains 4 to 16 macrocells, depending on the architecture.

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CPLDs provide a natural migration path for SPLD designers seeking higher density. CPLDs have a PAL-like architecture and generally four or more PALs comfortably fit into a CPLD. Most CPLDs support the SPLD development languages such as ABEL, CuPL, PALASM, etc. CPLDs are generally best for control-oriented designs, due in part to their fast pin-to-pin performance. The wide fan-in of their macrocells makes them well-suited to complex, high performance state machines. Some of the major variations between CPLD architectures include the number of product terms per macrocell, whether product terms from one macrocell can be borrowed or allocated to another macrocell, and whether the interconnect switch matrix is fully- or partially-populated. In some architectures, when the number of product terms required exceeds the number available in the macrocell, additional product terms are borrowed from an adjoining macrocell. This makes the CPLD device useful for a wider variety of applications. When borrowing product terms from an adjoining macrocell, that macrocell may no longer be useful. In some architectures, the macrocell still has some basic functionality. Borrowed product terms usually means increased propagation delay. Another difference in architectures is the number of connections within the switch matrix. A switch matrix supporting all possible connections is fully populated. A partially- populated switch supports most, but not all, connections. The number of connections within the switch matrix determines how easy a design will fit in a given device. With a fullypopulated switch matrix, a design will route even with a majority of the device resources used and with fixed I/O pin assignment. Generally, the delays within a fully populated switch matrix are fixed and predictable. A device with a partially-populated switch matrix may have problems routing complex designs. Also, it may be difficult to make design changes in these devices without using a different pinout. Routing to a fixed pinout is important. It is far easier to change the internals of a programmable logic device than it is to re-layout a circuit board. The delays within a partially-populated switch matrix are not fixed and less easily predicted, similar to most FPGA devices. Though a partially populated switch matrix has some potential limitations, it is less expensive to manufacture. CPLDs are manufactured using one of three process technologies-EPROM, EEPROM, or FLASH. EPROM-based CPLDs are usually one-time programmable (OTP) unless they are in an UV-erasable windowed package. A device programmer or the manufacturer or distributor programs an EPROM-based CPLD. Generally, CPLDs are CMOS and use non-volatile memory cells such as EPROM, EEPROM, or FLASH to define the functionality. Many of the most-recently introduced CPLD families use a EEPROM or FLASH and have been designed so that they can be programmed in-circuit (also called ISP for in-system programmable). FPGA - Field Programmable Gate Array FPGAs are a distinct from SPLDs and CPLDs and typically offer the highest logic capacity. An FPGA consists of an array of logic blocks, surrounded by programmable I/O blocks, and connected with programmable interconnect. A typical FPGA contains from 64 to tens of thousands of logic blocks and an even greater number of flip-flops. Most FPGAs do not provide 100% interconnect between logic blocks (to do so would be prohibitively expensive). Instead, sophisticated software places and routes the logic on the device much like a PCB autorouter would place and route components.

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A generic description of an FPGA is a programmable device with an internal array of logic blocks, surrounded by a ring of programmable input/output blocks, connected together via programmable interconnect. There are a wide variety of sub-architectures within this group. The secret to density and performance in these devices lies in the logic contained in their logic blocks and on the performance and efficiency of their routing architecture.

There are two primary classes of FPGA architectures: coarse-grained, and fine-grained.

Coarse-grained architectures consist of fairly large logic blocks, often containing two or more look-up tables and two or more flip-flops. In a majority of these architectures, a four-input look-up table (think of it as a 16x1 ROM) implements the actual logic. The larger logic block usually corresponds to improved performance. The other architecture type is called fine-grained. In these devices, there are a large number of relatively simple logic blocks. The logic block usually contains either a two-input logic function or a 4-to-1 multiplexer and a flip-flop. These devices are good at systolic functions and have some benefits for designs created by logic synthesis. Another difference in architectures is the underlying process technology used to manufacture the device. Currently, the highest-density FPGAs are built using static memory (SRAM) technology, similar to microprocessors. The other common process technology is called anti-fuse, which has benefits for more plentiful programmable interconnect. SRAM-based devices are inherently re-programmable, even in-system. However, they require some form of external configuration memory source. The configuration memory holds the program that defines how each of the logic blocks functions, which I/O blocks are inputs and outputs, and how the blocks are interconnected together. The FPGA either self-loads its configuration memory or an external processor downloads the memory into the FPGA. When self-loading, the FPGA addresses a standard byte-wide PROM-much like a processor addresses its boot PROM-or uses a special sequential-access serial PROM. When downloaded by a processor, the FPGA appears much like a standard microprocessor peripheral. The configuration time is typically less than 200 ms, depending on the device size and configuration method. In contrast, anti-fuse devices are one-time programmable (OTP). One programmed, they cannot be modified, but they also retain their program when the power is off. Anti-fuse devices are programmed in a device programmer either by the end user or by the factory or distributor. Some FPGAs have system-level features built-in like on-chip bussing, on-chip RAM for building small register files or FIFOs, and built-in JTAG boundary-scan support. Most FPGAs use either SRAM or anti-fuse CMOS technology. SRAM-based FPGAs are in-system programmable whereas anti-fuse-based FPGAs are one-time programmable.

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