DOC/LP/01/28.02.02 LP VL9252 LP Rev. No:00 Sub Code & Name: VL9252- LOW POWER VLSI DESIGN Date: 6.2.

.2013 Page 01 of 06 Unit : I Branch : M.E.Applied Electronics Year:I Sem:II UNIT I POWER DISSIPATION IN CMOS 9 Hierarchy of limits of power Sources of power consumption Physics of power dissipation in CMOS FET devices- Basic principle of low power design. Objective: The aim of this course is to familiarize the student about various power dissipation in CMOS devices. Session Topics to be covered No. 1. Basic principle of low power design 2. 3. 4. 5. 6. 7. 8. Sources of power consumption Physics of power dissipation in MOSFET devices Surface space charge region and the threshold voltage Depth of depletion region,Charge in the Inversion layer,Thickness Effects influencing Threshold voltage Power dissipation in CMOS-Short circuit dissipation,Dynamic dissipation Hierarchy of limits of power-Fundamental, Material, device, circuit, Systems level limits. Time 50 50 50 50 50 50 50 50 Ref 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 Teaching Method BB BB BB BB BB BB BB BB LESSON PLAN

DOC/LP/01/28.02.02 LP VL9252 LP Rev. No: 00 Sub Code & Name: VL9252- LOW POWER VLSI DESIGN Date: 6.2.2013 Page 02 of 06 Unit : II Branch : M.E.Applied Electronics Year:I Sem : II UNIT II POWER OPTIMIZATION 9 LESSON PLAN

Logical level power optimization Circuit level low power design Circuit techniques for reducing power consumption in adders and multipliers. Objective: The aim of this course is to optimize the power in adder and multiplier circuits. Session No. 9. 10. 11. 12. 13. 14. 15. 16. 17. Topics to be covered Logical level power optimization Combinational circuits Technology independent Optimization Sequential circuits Technology independent Optimization Logic optimization, Technology dependent optimization. Circuit level low power design, Logic style-Static and Dynamic logic, pass transistor logic, Single rail pass transistor logic and other logic styles. Latches and Flipflops Transistor sizing and ordering Circuit techniques for reducing power consumption in adders. Circuit techniques for reducing power consumption in multipliers. Time 50 50 50 50 50 50 50 50 50 Ref 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 Teaching Method BB BB BB BB BB BB BB BB BB

DOC/LP/01/28.02.02 LESSON PLAN Sub Code & Name: VL9252- LOW POWER VLSI DESIGN Unit : III Branch : M.E.Applied Electronics Year:I Sem : II UNIT III DESIGN OF LOW POWER CMOS CIRCUITS LP VL9252 LP Rev. No: 00 Date: 6.2.2013 Page 03 of 06 9

Computer Arithmetic techniques for low power systems Reducing power consumption in memories Low power clock, Interconnect and layout design Advanced techniques Special techniques Objective: The aim of this course is to design low power CMOS circuits.

Session No. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29.

Topics to be covered Computer Arithmetic techniques for low power systems Conventional Arithmetic and Low power design Logarithmic Number system-LNS & Power dissipation Residue Number system Reducing power consumption in memoriesStatic Random Access Memories,Low power SRAM circuit techniques Dynamic Random Access Memories,Sources of power dissipation in DRAMs. Low power DRAM circuit techniques. Low power clock design Interconnect delays Low power optimization for Layout design Advanced techniques Special techniques

Time 50 50 50 50 50 50 50 50 50 50 50 50

Ref 1,2,4,5, 6 1,2,4,5, 6 1,2,4,5, 6 1,2,4,5, 6 1,2,4,5, 6 1,2,4,5, 6 1,2,4,5, 6 1,2,4,5, 6 1,2,4,5, 6 1,2,4,5, 6 1,2,4,5 ,6 1,2

Teaching Method BB BB BB BB BB BB BB BB BB BB BB BB

DOC/LP/01/28.02.02 LP VL9252 LESSON PLAN LP Rev. No: 00 Date: 6.2.2013 Sub Code & Name: VL9252- LOW POWER VLSI DESIGN Page 04 of 06 Unit : III Branch : M.E.Applied Electronics (MAE) Year:I Sem : II UNIT IV POWER ESTIMATION 9 Power estimation techniques Logic level power estimation Simulation power analysis-Probabilistic power analysis. Objective: The aim of this course is to familiarize the students about various power estimation techniques.

Session Topics to be covered No. 30. Logic level power estimation-Sources of power dissipation 31. Behavior of digital signal-Signal correlation, Structural dependencies, 32. Sequential correlations, Gate delay model. 33. Classification of Power estimation Methodologies 34. Simulation based Power Estimation-Monte Carlo power estimation, 35. Sampling Techniques, Vector Compaction 36. 37. 38. Probabilistic methods-Combinational circuits, Real-Delay Gate Power Estimation Symbolic simulation for consumption Estimation for sequential cicuits. CAT-I

Time 50 50 50 50 50 50 50 50 50 180

Ref 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2

Teaching Method BB BB BB BB BB BB BB BB BB -

DOC/LP/01/28.02.02 LESSON PLAN Sub Code & Name: VL9252- LOW POWER VLSI DESIGN Unit : III Branch : M.E.Applied Electronics (MAE) Year:I Sem : II LP VL9252 LP Rev. No: 00 Date: 6.2.2013 Page 05 of 06

UNIT V SYNTHESIS AND SOFTWARE DESIGN FOR LOW POWER 9 Synthesis for low power Behavioral level transforms- Software design for low power Objective: The aim of this course is to familiarize the students about synthesis tool and

software design for reducing area and power. Session Topics to be covered No. 39. Synthesis for low power-Behavioral level transforms 40. Algorithm level transforms for low power 41. Power constrained Least-Squares Optimization for Adaptive and Nonadaptive Filters 42. Circuit Activity driven Architectural Transformations 43. Sources of software power dissipation 44. Software power estimation-Gate level and Architecture level power estimation 45. Bus switching activity, Instruction level power analysis 46. Software power optimization-Algorithm Transformation s to Match Computational resources 47. Minimizing Memory access codes 48. Instruction Selection and ordering CAT-II. Time 50 50 50 50 50 50 50 50 50 50 40 Ref 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 Teaching Method BB BB BB BB BB BB BB BB BB BB -

DOC/LP/01/28.02.02 LESSON PLAN Sub Code & Name: VL9252- LOW POWER VLSI DESIGN Unit : III Branch : M.E.Applied Electronics (MAE) Year:I Sem : II Course Delivery Plan: 1 2 3 4 Week I I I I II II II II UNIT LP VL9252 LP Rev. No: 00 Date: 6.2.2013 Page 06 of 06

5 I II

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9 I II

10 I II 4

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TEST

T1 T2

T3

T4

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T8 CAT-I

T9

T10 CAT-II

Note: T1,,T10: Weekly Test ; CAT: Continuous Assessment Test

TEXT BOOKS:
1. K.Roy and S.C. Prasad , LOW POWER CMOS VLSI circuit design, Wiley,2000 2. Dimitrios Soudris, Chirstian Pignet, Costas Goutis, DESIGNING CMOS CIRCUITS FOR LOW POWER, Kluwer,2002 3. J.B. Kuo and J.H Lou, Low voltage CMOS VLSI Circuits, Wiley 1999. 4. A.P.Chandrakasan and R.W. Broadersen, Low power digital CMOS design, Kluwer,1995. 5. Gary Yeap, Practical low power digital VLSI design, Kluwer,1998. 6. Abdellatif Bellaouar,Mohamed.I. Elmasry, Low power digital VLSI design,s Kluwer,1995. 7. James B. Kuo, Shin chia Lin, Low voltage SOI CMOS VLSI Devices and Circuits.John Wiley and sons, inc 2001

Prepared by Signature Name Designation Date B.Sarala Assistant Professor 06/02/2013

Approved by Dr.S.Ganesh Vaidyanathan HOD, Department of EC 06/02/2013