Generation of PWM signal using Microcontrollers and DPS

Modern power electronics controllers are rapidly moving toward digital implementation. Typical solutions consist of microcontrollers or DSPs. In addition, coprocessors, such as the ADMC200/201 from Analog Devices, are available that are specifically designed to support inverter control. Most of the processors, such as the 68HC12B32 from Motorola, that are commonly used to control power electronics have built-in hardware support for PWM generation. Figure 7.17 shows the basic principle of their digital PWM generation. For clarity, the circuit shown in Fig. 7.17 has only 4-bit resolution for the duty cycle of the generated PWM signals, resulting in only 16 discrete duty cycles. In actual applications, 8 to 12 bits of resolution is typical. In Fig. 7.17, a digital counter (74163) counts from zero to its maximum value and repeats the cycle afterward. The count is continuously compared with a digital value representing the duty cycle using a hardware comparator (7485). The PWM signal is available on the output of the comparator. Figure 7.18 shows the simulation results from the example circuit shown in Fig. 7.17. The duty cycle in this example is 3/16. If more than one channel is present, the PWM signals can be left, right, or center aligned. To be center aligned, updown counters are used, which count up to their maximum count and then back to zero before starting the next cycle. The maximum count (2bits-1) is determined by the number of stages (bits) the digital counter has.

FIGURE 7.17 Principle of digital PWM signal generation. In a digital PWM modulator each counter has an associated period register. The content of this register determines the maximum count at which the counter resets. If this number is less than the maximum count (2bits-1)

FIGURE 7.18 Simulation results from the circuit shown in Fig. 7.17. The repetition (switching) frequency is increased and the resolution of the duty cycle is decreased for a given clock speed. It is often important to make the correct trade-off between the switching frequency and the resolution. The advantage of hardware support for PWM generation is that the processor typically only needs to access any registers if the duty cycle is to be changed, since the period is typically only initialized once upon program start-up. It should also be mentioned that the duty cycle registers are typically doublebuffered, meaning that an update of a duty cycle does

not need to be synchronized with the current state of the counter. In double-buffered systems, the new duty cycle will only be chosen once the previous period is completed to avoid truncated PWM signals. If necessary, a software override can disable this feature.