Chapter # 1

Historical Evolutions of Microprocessors

The complete Microprocessor Family Features of 80286 Features of 80386 Features of 80486 Pentium Family Pentium Features

The complete Microprocessor Family

Features of 80286
16-bit microprocessor
16 MB Address Space (1 GB Virtual Memory) 80286 4 /8/16 MHz Separate pins for Address & Data Lines BU, AU, IU, EU Real Mode and Protected Virtual Address Mode Compatible with earlier versions

Features of 80386
32-bit microprocessor 4 GB Address Space (64 TB Virtual Memory) Pipelined Architecture (3-4 million Inst/sec) Switch OS Different Data Types (b/ B/ W/ DW/ PW/ QW/ TB) Real Mode, Protected mode and Virtual 8086 Mode Compatible with earlier versions

Features of 80486
32-bit microprocessor 4 GB Address Space (64 TB Virtual Memory) 80486 25/33/50/66/100 MHz 80486DX / 80486SX On-chip Memory Mgmt and Cache Memory Units Pipelined Architecture (5-stage)

Real Mode, Protected mode and Virtual 8086 Mode

Features of 80486

(contd)

Built-in Parity Generator/Checker Unit

Burst mode memory read and write

New Instructions (XADD, CMPXCHG, BSWAP) Supports Built-in-self-test (BIST) TR3-TR5 Compatible with earlier versions

The complete Microprocessor Family

Chip 4004 8008 8080 8085 8086/8088 80186/80188 80286 80386-SX 80386-DX 80486-SX 80486-DX 1980-90 1970-80 Year Data Bus Address Bus 4 8 16 16 20 20 24 24 32 32 32

Pentium

1993

4 8 8 8 16/8 16/8 16 16 32 32 32 64

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The Pentium Family

Processor Memory L1 Cache Data-Code 8K-8K 8K-8K 16K-16K 16K-16K 16K-16K 16K-16K 16K-16K L2 Cache Bus Transfer Speed (MHz) 60-66 60-66 100 100 100 66 100 Pentium Pentium Pro Pentium II Pentium II Xeon Pentium III (1GHz) Pentium III (1GHz) Celeron Pentium IV (1.3,1.4,1.5GHz) 4 GB 64 GB 64 GB 64 GB 64 GB 64 GB 64 GB 256K 512K 512K 256K 256K 256K

Pentium Features
Wider Data bus width (64-bits) Faster Floating Point Unit (10 times faster) Improved Cache Structure Separate data and code cache Dedicated TLB

Dual Integer Processor (2 Instn/clock)

Branch Prediction Logic (2 pre-fetch buffers)

Pentium Features (contd)

Data Integrity and Error Detection Functional Redundancy Checking (2nd Processor Checker ) Superscalar Architecture Pentium-Pro (5 Instn/Execution) 16K L1 and 256K L2 cache Includes Error-Correction Circuitry 4 additional address lines (64 GB memory space)

Comparison of 16,32 and 64 bit Microprocessors

Comparison of 16,32 and 64 bit Microprocessors (contd.)

Comparison of 16,32 and 64 bit Microprocessors (contd.)

Comparison of 16,32 and 64 bit Microprocessors (contd.)

Pentium Architecture

RISC Concepts
CISC ?????
Complex Instructions and Addressing modes Performance bottleneck Multiple Clock Cycles required

RISC ?????
Smaller Instruction- set Fewer Instructions and simpler Addressing modes Ex. Video games & laser printer

Pentium RISC Features

Goals of RISC Machine

Reduce access to main memory Keep Addressing modes and Instructions simple Make good use of Registers

Pipeline Everything
Utilize the compiler extensively

1. Reduce Access to Main Memory

10ns vs 60ns Cache

2.

Keep Addressing modes and Instructions Simple

Programmers use small subset Reduce complexity of Instruction decoder, addressing logic & execution unit Looks like CISC machine

3. Make good use of Registers

Large set of registers 16-bit, 32-bit, 80-bit

4.

Pipeline everything

2 pipelines
Instruction Pipeline Bus Cycle Pipeline Branch Prediction

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5. Utilize Compiler Extensively

Optimization on Assembly Language Substitute an Instruction

Pentium contains both CISC and RISC characteristics

Pentium Real Mode

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Pentium Real Mode

Pentium Real Mode

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Pentium Real Mode

Pentium Real Mode : Address Generation

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Pentium Real Mode

Pentium Real Mode: Interrupts & Exception

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Pentium Real Mode: Interrupts & Exception

Pentium Real Mode

Supports Architecture of 8086 but can access 32-bit registers Programming Model (Register Set : 8+8 = 16) CR0 (Control Register 0) : used to enter in Protected Mode (PE) 1 MB memory and 64KB I/O Space

Paging mechanism is not supported Linear addresses are Physical addresses

(21-bit address allowed) From 000 H 3FF H (400 memory locations) are dedicated for IDT (Interrupt Descriptor Table or Pointer to ISR) IDTR Re-locatable, 48-bit (32-base & 16-limit)

Interrupts and Exceptions

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Pentium Superscalar Architecture

Superscalar Machine: Processor capable of parallel instruction execution of multiple instructions are known as superscalar machines Capable of 2 integer or 2 floating point instructions simultaneously Possible due to U & V pipeline Restrictions for Pairing Instructions Compilers role for ordering instructions during code generation

Pentium Superscalar Architecture

Floating point Instructions Pairing Rule

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Instruction Pairing Rules

1. Both instructions must be Simple Instructions Execute in 1 clock (hardwired) MOV R/R, INC, DEC, Near conditional Jumps (JZ, JNZ) Restriction to conditional instructions: it must be the 2nd instruction in the pair 2. 3. 4. 5. Shifts or Rotates can only pair in the U pipe ADC and SBB can only pair in the U pipe JMP, CALL and JCC can only pair in the V pipe Neither instruction can contain both a displacement and an immediate operand. (Ex: MOV [SI+2], 0010H) 6. Prefixed instructions can only pair in the U pipe

Instruction Pairing Rules

7. The U pipe instruction must be only 1 byte in length or it will not pair until 2nd time it executes from the cache 8. There should NOT be any DATA DEPENDANCY Read-after-write dependency Write-after-write dependency

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Pipelining
Is a valid technique for improving Instruction Execution Rate Pipeline Stages of U & V Pipeline

Pipelining

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Pipelining
U pipeline can execute ANY instruction V pipeline executes only SIMPLE instructions. Under ideal conditions 2 INTEGER instructions my complete execution EVERY clock cycle

Branch Prediction
The incorrect instructions that loaded wrongly, must be discarded. This is called FLUSHING of the pipeline. No work is done when the pipeline stages are reloaded. These disturbances in the pipelined instruction execution are called BUBBLES.

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Branch Prediction : Dynamic

BTB ( Branch Target Buffer )
a special cache that stores the instruction and target addresses of any branch instruction that have been encountered in the Instruction Stream.

BTB stores history bits. These are Initially set to 11 when a new target address is placed into the BTB. If a new branch instruction is encountered, the prediction is not taken. (no target address in the BTB / HB = 00)

Dynamic Branch Prediction

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Branch Prediction : Dynamic

Two 32-Byte Pre-fetch Buffers Incorrect predictions or correct predictions with wrong target address cause the pipelines to be flushed

Pentium sets the history bits to 11 for a new entry.

The Instruction and Data Cache

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The Instruction and Data Cache

Cache Organization

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The Instruction and Data Cache in PENTIUM

The Instruction and Data Cache

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The Instruction and Data Cache

Linear to Physical Address Generation

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FPU: Floating Point Unit

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FPU: Floating Point Unit Pipeline Stages

FPU: Pipeline Stages

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FPU Register File

FPU Data Types

Integer (Signed and Unsigned) Byte Integer Word Integer Short Integer (Double Word) Long Integer (Quad Word) Packed BCD (10 / 9 Bytes -18) Real Numbers Short Real (Single-precision) Long Real (Double-precision) Extended Real (Extended-precision)

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Integer formats in the FPU

Real, Long Real, Extended Real Formats in the FPU

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