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D5901
14.0±0.3
z Battery charging circuit.
10.0±0.3
D5901
z General purpose operational a mplifier is
contained. 44 12
1.2
1 11 0.2±0.1
z Thermal shutdown circuit.
2.15±0.1
z QFP44 package.
0.05
z Load drive voltage can be processed by PWM control th rough an external co mponent.
z Excellent gain can be obtained by a voltage feedback circuit.
z Mute function is disabled for ch1, ch2 and ch3/ch4 respectively.
<DC/DC converter control circuit>
z Starter and power off function.
z Soft-start function and short-circuit protection function.
z Self-advancing oscillation and clock synchronization are available.
<Reset circuit>
z Reset voltag e is in terlocked with the set voltage of DC/DC converter.
z Inversion output termi nal for reset output is available.
<Reduced voltage detection circuit>
z Battery charger and dry battery allow to switch “E mp ty” detection level.
<Battery charging circuit>
z Constant cu rrent battery charging system allows to vary current value throug h
resistance.
z It is separated from any other blocks and it can be operated independently.
z A charging power transistor is co ntained.
z Independent thermal shutdown circuit is contained.
MUTE 1
EMP 35 21 MUTE2
HVc c 36 20 IN2
BTL BTL BTL BTL
MUTE 34
PSW 37 TSD - 19 MUTE34
Maximum +
De tec tion
CLK
CLK 38 - 18 IN4
+
START 39 -
+ - +
17 IN3
Powe r off
sta rter
-
OFF 40 + 16 VREF
Tria ngula r
wa ve
CHGVc c 41 TSD
Pre -drive power supply
15 VSYS2
Over voltage
SEL 42 14 OP+
+
-
+-
+
Control circuit
-
P ower supply
+
PREGND 43 13 OPOUT
B attery power supply
-
+- +
PWMFIL 44 12 VSYS1
+-
1 2 3 4 5 6 7 8 9 10 11
BSEN BATT RESET DEAD SW EO EI SPRT CT NC OP-
TERMINAL DESCRIPTION
16.5K
71K
Battery voltage
1 BSEN
monitor terminal 10K 19K
11.5K
90K
Cassette detection
3 RESET
output terminal 3
VSYS1
18K
Dead-ti me setting
4 DEAD
terminal 4
65K
50K
BATT
BATT
Booster transistor
5 SW
drive termi n al 5
250
9K
VSYS1
VSYS1
35K
Error a mp lifier input
7 EI 7
terminal
21K
VSYS1
VSYS1
Short-circuit protection
8 SPRT
setting terminal 8
220K
VSYS1 BATT
2K
20K
10 NC
VSYS1 VSYS1
Operational amplifi er
11 OP-
negative input terminal
14 11
Operational amplifi er
14 OP+ positive input terminal
Operational amplifi er
13 OP O U T
output terminal 13
16
×4
15K
Reference power supply
30K
16 VREF
input termi n al
75K
CHGVc c
BATT
BATT
35
“E mp ty” detection
35 EMP
output terminal
BATT BATT
37
PWM transistor drive
37 PSW
terminal
54
VSYS1
2K
38
External clock
38 CLK synchronization input
terminal
51K
100K
BATT
BATT
390K
VSYS1
VSYS1
180K
Boost DC/DC converter
40 OFF
OFF terminal 40
30K
220K
VSYS1
PWM phase
44 PWMFIL 44
co mpensation terminal
2K
ELECTRIC CHARACTERISTICS
(Unless specified particularly: Ta=2 5°C, BATT=2.4V V S Y S 1 =V S Y S 2 =3.2 V, V R E F =1.6V,
CHGVcc=0V, f C L K =88.2kHz)
ELECTRICAL CHARACTERISTICS
(Unless specified particularly: Ta=2 5°C, BATT=2.4V V S Y S 1 =V S Y S 2 =3.2 V, V R E F =1.6V,
CHGVcc=0V, f C L K =88.2kHz)
(Short-circuit protection)
S P RT p i n v o l t a g e ( n o r m a l ) VSPR EI=1.3V 0 0.1 V
S P RT p i n c u r r e n t 1 E O = H ISPR1 EI=0.7V 6 10 16 µA
S P RT p i n c u r r e n t 2 O F F = L ISPR2 E I = 1 . 3 V, O F F = 0 V 12 20 32 µA
S P RT p i n c u r r e n t 3 ( o v e r- v o l t a g e ) ISPR3 E I = 1 . 3 V, B AT T = 9 . 5 V 12 20 32 µA
S P RT p i n i m p e d a n c e RSPR 175 220 265 kΩ
S P RT p i n t h r e s h o l d v o l t a g e VSPTH E I = 0 . 7 V, C T = 0 V 1.1 1.2 1.3 V
O v e r- v o l t a g e p r o t e c t i o n d e t e c t VHVPR BSEN pin voltage 8.0 8.4 9.0 V
ELECTRICAL CHARACTERISTICS
(Unless specified particularly: Ta=2 5°C, BATT=2.4V V S Y S 1 =V S Y S 2 =3.2 V, V R E F =1.6V,
CHGVcc=0V, f C L K =88.2kHz)
(Interface section)
VSYS1
OFF pin threshold voltage VOFFH EI=1.3V V
-2.0
OFF pin bias current IOFF OFF=0V 75 95 11 5 µA
S TA RT pin ON threshold B AT T
voltage V S TA R T 1 V S Y S 1 = V S Y S 2 = 0 V, C T = 2 V -1.0 V
S TA RT p i n O F F B AT T
V S TA R T 2 V S Y S 1 = V S Y S 2 = 0 V, C T = 2 V -0.3 V
threshold voltage
S TA RT p i n b i a s c u r r e n t I S TA R T S TA RT = 0 V 13 16 19 µA
CLK pin threshold
VCLKTHH 2.0 V
Vo l t a g e H
CLK pin threshold
VCLKTHL 0.8 V
Vo l t a g e L
CLK pin bias current ICLK CLK=3.2V 10 µA
(Starter circuit section)
V S Y S 1 = V S Y S 2 = 0 V → 3 . 2 V,
St a r t e r s w i t c h i n g v o l t a g e VSTNH 2.3 2.5 2.7 V
S TA RT = 0 V
St a r t e r switching hysteresis
VSNHS S TA RT = 0 V 130 200 300 mV
width
D i s c h a rg e r e l e a s e v o l t a g e VDIS 1.63 1.83 2.03 V
ELECTRICAL CHARACTERISTICS
(Unless specified particularly: Ta=2 5°C, BATT=2.4V V S Y S 1 =V S Y S 2 =3.2 V, V R E F =1.6V,
CHGVcc=0V, f C L K =88.2kHz)
APPLICATION CIRCUIT
Tra ve rse Spindle Foc us Tric king
1.0K
M M
33 32 31 30 29 28 27 26 25 24 23
BRAKE 1
34 22
MUTE 1
35 21
33µ
36 20
0.1uF
MUTE 34
37 TSD - 19
47 Maximum +
De tec tion
CLK
38 - 18
+
39 -
+ - +
17
Powe r off
0.1uF
sta rter
100K -
40 + 16
Tria ngula r
wa ve
41 TSD
Pre -drive power supply
15
Over voltage
42 14
+
-
+-
+ - Control circuit
P ower supply +
43 13
B attery power supply
-
--+
44 12
+-
2200pF 100K
10pF
1 2 3 4 5 6 7 8 9 10 11
Filter
0.1uF
0.1uF
470pF
6.2K
0.022uF
DC/DC
Converte r
a pplica tion
47uF
100uF
OPERATING EXPLANATION
z H-bridge driver
(Gain setting)
Driver input resistance is 11 kΩ(typ.) for CH1,CH3 and CH4 and 7.5 kΩ(typ.)for CH2.
Calculate driver gain with the under-mentioned expression and set it.
CH1, CH3,CH4 Gv=20log|55k/(11k +R)| (dB)
CH2 Gv=20log|110k/(7.5k +R)| (dB)
R: External resistance
The power supply of drive output stage is HVcc termin al (36 pin) and th at of pre-drive
circuit is VSYS2 terminal (15 pin). Attach by-pass capacitor (approximately 0.1µF) to the
legs of this IC between the po wer supplies.
(Mute function)
Brake function and mu te function are assigned to CH1 and other channels of the four
channels respectiv ely.
When BRAKE1 terminal (23 pin) has been set to “H”, the output of CH1 becomes “L”
for both pin 31 and pin 32 and enters a Brake mode.
When MUTE2 terminal (21 pin) has been set to “H” , the output of CH2 is mu ted.
When MUTE34 terminal (19 pin)has been set to “L” th e output of CH3 and that of CH4
are muted si mu ltaneously.
(V R E F drop mute)
When the voltage impressed to V R E F terminal (16 pin) is 1.0V(typ .) or less, impedance
of driver output becomes “h igh”.
(Thermal shutdown)
When th e ch ip temp era ture has been 150°C(typ.) the ou tput current is cut.
When th e chip tempe rature has dropped to 120°C(typ.) the ou tput current begins to
flow.
z PWM power supply driv e un it
This unit detects a ma ximu m output level of drivers of four chan nels and performs the
PWM supply of load drive po wer supply (36 pin). This unit uses PNP transistor , coil,
Schottky diode and capacito r as ex ternal component.
33µ
10pF
0.1uF
47uF
100K 47
2200pF
44 37 36
z DC/DC converter
(Output voltage)
Booster circuit of 3.2V(typ.) can be config ured with external co mponents. This voltage
varies depending on addition of external components. How to set the voltage is as
follows:
V S Y S 1 =1.2×{[(R1*R3)/(R1+R3)+(R2*R4)/(R2+R4)]/(R2* R4/(R2 +R4)}
R1=External re sistan
R2=External re sistan
12 R3=35KΩ
R4=21KΩ
R1 R3
R2 R4
1.2V
(Power-off operation)
SPRT terminal (8 pin) is charged by setting OFF terminal (40 pin) to “L”. Then,
switching of SW termi n al (5 pin) is terminated when the voltage of the SPRT terminal
(8 pin) has reached 1.2V(typ.). Time to disable switching depends on a capacitor of the
SPRT terminal (8 pin) and it can be calcu lated by the und er-mentioned expression:
t=C S P RT ×( V T H /I O F F ) (sec) (V T H =1.2V, I O F F =20µA)
(Over-voltage protection op eration)
When the voltage impressed to BSEN terminal (1 pin) has been 8.4V(typ .), SPRT
terminal (8 pin)is charged. Then, switching of SW termi n al (5 pin)is terminated when
the voltage of the SPRT terminal (8 pin) has reached 1.2V(typ.) Ti me to disable
switching depend s on a capacitor of the SPRT terminal (8 pin) an d it can be calculated
by the under-mentioned expression:
t=C S P RT ×( V T H /I H V ) (s ec) (V T H =1.2V, I H V =20 µA )
z “E mpty” detector unit
When the voltage impressed to BSEN termina l (1 pin) has been the detecting voltage is
2.2V or less, EMP terminal (35 pin) varies fro m “H” to “L” (open collector output).
Hysteresis of 50mV (t yp.) set to the detecting voltage to preven t th e output ch attering.
The detecting vo ltage varies depending on SEL terminal (42 pin) as follows:
SEL pin Detect voltage Return voltage
“L” 2.2V(typ.) 2.25V(typ.)
High-Z 1.8V(typ .) 1.85V(typ .)
z Reset circuit
Upon 90% (typ .) of DC/DC converter output voltage, RESET terminal (3 pin) varies
fro m “L” to “H” and AMUTE terminal (34 pin) changes fro m “H” to “L”. Hyste resis of
50mV (typ.) set to th e reset voltage to prevent the output chattering.
z Charging circuit
The power supply of the charging unit is CHGVcc terminal (41 pin) and it is
independent of any other circuits. Charging cu rrent is set by resistan ce between RCHG
ter minal (33 pin) and GND. The charging cu rrent takes constant current through SEL
terminal (42 pin)
This circuit has a private thermal shutdown circuit. When the chip temp e rature has
been 150°C (typ .), the charging current is cu t. When the chip temperature has dropped
to 120