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EE290C – Spring 2011

Lecture 3: Basic Transmitters and Receivers

EE290C – Spring 2011 Lecture 3: Basic Transmitters and Receivers Elad Alon Dept. of EECS

Elad Alon Dept. of EECS

Administrative

Elad will be out of town this Thurs.

Make-up lecture will be held on Mon. 1-31 1:30-3:00pm in 127 Dwinelle

Office hours on Thurs. cancelled – available over email

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Plain Old Inverters – Why Not?

Plain Old Inverters – Why Not? EE290C Lecture 3 3

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Outline

Signaling Basics

Single-ended vs. differential

“Current-mode” vs. “Voltage-mode” signaling

Termination

TX Circuit Design

Z control

CML, VM drivers

Power vs. swing

Serialization options

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RX Circuit Design

Comparator review

Deserialization options

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Single-Ended Signaling

rcvr d xmtr in ref d out C C d r
rcvr
d
xmtr
in
ref
d
out
C
C d
r

RX: comparing against a shared reference

Reference may be implicit (i.e., ground/supply)

Mismatch between shared and individual lines

TX: generates large variations on power supply

SSO – simultaneous switching outputs

No XTALK immunity

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So Why Even Mention This?

So Why Even Mention This? EE290C Lecture 3 6

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Classic Debate

“Differential must be twice as fast as single- ended in order to win”

Reality more complicated

E.g., power supply to signaling pin ratio higher in S.E.

Short “answer”

Differential a lot easier to build and get right the first time

Can make S.E. work – but often a lot more painful

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“Voltage-Mode” vs. ”Current-Mode”

“Voltage-Mode” vs. ”Current-Mode” • Transmission line has both voltage and current… • Terminology
“Voltage-Mode” vs. ”Current-Mode” • Transmission line has both voltage and current… • Terminology

Transmission line has both voltage and current…

Terminology unfortunately heavily overloaded

Whether or not Zo of driver is high

How Zo of driver is set

What sets output swing

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“Voltage-Mode” vs. ”Current-Mode” EE290C Lecture 3 9 Another View “Low Impedance” “High Impedance”
“Voltage-Mode” vs. ”Current-Mode”
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Another View
“Low Impedance”
“High Impedance”
V S
+
+
-
d
ref
-
V
S /2
shared
+
+
-
d
-
d
RX opposite of TX
Signal integrity implications?
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Single
Differential
Ended

Why Terminate?

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External vs. Internal Termination

 
 
 

Internal: makes package L, pad C part of T-line

External: chip/package become a stub

If want on-die term need to control its value…

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Untrimmed Poly Termination

Main issue is variation: +/-20% at one temperature

But

It’s relatively linear

ESD robust

Low parasitics…

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Ri, Ci, and Pad Complexity 1.00 R s L 0.80 C L I 0.60 G
Ri, Ci, and Pad Complexity
1.00
R s
L
0.80
C L I
0.60
G d
C I
0.40
R I
"low_CL"
0.20
"1_drop"
"2_drop"
"4_drop"
"8_drop"
Ci, Ri
0.00
1e+008
1e+009
typically dominate
Freq (Hz)
Normalized amplitude

LPF at pad can dominate overall channel

Example: 500fF ESD, 500fF driver, 500fF wire

Bandwidth ~4GHz with double-terminated link

Even worse in busses (or if add big series R)…

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Active Terminations

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AC vs. DC Termination

With diff. can terminate to complement

High Z lower power

See more shortly

TX sets common-mode

Can be inconvenient

May need wide CM range

AC-coupled + AC-term

Places some requirements on data though

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Rx R AC V CM
Rx
R AC
V CM
R CM R Rx AC R CM
R
CM
R
Rx
AC
R
CM

V CM

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TX Design: Series vs. Parallel Termination

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Alphabet Soup

LVDS, CML

GTL, GTL+, RSL, …

VM, CM

HCM, LCM

All same basic principles

Look at two representative circuits to understand some of the more fundamental tradeoffs

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CML TX + RX Term V D D V DD 50Ω 50Ω Zo = 50Ω
CML
TX + RX Term
V D D
V DD
50Ω
50Ω
Zo = 50Ω
Tx
Rx
Zo = 50Ω
I o = - 21mA
Double-terminated
on-chip
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Side
Note: Pre-Driver
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CML Power Consumption

 

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Differential VM TX + RX

 

Main motivation: can reduce power for same swing/supply

 

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Simplified Model And Power

 

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Bad News: Extra Complexity

 

Driver impedance (termination) now set totally by devices

Some sort of impedance control is critical

“High-swing” driver:

 

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Low-Swing VM Driver

Old standards often required large swings (>1V diff. p2p)

More modern designs use much lower swings (~200-400mV diff. p2p) to save power

Low-swing VM driver:

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Impedance Control

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Another Approach

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Serialization: Input vs. Output

On-chip clocks often slower than off-chip data- rates

Need to take a set of parallel on-chip data and serialize it

Can serialize either at input of TX or at final output

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Serialization: Input vs. Output

Input ser. requires on-chip circuitry to run at full line rate

May lead to high power consumption

In older technologies (0.35um) was hard to support high- freq. clocks

D0 D1 D2 data(ck0) clock(ck3) R TERM R TERM out_b ck3 out x 8
D0
D1
D2
data(ck0)
clock(ck3)
R TERM
R TERM
out_b
ck3
out
x 8

Output ser. noved burden at pad

At the time was highest BW

Limit in both designs: edge rate

Either for the clock or for the data

d0

d0

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Basic TX Final Notes

Usually need many peripheral controls

Zo, edge-rate, etc.

Keep tuning out of the high-speed signal path

P(High-speed, low res. + low-speed, high-res.) << P(high-speed, high-res.)

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Basic TX Final Notes

 

Lots of research focused on reduced signaling power

 

I.e., power spent by actual final driver

Watch out for “overhead” (pre-drivers)

 
 

Especially with emerging low-swing designs, overhead can actually dominate

 

P sig (400mV diff. p2p):

P digital (100 min. sized inverters @ 10GHz):

More on this later

 
 

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Basic RX

 

Simplest: RX is just a comparator @ f bit

 
 

(Clocking later)

Key things to watch out for:

 
 

High sensitivity (low noise, low offset/hysteresis)

Common-mode input range

 

Supply/common-mode rejection

Max. clock rate

Power consumption

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Typical Design

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StrongArm Review

 

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Higher Speeds

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