GDT-1668

CD-MP3 Audio Decoder

1. Introduction
1.1 Overview
GDT-1668 is a single-chip CD-MP3
audio decoder. Tailored for the CD audio
system, the GDT-1688 integrates all the
1.2 Features
z Single-chip MPEG1 layer 3
decoder (ISO 11172-3 compliance)
z Extension to MPEG low bit rates

necessary hardware and firmware (MPEG2 and MPEG2.5)

including Clock Manager, CD-DSP z Digital volume control
2
interface controller, I C bus controller, z Stereo/mono channel select
DSP core, and audio DAC interface z Sampling frequency from 8KHZ
controller to minimize the overall up to 48KHZ
system cost and development time. z Bit rate from 8k bits per second up
Operating at 2.5 volts, the GDT-1668 to 320k bits per second
consumes less power and is especially z CRC error concealment

suitable for CD portable audio z Embedded clock synthesizer

equipment whose battery life is critical. z Ancillary data and header
The GDT-1688 is available in a 48-Lead information extracted and
LQFP package. accessible via I2C bus
z Control/status information

accessible via I2C bus

z Built-in CD-DSP interface
z Programmable audio DAC
interface
z Over-sampling clock for audio

DAC generated and controlled

internally
z External audio clock supported

for sampling rate control

z Operating at 2.5 volts to reduce

power consumption
z Sleep/Resume power management

control
z 8 general purpose programmable

I/O pins

1
 GDT-1668
CD-MP3 Audio Decoder

1.3 Block Diagram

OSCI
SDATAO
OSCO Clock DAC BITCKO
EXTCLK Management I/F LRCKO
RESUME
OVSMPCLK

DSP
Core

CDINTREQ Control GPIO0~7

CDDSPREQ CD-DSP & SCL
SDATAI I/F Status
SDA
SCLKI Registers

2
 GDT-1668
CD-MP3 Audio Decoder

2. Pin Description

2.1 Pin Diagram

GPIO7
GPIO6

AVDD
GPIO4

GPIO5
GPIO3

OSCO
AVSS

OSCI
VDD

N.C.

VSS
27
35

25
33
36

34

29

26
32

31

30

28
VSS 37 24 VDD
GPIO2 38 23 TEST4
GPIO1 39 22 TEST3

GPIO0 40 21 TEST2

SA5 41 20 HRESB

SA4
N.C.
42
43
GDT-1668 19
18
RESUME

N.C.

SA3 44 17 CDDSPREQ

SA2 45 16 SCLKI
SA1 46 15 SDATAI

SA0 47 14 EXTCLK
VDD 48 13 VSS
12
11
10
2

7
1

9
6
C3ERR

N.C.
TEST1

BITCKO
SDATAO

LRCKO

VDD
CDINTREQ

OVSMPCLK
SCL

SDA
VSS

3
 GDT-1668
CD-MP3 Audio Decoder

2.2 Pin-out Assignment

Pin # Pin Name Pin Type Description

1 VSS GND Digital Ground
2 TEST1 I Test Pin #1 (tied to VSS)
3 C3ERR I C3 Error from CD-DSP (active high)
4 CDINTREQ O Interrupt Request to CD-DSP
5 SCL I/O I2C Clock Line
6 N.C.
7 SDA I/O I2C Data Line
8 SDATAO O Serial Data Output to Audio DAC
9 BITCKO O Bit Clock Output to Audio DAC
10 LRCKO O Sample Rate Clock Output to Audio DAC
11 OVSMPCLK O Over-sampling Clock Output to Audio DAC
12 VDD PWR Digital Power
13 VSS GND Digital Ground
14 EXTCLK I External I2C Clock /12.288 MHZ
15 SDATAI I Serial Data Input from CD-DSP
16 SCLKI I Bit Clock Input from CD-DSP
17 CDDSPREQ O Data Request Output to CD-DSP
18 N.C.
19 RESUME I Resume from Sleep State
20 HRESB I Hardware Reset (active low)
21 TEST2 I Test Pin #2 (tied to VSS)
22 TEST3 I Test Pin #3 (tied to VSS)
23 TEST4 I/O Test Pin #4 (pulled low)
24 VDD PWR Digital Power

4
 GDT-1668
CD-MP3 Audio Decoder

Pin # Pin Name Pin Type Description

25 VSS GND Digital Ground
26 OSCO O 16.9344 MHZ Oscillator Output
27 OSCI I 16.9344 MHZ Oscillator Input
28 AVSS GND Analog Ground for PLL
29 AVDD PWR Analog Power for PLL
30 GPIO7 I/O General Purpose Programmable I/O Bit 7
31 N.C
32 GPIO6 I/O General Purpose Programmable I/O Bit 6
33 GPIO5 I/O General Purpose Programmable I/O Bit 5
34 GPIO4 I/O General Purpose Programmable I/O Bit 4
35 GPIO3 I/O General Purpose Programmable I/O Bit 3
36 VDD PWR Digital Power
37 VSS GND Digital Ground
38 GPIO2 I/O General Purpose Programmable I/O Bit 2
39 GPIO1 I/O General Purpose Programmable I/O Bit 1
40 GPIO0 I/O General Purpose Programmable I/O Bit 0
41 SA5 I I2C Slave Address Bit 5
42 SA4 I I2C Slave Address Bit 4
43 N.C.
44 SA3 I I2C Slave Address Bit 3
45 SA2 I I2C Slave Address Bit 2
46 SA1 I I2C Slave Address Bit 1
47 SA0 I I2C Slave Address Bit 0
48 VDD PWR Digital Power