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CD4051B, CD4052B, CD4053B Data sheet acquired from Harris Semiconductor August 1998 - Revised January 2003

CD4051B, CD4052B, CD4053B

Data sheet acquired from Harris Semiconductor

August 1998 - Revised January 2003

SCHS047F

Features

• Wide Range of Digital and Analog Signal Levels

-

Digital

 

3V to 20V

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20V P-P

 

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[ /Title

(CD405

1B,

• Low ON Resistance, 125(Typ) Over 15V P-P Signal Input Range for V DD -V EE = 18V

• High OFF Resistance, Channel Leakage of ±100pA (Typ) at V DD -V EE = 18V

• Logic-Level Conversion for Digital Addressing Signals of 3V to 20V (V DD -V SS = 3V to 20V) to Switch Analog Signals to 20V P-P (V DD -V EE = 20V)

• Matched Switch Characteristics, r ON = 5(Typ) for V DD -V EE = 15V

• Very Low Quiescent Power Dissipation Under All Digital- Control Input and Supply Conditions, 0.2µW (Typ) at V DD -V SS = V DD -V EE = 10V

• Binary Address Decoding on Chip

• 5V, 10V, and 15V Parametric Ratings

• 100% Tested for Quiescent Current at 20V

• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range, 100nA at 18V and 25 o C

• Break-Before-Make Switching Eliminates Channel

CD4052

B,

CD4053

B)

/Sub-

ject

(CMOS

Analog

Multi-

plex-

ers/Dem

ultiplex-

ers with

Logic

Level

Conver- Overlap

sion)

/Author

()

/Key-

words

(Harris

Semi- CMOS Analog Multiplexers/Demultiplexers

conduc- with Logic Level Conversion

tor,

CD4000

Applications

• Analog and Digital Multiplexing and Demultiplexing

• A/D and D/A Conversion

• Signal Gating

The CD4051B, CD4052B, and CD4053B analog multiplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage current. Control of

analog signals up to 20V P-P can be achieved by digital signal amplitudes of 4.5V to 20V (if V DD -V SS = 3V, a

V DD -V EE of up to 13V can be controlled; for V DD -V EE level

differences above 13V, a V DD -V SS of at least 4.5V is

required). For example, if V DD = +4.5V, V SS = 0V, and

V EE = -13.5V, analog signals from -13.5V to +4.5V can be

controlled by digital inputs of 0V to 5V. These multiplexer circuits dissipate extremely low quiescent power over the

full V DD -V SS and V DD -V EE supply-voltage ranges,

independent of the logic state of the control signals. When

a logic “1” is present at the inhibit input terminal, all channels are off.

The CD4051B is a single 8-Channel multiplexer having three binary control inputs, A, B, and C, and an inhibit input. The three binary signals select 1 of 8 channels to be turned on, and connect one of the 8 inputs to the output.

The CD4052B is a differential 4-Channel multiplexer having two binary control inputs, A and B, and an inhibit input. The two binary input signals select 1 of 4 pairs of channels to be turned on and connect the analog inputs to the outputs.

The CD4053B is a triple 2-Channel multiplexer having three separate digital control inputs, A, B, and C, and an inhibit input. Each control input selects one of a pair of channels which are connected in a single-pole, double-throw configuration.

When these devices are used as demultiplexers, the “CHANNEL IN/OUT” terminals are the outputs and the “COMMON OUT/IN” terminals are the inputs.

Ordering Information

 

TEMP. RANGE

 

PART NUMBER

(

o C)

 

PACKAGE

CD4051BF3A, CD4052BF3A,

-55 to 125

16

Ld CERAMIC

CD4053BF3A

DIP

CD4051BE, CD4052BE,

-55 to 125

16

Ld PDIP

CD4053BE

 

CD4051BM, CD4051BM96 CD4052BM, CD4052BM96, CD4053BM, CD4053BM96

-55 to 125

16

Ld SOIC

CD4051BNSR, CD4052BNSR,

-55 to 125

16

Ld SOP

CD4053BNSR

 

CD4051BPW, CD4051BPWR, CD4052BPW, CD4052BPWR CD4053BPW, CD4053BPWR

-55 to 125

16

Ld TSSOP

NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel.

1

1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Copyright ©

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated

to electrostatic discharge; follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated

CD4051B, CD4052B, CD4053B

Pinouts

CD4051B (PDIP, CDIP, SOIC, SOP, TSSOP) TOP VIEW

CD4052B (PDIP, CDIP, SOP, TSSOP) TOP VIEW

4 1 CHANNELS IN/OUT 6 2 COM OUT/IN 3 CHANNELS IN/OUT 7 4 5 5
4 1
CHANNELS
IN/OUT
6 2
COM OUT/IN
3
CHANNELS
IN/OUT
7
4
5
5

INH 6

7

8

V

V

EE

SS

OUT/IN 3 CHANNELS IN/OUT 7 4 5 5 INH 6 7 8 V V EE SS

16

15

14

13

12

11

10

9

V

2

1

0

3

A

B

C

DD

CHANNELS IN/OUT

0

2

COMMON “Y” OUT/IN

3

1

INH

Y

Y

CHANNELS

IN/OUT

IN/OUT 0 2 COMMON “Y” OUT/IN 3 1 INH Y Y CHANNELS IN/OUT CHANNELS IN/OUT V
IN/OUT 0 2 COMMON “Y” OUT/IN 3 1 INH Y Y CHANNELS IN/OUT CHANNELS IN/OUT V

CHANNELS

IN/OUT

V

V

EE

SS

CD4053B (PDIP, CDIP, SOP, TSSOP) TOP VIEW

 

by

1

IN/OUT

bx

2

cy

3

OUT/IN CX OR CY

4

IN/OUT CX

5

 

INH

6

V

EE

7

V

SS

8

5   INH 6 V EE 7 V SS 8 16 V DD 15 OUT/IN bx

16

V DD

15 OUT/IN bx OR by 14 OUT/IN ax OR ay 13 ay IN/OUT 12 ax
15
OUT/IN bx OR by
14
OUT/IN ax OR ay
13
ay
IN/OUT
12
ax
11
A
10
B

9 C

1

2

3

4

5

6

7

8

13 ay IN/OUT 12 ax 11 A 10 B 9 C 1 2 3 4 5

16

15

14

13

12

11

10

9

V

DD

2 X CHANNELS IN/OUT 1 COMMON “X” OUT/IN 0 X CHANNELS IN/OUT 3
2
X CHANNELS
IN/OUT
1
COMMON “X” OUT/IN
0
X CHANNELS
IN/OUT
3

A

B

Functional Block Diagrams

CD4051B

CHANNEL IN/OUT

3 A B Functional Block Diagrams CD4051B CHANNEL IN/OUT 7 6 5 4 3 2 1
7 6 5 4 3 2 1 0 16 V DD 4 2 5 1
7 6
5
4
3
2
1
0
16 V DD
4
2
5
1
12
15
14
13
TG
TG
A †
11
TG
COMMON
TG
B †
OUT/IN
10
3
LOGIC
LEVEL
TG
CONVERSION
BINARY
TO
1 OF 8
DECODER
WITH
C †
9
INHIBIT
TG
TG
INH †
6
TG
8
V
7
SS
V EE
† All inputs are protected by standard CMOS protection network.

2

2

CD4051B, CD4052B, CD4053B

Functional Block Diagrams (Continued)

CD4052B

A

B

INH

X CHANNELS IN/OUT 3 2 1 0 11 15 14 12 TG V 16 DD
X CHANNELS IN/OUT
3
2
1
0
11
15
14
12
TG
V
16
DD
TG
TG
COMMON X
OUT/IN
TG
13
10
BINARY
TO
TG
3
LOGIC
9
1 OF 4
COMMON Y
LEVEL
DECODER
OUT/IN
TG
CONVERSION
WITH
6
INHIBIT
TG
TG
1
5
2
4
0
1
2
3
8
7
V SS
V EE
Y
CHANNELS IN/OUT

CD4053B

BINARY TO 1 OF 2 DECODERS WITH INHIBIT IN/OUT LOGIC LEVEL 16 V DD CONVERSION
BINARY TO
1 OF 2
DECODERS
WITH
INHIBIT
IN/OUT
LOGIC
LEVEL
16 V DD
CONVERSION
cy
cx
by
bx
ay
ax
3
5
1
2
13
12
COMMON
OUT/IN
TG
ax
OR ay
14
A †
11
TG
COMMON
OUT/IN
TG
bx
OR by
15
B †
10
TG
COMMON
OUT/IN
TG
cx
OR cy
C †
9
4
TG
INH †
6
V
DD
8
V
7
SS
V EE
† All inputs are protected by standard CMOS protection network.

3

3

CD4051B, CD4052B, CD4053B

 

TRUTH TABLES

 
 

INPUT STATES

   

INHIBIT

C

B

A

“ON” CHANNEL(S)

CD4051B

0

 

000

 

0

0

 

001

 

1

0

 

010

 

2

0

 

011

 

3

0

 

100

 

4

0

 

101

 

5

0

 

110

 

6

0

 

111

 

7

1

X

X

X

None

CD4052B

INHIBIT

 

B

A

 

0

0

0

0x, 0y

0

0

1

1x, 1y

0

1

0

2x, 2y

0

1

1

3x, 3y

1

X

X

None

CD4053B

INHIBIT

A OR B OR C

 

0

 

0

ax or bx or cx

0

 

1

ay or by or cy

1

 

X

None

X = Don’t Care

4

4

CD4051B, CD4052B, CD4053B

Absolute Maximum Ratings

Supply Voltage (V+ to V-)

Thermal Information

Package Thermal Impedance, θ JA (see Note 1):

Voltages Referenced to V SS Terminal

DC

Input Voltage Range

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. -0.5V to V DD +0.5V

-0.5V to 20V

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PDIP package

SOIC package

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67 o C/W 73 o C/W

DC

Input Current, Any One

 

±10mA

SOP

package .

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64

o

C/W

Operating Conditions

 

TSSOP package

. Maximum Junction Temperature (Ceramic Package)

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108

o

C/W

.175 o C .150 o C

Temperature Range

 

-55 o C to 125 o C

Maximum Junction Temperature (Plastic Package) Maximum Storage Temperature Maximum Lead Temperature (Soldering 10s) (SOIC - Lead Tips Only)

.

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.

 

-65 o C to 150 o C .265 o C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

Electrical Specifications

Common Conditions Here: If Whole Table is For the Full Temp. Range, V SUPPLY = ±5V, A V = +1,

R L = 100, Unless Otherwise Specified

(Note 3)

   

CONDITIONS

   

LIMITS AT INDICATED TEMPERATURES ( o C)

 
                 

25

 

PARAMETER

V IS (V)

V EE (V)

V SS (V)

V DD (V)

-55

-40

85

125

MIN

TYP

MAX

UNITS

SIGNAL INPUTS (V IS ) AND OUTPUTS (V OS )

 

Quiescent Device Current, I DD Max

 

- -

-

 

5

5

5

150

150

-

0.04

5

µA

 

- -

-

 

10

10

10

300

300

-

0.04

10

µA

   

- -

-

 

15

20

20

600

600

-

0.04

20

µA

 

- -

-

 

20

100

100

3000

3000

-

0.08

100

µA

Drain to Source ON Resistance r ON Max 0 V IS V DD

 

- 0

0

 

5

800

850

1200

1300

-

470

1050

 

- 0

0

 

10

310

330

520

550

-

180

400

   

- 0

0

 

15

200

210

300

320

-

125

240

Change in ON Resistance (Between Any Two Channels), r ON

 

- 0

0

 

5

-

-

-

-

-

15

-

 

- 0

0

 

10

-

-

-

-

-

10

-

 

- 0

0

 

15

-

-

-

-

-

5

-

OFF Channel Leakage Current: Any Channel OFF (Max) or ALL Channels OFF (Common OUT/IN) (Max)

 

- 0

0

 

18

±100 (Note 2)

±1000 (Note 2)

-

±0.01

±100

nA

(Note 2)

Capacitance:

 

- -5

 

5-

5

               
 

Input, C IS

 

-

- -

- -

5

-

pF

Output, C OS

               

CD4051

-

- -

- -

30

-

pF

CD4052

-

- -

   

- -

18

-

pF

CD4053

-

- -

   

- -

9

-

pF

Feedthrough

               

C

IOS

-

- -

- -

0.2

-

pF

Propagation Delay Time (Signal Input to Output

V

DD

R L = 200k, C L = 50pF, t r , t f = 20ns

5

-

- -

   

- -

30

60

ns

10 - - -     - - 15 30 ns

10

-

- -

   

- -

15

30

ns

   

15

-

- -

   

- -

10

20

ns

5

5

CD4051B, CD4052B, CD4053B

Electrical Specifications

Common Conditions Here: If Whole Table is For the Full Temp. Range, V SUPPLY = ±5V, A V = +1, R L = 100, Unless Otherwise Specified (Continued) (Note 3)

   

CONDITIONS

   

LIMITS AT INDICATED TEMPERATURES ( o C)

   
                 

25

PARAMETER

V IS (V)

V EE (V)

V SS (V)

V DD (V)

-55

-40

85

125

MIN

TYP

MAX

UNITS

CONTROL (ADDRESS OR INHIBIT), V C

 

Input Low Voltage, V IL , Max

V IL = V DD

V EE = V SS , R L = 1kto V SS , I IS < 2µA on All OFF Channels

5

1.5

1.5

1.5

1.5

-

 

-

1.5

V

through

10

 

3

3

3

3

   

3

 

V

 

1k;

-

 

-

V IH = V DD

15

4

4

4

4

-

 

-

4

V

through

   
                   

Input High Voltage, V IH , Min

1k

5

3.5

3.5

3.5

3.5

3.5

 

-

-

V

10

7

7

7

7

7

 

-

-

V

 

15

11

11

11

11

11

 

-

-

V

Input Current, I IN (Max)

V IN = 0, 18

 

18

±0.1

±0.1

±1

±1

-

±10 -5

±0.1

µA

Propagation Delay Time:

                       

Address-to-Signal OUT (Channels ON or OFF) See Figures 10, 11, 14

t r , t f = 20ns, C L = 50pF, R L = 10k

0

0

5

- -

-

-

-

450

720

ns

0

0

10

- -

 

-

-

-

160

320

ns

 

0

0

15

- -

 

-

-

-

120

240

ns

 

-5

0

5

- -

 

-

-

-

225

450

ns

Propagation Delay Time:

                       

Inhibit-to-Signal OUT (Channel Turning ON) See Figure 11

t r , t f = 20ns, C L = 50pF, R L = 1k

0

0

5

- -

-

-

-

400

720

ns

0

0

10

- -

 

-

-

-

160

320

ns

   

0

0

15

- -

 

-

-

-

120

240

ns

-10

0

5

- -

 

-

-

-

200

400

ns

Propagation Delay Time:

                       

Inhibit-to-Signal OUT (Channel Turning OFF) See Figure 15

t r , t f = 20ns, C L = 50pF, R L = 10k

0

0

5

- -

-

-

-

200

450

ns

0

0

10

- -

 

-

-

-

90

210

ns

   

0

0

15

- -

 

-

-

-

70

160

ns

-10

0

5

- -

 

-

-

-

130

300

ns

Input Capacitance, C IN (Any Address or Inhibit Input)

 

- -

 

-

-

-

 

5

7.5

pF

NOTE:

2. Determined by minimum feasible leakage measurement for automatic testing.

 

Electrical Specifications

 
   

TEST CONDITIONS

 

LIMITS

 

PARAMETER

V IS (V)

V DD (V)

R L (k)

 

TYP

UNITS

Cutoff (-3dB) Frequency Chan- nel ON (Sine Wave Input)

5 (Note 3)

 

10

 

1

V OS at Common OUT/IN

 

CD4053

 

30

 

MHz

V EE = V SS ,

   

CD4052

 

25

 

MHz

   

V

20Log ------------= 3dB

OS

 

CD4051

 

20

 

MHz

V

IS

V OS at Any Channel

   

60

 

MHz

6

6

CD4051B, CD4052B, CD4053B

Electrical Specifications

   

TEST CONDITIONS

 

LIMITS

 

PARAMETER

V IS (V)

V DD (V)

R L (k)

 

TYP

UNITS

Total Harmonic Distortion, THD

2

(Note 3)

5

10

 

0.3

 

%

3

(Note 3)

10

0.2

 

%

5

(Note 3)

15

0.12

 

%

V

EE = V SS , f IS = 1kHz Sine Wave

 

%

-40dB Feedthrough Frequency (All Channels OFF)

5

(Note 3)

10

1

V OS at Common OUT/IN

CD4053

8

MHz

V

EE = V SS ,

 

CD4052

10

MHz

 

V

     
 

OS

20Log ------------= 40dB

V

CD4051

12

MHz

 

IS

V OS at Any Channel

8

MHz

-40dB Signal Crosstalk Frequency

5

(Note 3)

10

1

Between Any 2 Channels

 

3

MHz

V

EE = V SS ,

 

Between Sections,

Measured on Common

6

MHz

 

V

CD4052 Only

Measured on Any Chan-

nel

10

 
 

OS

20Log ------------= 40dB

V

IS

MHz

 

Between Any Two Sections, CD4053 Only

In Pin 2, Out Pin 14

2.5

MHz

In Pin 15, Out Pin 14

6

MHz

Address-or-Inhibit-to-Signal

 

-

10

10

 

65

mV

PEAK

Crosstalk

 

(Note 4)

 

V

EE = 0, V SS = 0, t r , t f = 20ns, V CC

65

mV

PEAK

=

V DD - V SS (Square Wave)

 

NOTES:

3. Peak-to-Peak voltage symmetrical about

4. Both ends of channel.

-----------------------------

2

V DD

V EE

Typical Performance Curves

600 5V V DD - V EE = 500 400 T A = 125 o
600
5V
V DD - V EE =
500
400
T A = 125 o C
300
T A = 25 o C
200
T A = -55 o C
100
0
r ON , CHANNEL ON RESISTANCE (Ω)

-4

-3

-2

-1

0

1

2

3

4

V IS , INPUT SIGNAL VOLTAGE (V)

5

FIGURE 1. CHANNEL ON RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES)

300 V EE = 10V V DD - 250 T A = 125 o C
300
V EE = 10V
V DD -
250
T A = 125 o C
200
150
T A = 25 o C
100
T A = -55 o C
50
0
r ON , CHANNEL ON RESISTANCE (Ω)

-10

-7.5

0

V IS , INPUT SIGNAL VOLTAGE (V)

-5

-2.5

2.5

5

7.5

10

FIGURE 2. CHANNEL ON RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES)

7

7

CD4051B, CD4052B, CD4053B

Typical Performance Curves (Continued)

600 T A = 25 o C V DD - V EE = 5V 500
600
T A = 25 o C
V DD - V EE = 5V
500
400
300
200
10V
100
15V
0
-10
-7.5
-5
-2.5
0
2.5
5
7.5
10
r ON , CHANNEL ON RESISTANCE (Ω)

V IS , INPUT SIGNAL VOLTAGE (V)

FIGURE 3. CHANNEL ON RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES)

6 V DD = 5V R L = 100kΩ, R L = 10k Ω V
6
V DD = 5V
R L = 100kΩ,
R L = 10k
V SS = 0V
1kΩ
V EE = -5V
4
500Ω
= 25 o C
T A
100Ω
2
0
-2
-4
-6
-6
-4
-2
0
2
4
6
V OS , OUTPUT SIGNAL VOLTAGE (V)

V IS , INPUT SIGNAL VOLTAGE (V)

FIGURE 5. ON CHARACTERISTICS FOR 1 OF 8 CHANNELS

(CD4051B)

5 10 T = 25 o C A ALTERNATING “O” TEST CIRCUIT AND “I” PATTERN
5
10
T
=
25 o C
A
ALTERNATING “O”
TEST CIRCUIT
AND
“I”
PATTERN
C
=
50pF
V
DD
L
f
4
10
CD4029
B/D
V
= 15V
V
DD
DD
A
B
100Ω
10
9
1
3
C
L
3
10
5
13
2
12
4
14
V DD = 10V
CD4052
15
6
11
2
10
V
= 5V
DD
7
8
C L = 15pF
Ι
10
3
4
5
1
10
10 2
10
10
10
P D , POWER DISSIPATION PACKAGE (µW)
100Ω

SWITCHING FREQUENCY (kHz)

FIGURE 7. DYNAMIC POWER DISSIPATION vs SWITCHING FREQUENCY (CD4052B)

250 V - V EE = 15V DD 200 T = 125 o C A
250
V
- V EE = 15V
DD
200
T
= 125 o C
A
150
T A = 25 o C
100
T A = -55 o C
50
0
-10
-7.5
-5
-2.5
0
2.5
5
7.5
10
r ON , CHANNEL ON RESISTANCE (Ω)

V IS , INPUT SIGNAL VOLTAGE (V)

FIGURE 4. CHANNEL ON RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES)

5 10 TEST CIRCUIT T = 25 o C A V DD ALTERNATING “O” AND
5
10
TEST CIRCUIT
T
=
25 o C
A
V
DD
ALTERNATING
“O”
AND “I”
PATTERN
B/D
f
C
= 50pF
CD4029
L
4
10
ABC
V
DD
V
=
15V
DD
100Ω
11
10
9
13
14
3
10
15
12
CD4051
1
V DD = 10V
5
3
2
2
10
4
V
=
5V
8
7
6
C
DD
L
100Ω
Ι
C
= 15pF
L
10
2
3
4
5
1
10
10
10
10
10
P D , POWER DISSIPATION PACKAGE (µW)

SWITCHING FREQUENCY (kHz)

FIGURE 6. DYNAMIC POWER DISSIPATION vs SWITCHING FREQUENCY (CD4051B)

5 10 T = 25 o C V = 15V DD A ALTERNATING “O” V
5
10
T
= 25 o C
V
=
15V
DD
A
ALTERNATING “O”
V
= 10V
AND “I”
PATTERN
DD
C
=
50pF
L
4
10
TEST
CIRCUIT
V DD
f
9
4
C
100Ω
L
3
12
3
10
5
13
100Ω
CD4053
2
10
1
11
15
V
=
5V
2
DD
10
6
14
7
8
C L = 15pF
Ι
10
1 10
10 2
10 3
10 4
10 5
P D , POWER DISSIPATION PACKAGE (µW)

SWITCHING FREQUENCY (kHz)

FIGURE 8. DYNAMIC POWER DISSIPATION vs SWITCHING FREQUENCY (CD4053B)

8

8

CD4051B, CD4052B, CD4053B

Test Circuits and Waveforms

V DD = 15V 16 V EE = 0V 7 8 V SS = 0V
V DD = 15V
16
V EE = 0V
7
8
V SS = 0V

(A)

V DD = 7.5V V DD = 5V = 5V V DD 5V 5V 7.5V
V DD = 7.5V
V DD = 5V
= 5V
V DD
5V
5V
7.5V
16
16
16
V SS = 0V
V SS = 0V
V SS = 0V
7
7
7
V EE = -7.5V
V EE = -10V
8
8
V EE = -5V
8
(B)
(C)
(D)

NOTE: The ADDRESS (digital-control inputs) and INHIBIT logic levels are: “0” = V SS and “1” = V DD . The analog signal (through the TG) may swing from V EE to V DD .

FIGURE 9. TYPICAL BIAS VOLTAGES

t r = 20ns t f = 20ns 90% 90% 50% 50% 10% 10% TURN-ON
t r = 20ns
t f = 20ns
90%
90%
50%
50%
10%
10%
TURN-ON TIME
90%
50%
10%
10%
TURN-OFF TIME

FIGURE 10. WAVEFORMS, CHANNEL BEING TURNED ON (R L = 1k)

t r = 20ns t f = 20ns 90% 90% 50% 50% 10% 10% 90%
t r = 20ns
t f = 20ns
90%
90%
50%
50%
10%
10%
90%
10%
TURN-OFF TIME
TURN-ON
TIME
t PHZ

FIGURE 11. WAVEFORMS, CHANNEL BEING TURNED OFF

(R L = 1k)

V DD V DD V DD 1 16 1 16 1 16 2 15 2
V DD
V DD
V DD
1 16
1
16
1
16
2 15
2
15
2
15
3 I DD
14
3
14
3
14
I DD
4 13
4
13
4
13
I DD
5 12
5
12
5
12
6 11
6
11
6
11
7 10
7
10
7
10
8 9
8
9
8
9
CD4051
CD4052
CD4053

FIGURE 12. OFF CHANNEL LEAKAGE CURRENT - ANY CHANNEL OFF

9

9

CD4051B, CD4052B, CD4053B

Test Circuits and Waveforms (Continued)

V

DD

1 16 2 15 I DD 3 14 4 13 5 12 6 11 7
1 16
2 15
I
DD
3
14
4
13
5
12
6
11
7
10
8
9
CD4051

V

DD

1 16 2 15 I DD 3 14 4 13 5 12 6 11 7
1 16
2 15
I
DD
3
14
4
13
5
12
6
11
7
10
8
9
CD4052

V

DD

1 16 I 2 15 DD 3 14 4 13 5 12 6 11 7
1 16
I
2 15
DD
3 14
4 13
5 12
6 11
7 10
8 9
CD4053

FIGURE 13. OFF CHANNEL LEAKAGE CURRENT - ALL CHANNELS OFF

V DD V DD OUTPUT OUTPUT OUTPUT 1 16 1 16 1 16 V DD
V DD
V DD
OUTPUT
OUTPUT
OUTPUT
1
16
1
16
1
16
V DD
2
15
R
2
15
R
C
V DD
L
C L
2
15
L
L
C
R
L
L
3
14
3
14
3
14
4
13
V EE
V DD
4
13
4
13
V
5
12
5
12
EE
V DD
5
12
V DD
6
11
V EE
6
11
V EE
6
11
V EE
V EE
V DD
V SS
CLOCK
V SS
CLOCK
7
10
7
10
7
10
IN
8
9
IN
V SS
8
9
8
9
CLOCK
V
SS
V SS
IN
V SS
CD4051
V SS
CD4053
CD4052
V SS
V SS

FIGURE 14. PROPAGATION DELAY - ADDRESS INPUT TO SIGNAL OUTPUT

V DD OUTPUT 1 16 R 50pF 2 15 L 3 14 V EE 4
V
DD
OUTPUT
1
16
R
50pF
2
15
L
3
14
V
EE
4
13
V
5
12
V DD
DD
6
11
V SS
CLOCK
V
7
10
EE
IN
V
8
9
SS
V SS
t PHL AND t PLH

CD4051

DD V 7 10 EE IN V 8 9 SS V SS t PHL AND t PLH

CD4052

CD4053

FIGURE 15. PROPAGATION DELAY - INHIBIT INPUT TO SIGNAL OUTPUT

V DD µA V IH 1K 1 16 2 15 3 14 1K 4 13
V DD
µA
V IH
1K
1 16
2 15
3 14
1K
4 13
V
IH
5
12
6
11
V
IL
7 10
8
9
CD4051B
V IL

MEASURE < 2µA ON ALL “OFF” CHANNELS (e.g., CHANNEL 6)

V DD

1 16 1K 2 15 µA 3 14 V 4 13 IH 5 12 1K
1 16
1K
2 15
µA
3
14
V
4
13
IH
5
12
1K
6 11
V
7 10
IL
8
9
V
IH
CD4052B
V
IL

MEASURE < 2µA ON ALL “OFF” CHANNELS (e.g., CHANNEL 2x)

V DD 1 16 1K 2 15 µA 3 14 1K 4 13 V IH
V DD
1 16
1K
2
15
µA
3
14
1K
4
13
V IH
5
12
6
11
V IH
V IL
7 10
8
9
V IL
CD4053B

MEASURE < 2µA ON ALL “OFF” CHANNELS (e.g., CHANNEL by)

FIGURE 16. INPUT VOLTAGE TEST CIRCUITS (NOISE IMMUNITY)

10

10

CD4051B, CD4052B, CD4053B

Test Circuits and Waveforms (Continued)

V DD

1 16 2 15 3 14 4 13 5 12 6 11 7 10 8
1 16
2 15
3 14
4 13
5
12
6
11
7 10
8
9
Ι CD4051
CD4053

V DD

1 16 2 15 3 14 4 13 5 12 6 11 7 10 8
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
Ι
CD4052

FIGURE 17. QUIESCENT DEVICE CURRENT

V DD

1 16 2 15 3 14 4 13 5 12 V DD 6 11 7
1
16
2
15
3
14
4
13
5
12
V
DD
6
11
7
10
Ι
8
9
V
SS
CD4051
V SS
CD4053
NOTE: Measure inputs sequentially,
to both V DD and V SS connect all
unused inputs to either V DD or V SS .
KEITHLEY V DD 160 DIGITAL MULTIMETER TG 10kΩ “ON” 1kΩ Y RANGE V X-Y SS
KEITHLEY
V DD
160 DIGITAL
MULTIMETER
TG
10kΩ
“ON”
1kΩ
Y
RANGE
V
X-Y
SS
PLOTTER
X
H.P.
MOSELEY
7030A

FIGURE 18. CHANNEL ON RESISTANCE MEASUREMENT CIRCUIT

V DD 1 16 2 15 3 14 4 13 5 12 V DD 6
V DD
1
16
2
15
3
14
4
13
5
12
V DD
6
11
7
10
Ι
8
9
V SS
CD4052
V SS
NOTE: Measure inputs sequentially,
to both V DD and V SS connect all
unused inputs to either V DD or V SS .

FIGURE 19. INPUT CURRENT

5V P-P

CHANNEL ON RF COMMON R L OFF VM CHANNEL 1K V DD CHANNEL 6 OFF
CHANNEL
ON
RF
COMMON
R
L
OFF
VM
CHANNEL
1K
V
DD
CHANNEL
6
OFF
7
R
L
8

RF

VM

5V P-P CHANNEL OFF RF VM R L CHANNEL ON R L
5V P-P
CHANNEL
OFF
RF
VM
R L
CHANNEL
ON
R L

FIGURE 20. FEEDTHROUGH (ALL TYPES)

FIGURE 21. CROSSTALK BETWEEN ANY TWO CHANNELS (ALL TYPES)

5V P-P CHANNEL IN X ON OR OFF
5V P-P
CHANNEL IN X
ON OR OFF
 

CHANNEL IN Y

 
  CHANNEL IN Y   RF

RF

 
R L
R
L

ON OR OFF

 
R L
R
L

VM

   
   

FIGURE 22. CROSSTALK BETWEEN DUALS OR TRIPLETS (CD4052B, CD4053B)

11

11

CD4051B, CD4052B, CD4053B

Test Circuits and Waveforms (Continued)

DIFFERENTIAL CD4052 CD4052 SIGNALS COMMUNICATIONS LINK DIFF. DIFF. AMPLIFIER/ RECEIVER LINE DRIVER DIFF.
DIFFERENTIAL
CD4052
CD4052
SIGNALS
COMMUNICATIONS
LINK
DIFF.
DIFF.
AMPLIFIER/
RECEIVER
LINE DRIVER
DIFF.
DEMULTIPLEXING

MULTIPLEXING

FIGURE 23. TYPICAL TIME-DIVISION APPLICATION OF THE CD4052B

Special Considerations

In applications where separate power sources are used to drive V DD and the signal inputs, the V DD current capability should exceed V DD /R L (R L = effective external load). This provision avoids permanent current flow or clamp action on the V DD supply when power is applied or removed from the CD4051B, CD4052B or CD4053B.

A B CD4051B C A B C INH Q 0 D A COMMON Q OUTPUT
A
B
CD4051B
C
A
B
C
INH
Q
0
D
A
COMMON
Q
OUTPUT
1
1/2
A
B
E
B
CD4051B
CD4556
Q
C
2
E
INH
A
B
CD4051B
C
INH
FIGURE 24. 24-TO-1 MUX ADDRESSING

12

12

CD4051B, CD4052B, CD4053B

13

13

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