Physical Design Complete

7/14/13
Physical Design Complete
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Physical Design Concepts

set_clock_latency on the virtual clocks to match the clock tree insertion delay in case of a block level implementation. It is possible to leave unchanged values if the estimated latencies is reasonably close to the implemented clock tree insertion delay. In case of a top level implementation, input/output delay might not change at all with respect to the chip internal insertion delay. This is highly dependant on the IO logic involved.
set_clock_uncertainty that must not include margin for clock tree implementation any more (but typically still include PLL jitters for setup, and functional hold margin with respect to
substrate noise).
set_clock_latency and set_clock_transition on real clocks should be removed. The flow scripting automatically removes the spurious set_clock_transition, set_clock_latency and put the clocks in propagated mode automatically in Physopt flow. CTS options:
Max transition: maximum slope allowed at leaf pins. Max skew: maximum skew targeted among leaf pins Names of buffers allowed for insertion. Names of inverters allowed for insertion. Routing rule: specific routing rule used for routing clock tree nets. Routing mode: select the CTS mode.
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3. Floorplanning
1. What is Pad limited design and core limited design. Is there any difference in approaches to handle these? Pad limited design: The Area of pad limits the size of die. No of IO pads may be lager. If die area is a constraint, we can go for staggered IO Pads. Core limited design: The Area of core limits the size of die. No of IO pads may be lesser. In these designs In line IOs can be used. 2. How will we decide chip core area?
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Core Size
Sandard Cell Area S tan dared Cell Utilization
(Macro Area + Hallo)
Die Size= CoreSize+ IO to CoreClearance ) + Areaof Bond + Areaof Pad(Including IO Pitch Area
I/O-core clearances is the space from the core boundary to the inner side of I/O pads(Design Boundary)
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How to arrive at the value of utilization factor and aspect ratio during initial floorplan?
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the Standard Cells occupies 70 % of Base Layers and the remaining 30 % is utilized for Routing. If the area of macros is more then utilization can be increased accordingly Chip utilization, flat
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Chip Utilizatio n =
Area of [ Sandard Cell
Macro + ( Pad , PadFiller , CornerPad )] Area of Chip
Blockages, macros, and pads are combined in the denominator of the effective Utilization. The effective utilization definition is that all standard cells are placed outside of the blockage areas. This includes buffers, which (for the purposes of computing utilization) are assumed to be placed outside of non-buffer blockage areas.
Best Aspect Ratio: Consider a five-layer design in which layers 1, 3, and 5 are horizontal and layers 2 and 4 are Search This Document vertical. Usually, layer Search 1 is occupied by the standard cell geometries and is unusable for routing. Search History:to metal layer 1 pins through vias. These vias tend to obstruct about Metal layer 2 often connects 20 percent of the potential vertical routing on metal layer 2. If routing pitch is the same on all
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20 percent of the potential Searching... vertical routing on metal layer 2. If routing pitch is the same on all Result 00 of 00 layers, the ratio between horizontal and vertical layers is approximately 2 : 1.8. This means that 00 results for result for the available vertical routing resource is less than the horizontal routing resource, which dictates p. a chip aspect ratio that is wider than it is high.
Using the ratio of horizontal-to-vertical routing resources, the best aspect ratio is 1.11; therefore, the chip aspect ratio is rectangular rather than square and is wider than it is high:
AspectRatio =
W H
Horizontal Routing Re sources Vertical Routing Re sources
Next, consider a four-layer design. metal layer 1 is not usable for routing, and metal layer 2 is 20 percent obstructed by vias connecting layer 1 andlayer 2. Layer 3 is horizontal and fully available, and layer 4 is vertical and fully available. For this case, there is 80 percent more vertical routing resource than there is horizontal resource. Therefore, the ratio of horizontal to vertical routing resource is 0.56, and the vertical dimension of this chip is larger than its horizontal dimension. The assumptions is that metal layer 1 is unavailable for routing and that metal layer 2 is 20 percent obstructed by vias.
4. What is an HALO? How is it different from the blockage? Block halos can be specified for hard macros, black boxes, or committed partitions. When you add a halo to a block, it becomes part of the blocks properties. If you move the block, the halo moves with it. Blockages can be specified for nay part of the design. If we move the a block, the blockage will
not.

4. What is the best place to put an HARD macro if it is a power hungry device and dissipates lot of heat? By placing Power hungry macros near the boundary of core, the required amount of current can be supplied, hence avoid dropped voltage supplyied to std cells and avoid Electron migration. 4. Is there any thumb rule to be followed for deciding the assignment of different layers? The top most layers have to be may be power 4. How will you do floor planning for multi supply design? Create Voltage Regions
4. What is the minimum clearance (placement and routing) around macro?

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4. What is the minimum clearance (placement and routing) around macro? -That will vary between macros, we need to check the Macro data sheet and decide. 4. How is floorplanning done in hierarchical flow? Partitioning
4. How to decide on the shape of the floorplan for soft macro. Explanation with case study is helpful. 4. How to Decide pin/pad location? To meet Top level requirements (If it is block ) Timing Timing and congestion Board design Requirement or standard Area and Power 4. How much utilization is used in the design? There is no hard and fast rule, even though if the following values maintained then the design can be closed without much congesstion Floor Plan - 70 % Placement - 75 %
CTS - 80 % Routing During GDSii Generation 100 %
- 85 %
4. What is the difference between standard cells and IO cells? Is there any difference in their operating voltages? If so why is it. Std Cells are logical cells. But the IO cells interact between Core and Outside world. IO cells contains some protection circuits like short circuit, over voltage. There will be difference between Core operating Voltage and IO operating voltage. That depends on technology library used. For 130 nm generic library the Core voltage is 1.2 v and IO voltage is 2.5/3.3. 4. What is the significance of simultaneous switching output (SSO) file? SSO: The abbreviation of Simultaneously Switching Outputs, which means that a certain number of I/O buffers switching at the same time with the same direction (H ! L, HZ ! L or L ! H, LZ ! H). This simultaneous switching will cause noise on the power/ground lines because of the large di/dt value and the parasitic inductance of the bonding wire on the I/O power/ground cells. SSN: The noise produced by simultaneously switching output buffers. It will change the voltage levels of power/ground nodes and is so-called Ground Bounce Effect. This effect is tested at the device output by keeping one stable output at low 0 or high 1, while all other

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outputs of the device switch simultaneously. The noise occurred at the stable output node is called Quiet Output Switching (QOS). If the input low voltage is defined as Vil, the QOS of Vil is taken to be the maximum noise that the system can endure.
DI: The maximum copies of specific I/O cell switching from high to low simultaneously without making the voltage on the quiet output 0 higher than Vil when single ground cell is applied. We take the QOS of Vil as criterion in defining DI because 1 has more noise margin than 0. For example, in LVTTL specification, the margin of Vih (2.0V) to VD33 (3.3V) is 1.3V in typical corner, which is higher than the margin of Vil (0.8V) to ground (0V). DF: Drive Factor is the amount of how the specific output buffer contributes to the SSN on the power/ground rail. The DF value of an output buffer is proportional to dI/dt, the derivative of the current on the output buffer. We can obtain DF as: DF = 1 / DI 4. Explain Floor planning, from scratch to end? Floorplanning is the process of: Positioning blocks on the die or within another block, thereby defining routing areas between them. Creating and developing a physical model of the design in the form of an initial optimized layout Because floorplanning significantly affects circuit timing and performance, especially for complex hierarchical designs, the quality of your floorplan directly affects the quality of your final design
If we have multi height cells in the reference library separate placement rows have to be provided for two different unit tiles. Creating I/O Rings Creating the Pad Ring for the Chip Creating I/O Pin Rings for Blocks Preplacing Macros and Standard Cells using Data Flow diagram and by fly-line analysis.
Calculation of Core, Die size and Aspect Ratio. 70% of the core utilization is provided Aspect ratio is kept at 1 Initializing the Core Rows are flipped, double backed and made channel less
Prerouting Buses The core area is divided into two separate unit tile section providing larger area for Hvt unit tile as shown in the Figure 3.
Creating Placement Blockages
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