Ex.

No:3

Date:.

Modelling Of Multiplexer Using VHDL

Aim:

To stimulate a multiplexer circuit using VHDL.

Software Used:

Active HDL 4.1

Theory:

The term multiplexer means many input to one output. There are n i/p lines. There is a single o/p line which is connected to compiler i/p port. o/p is selected based on the selected lines. A multiplexer is a combinational circuit that selects binary information from one of many i/p lines and directs it to a single o/p line. The selection of a particular i/p line is controlled by a set of select lines. The multiplexer have n i/p line m control line and 2m =n.
Program: 4:1MUX: Library IEEE; USE IEEE STD _LOGIC_1164.ALL; Port (o: in STD_LOGIC_VECTOR (3 DOWN TO 0); p: in STD_LOGIC_VECTOR (3 DOWN TO 0); q: in STD_LOGIC_VECTOR (3 DOWN TO 0); r: in STD_LOGIC_VECTOR (3 DOWN TO 0); s: in STD_LOGIC_VECTOR (1 DOWN TO 0);

y: in STD_LOGIC_VECTOR (3 DOWN TO 0); end mux; architecture mux of mux is begin process (o,p,q,r,s) begin if (s<=00)then y<=o; elsif (s<=01)then y<=p; elsif (s<=10)then y<=q; elsif (s<=11)then y<=r; end if end process end mux; 8:1 MUX: Library IEEE; USE IEEE STD _LOGIC_1164.ALL; entity mux is Port (a: in STD_LOGIC_VECTOR (7 DOWN TO 0); b: in STD_LOGIC_VECTOR (7 DOWN TO 0); c: in STD_LOGIC_VECTOR (7 DOWN TO 0); d: in STD_LOGIC_VECTOR (7 DOWN TO 0);

e: in STD_LOGIC_VECTOR (7 DOWN TO 0); f: in STD_LOGIC_VECTOR (7 DOWN TO 0); g: in STD_LOGIC_VECTOR (7 DOWN TO 0); h: in STD_LOGIC_VECTOR (2 DOWN TO 0); s: out STD_LOGIC_VECTOR (7 DOWN TO 0); end mux; architecture mux of mux is begin process (a,b,c,d,e,f,g,h,s) begin if (s<=000)then y<=a; elsif (s<=001)then y<=b; elsif (s<=010)then y<=c; elsif (s<=011)then y<=d; elsif (s<=100)then y<=e; elsif (s<=101)then y<=f; elsif (s<=110)then y<=g; elsif (s<=110)then y<=g; elsif (s<=111)then y<=h; end if end process

end mux;

Procedure: 1. Open the application active HDL 4.1. 2. Open new project and select VHDL module. 3. Specify input and output process. 4. Type the program using Xilinx 4.1. 5. Synthesis the program using model sim. 6. Simulate the program using model sim. 7. Simulate the program using model sim and view the output.

Result: Thus the multiplexer circuits are simulated using VHDL.

4:1 MUX: Logic diagram:

Truth table:
Input S0 0 0 1 1 S1 0 1 0 1 Output Y a b c d

Circuit Diagram:

8:1 MUX:

Logic Diagram:

Circuit Diagram:

Truth table: Input S0 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S2 0 1 0 1 0 1 0 1 Output Y a b c d e f g h

Output: 4:1 MUX:

8:1 MUX: