Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
SUMMARY
Over 19 years experience designing complex ASICs and FPGAs, recipient of 3 patents. Strengths include chip and micro
architecture, RTL development, verification as well as project management. Extensive knowledge of Ethernet, IP, ATM,
SONET.
• Experience with C/C++, Specman E, Perl, Verilog, VHDL, Cadence NCS, Modelsim, Primetime, Synopsys,
Synplicity, Xilinx, Lattice FPGA
• Familiar with physical design process including Synopsys DC Compiler, Formal Verification, DFT techniques
including JTAG, Scan Test, BIST, floorplanning, placement and routing concepts.
A team player with a proven track record of visualizing and implementing solutions to the most complex problems;
contributes equally effectively as a leader or member of a dynamic group.
PROFESSIONAL EXPERIENCE
PATENTS
EDUCATION