LAB-MANUAL ON CADENCE VIRTUOSO TOOL (ANALOG AND MIXED SIGNAL)

OPENING THE VIRTUOSO COMMAND INTERPRETOR WINDOW (CIW): Right click on desktop->Terminal window opens In Terminal window,

csh ->To invoke c shell mode. source ~/cshrc ->To invoke all the variables related to tool. NOTE: cshrc stands for c-shell related/running commands. pwd -> To check the present working directory. ls ->To list all the files and folders in the present directory. cd cadence_ms_labs_614/ virtuoso -> To open the virtuoso CIW. NOTE: If the Whats new window appears, close it with file->close and do not show window again option.

CREATE A NEW LIBRARY In CIW, File ->New ->Library Choose the third option: attach existing technological library gpdk180.tf Enter name of library as: ambedkar Press OK. This creates ambedkar library in 180 nm technology.

CREATE A CELL (Inverter) IN LIBRARY(ambedkar): In CIW, File->New->cellview

It opens a new file window. In the new file window, Set library as ambedkar Enter cell name as inverter Set type as schematic Press OK. This opens a blank schematic editor window.

CREATING INVERTER SCHEMATIC: In the schematic editor window, Go to create ->instance. Click on browse button. Select library as gpdk180,select category as mos, select nmos,select symbol,close and hide. Place the nmos component in the schematic window. NOTE: After placing any instance, always press the ESC key. Create ->pin. The add pin window appears. Set direction as input Enter pin names as vin, vdd and vss. Place the pins on schematic window. NOTE: Press R to rotate the pins before placing them. Create ->pin Set direction as output Enter pin name as vout Create ->wire (narrow). Make all circuit connections. NOTE: To make connections, left click on one node, extend the wire upto another node and left click on the second node. Check and save.

See CIW for any errors. NOTE: Never place one instance over another.

CREATING SYMBOL FOR INVERTER SCHEMATIC: In the inverter schematic window, Create ->cellview-> from cellview The cellview from cellview window opens Verify that from view name is set to schematic, to view name is set to symbol and the tool/data type is set to schematic symbol. Click OK This opens symbol generation options window. Specify the pin specifications as: Left ->vin, right ->vout, top ->vdd, bottom ->vss. Click OK Inverter symbol is created.

EDITING THE SYMBOL: Select the green rectangle by left clicking on it, and click on delete icon in the symbol window to delete it. NOTE: The green rectangle represents the editing window and the red rectangle represents the symbolic area. Create ->line and draw a triangle. Create ->circle and draw a circle. Check and save.

CREATING AN INVERTER TEST CIRCUIT: In CIW, File ->New ->cellview.

Create cell named inverter_test and type schematic. A new schematic editor windows. In the schematic editor window, Go to Create ->instance. Click on browse button. Select library as ambedkar,cell as inverter, and view as symbol. Place inverter symbol on schematic. Create ->instance->browse. Select library as analog_lib,select vpulse,select symbol and close. Set pulse parameters as: V1:0, V2:3, Period:40ns,delay time:1ns,rise time:1ns,fall time:1ns,pulse width:20ns. Hide and place the vpulse on schematic. Create ->instance ->browse. Select library as analog_lib,select vdc,select symbol and close. Set dc voltage as 1.8v. Hide and place. Create ->instance ->browse. Select library as analog_lib, select gnd, select symbol and close. Place the gnd symbol on schematic. Create ->instance ->pin. Set direction as output and pin name as out. Place the pin on schematic. Check and save.

ANALOG SIMULATION WITH SPECTRE (INVERTER_TEST CIRCUIT): In the inverter_test schematic window, Launch ->ADEL.

This opens virtuoso analog design environment (ADE) simulation window. Go to set up->design->inverter_test and click OK. Go to set up->simulator/directory/host. In the choosing simulator form, set up the simulator field to spectre and click OK. NOTE: To add model files go to setup->model libraries.

CHOOSING ANALYSES: In the ADE window, Go to Analyses->choose. Set up for transient analysis: In the choosing analyses window, select tran Select stop time as 200ns Click at the moderate and enabled button at the bottom. Click OK. Selecting outputs for plotting: In the ADE window, Go to outputs->to be plotted. Open the inverter_test schematic window and select the wires connecting the outputs to be plotted. NOTE: Selecting wires, plot the corresponding voltage and selecting nodes, plot the corresponding current. NOTE: Spectre cannot simulate transistor level schematic. Running the simulation: Click on run icon or go to simulation ->netlist and run. This creates the netlist as well as run the simulation and plot the outputs. Set up for DC analysis: Go to Analyses ->choose. In the choosing analyses window,select DC.

Turn on save dc operating point. Turn on the component parameters. Double click on select component, which takes you to schematic window. Select input vpulse in the inverter_test schematic window. Select dc voltage in the select component parameter window and click OK. In the choosing analyses window, set start and stop time as 0 and 1.8 V. Turn on the enable button and click OK. Run the simulation.

Changing design parameters: In the schematic window,select PMOS symbol,press Q, A new window opens. Set the total width as wp. Press OK. NOTE: If, it is not editable, Go to File->editable. Check and save.

Set up for parametric analysis: Parametric analysis yields information for each parametric step. Run a parametric dc analysis on the wp variable of the PMOS device of the inverter by sweeping the value of wp. In the ADE window, Go to Tools->parametric analysis. The parametric analysis window opens. Here, execute setup->pick name for variable ->sweep1. Set the variable name field as wp. Set the range type as from 1u to 20u. Set steps as 10. This varies the value of wp between 1um and 20um at ten equally spaced intervals.

In the inclusion and exclusion list, the value of wp to be included into and excluded from parametric analysis can be specified. EX: Inclusion list: 17u ,performs parametric analysis for wp=17u,and Exclusion list:16u, excludes parametric analysis for wp=16u. Execute Analysis->start.

CREATING LAYOUT VIEW OF INVERTER: In CIW, Go to Tools->Library manager->Ambedkar->inverter->schematic and open it. In the schematic window, Select PMOS symbol, press Q(edit object properties), change total width from wp to 2u, press OK. Go to Launch->LayoutXL Set create new and automatic. Press OK. NOTE: Layout is always done from schematic. The LayoutXL window opens. In the LayoutXL window, Go to connectivity->Generate->All from source. Select stretch icon, stretch the upper window and drag and drop all symbols below into the upper window. Press shift+F to view all the layers in the components. Go to Place->pin placement. This opens the pin assistant window. Do place as in schematic and close. Go to place->pin placement. Click on vdd and vss. Click on Hrail, apply and close. NOTE: Press F to fit the design in the window.

Change workspace to Basic. This opens the navigator window. Clicking on vss,vdd ,vin ,vout etc shows the routing to be done. Click on vdd. The routing to be done is displayed. Go to create->wiring->wire. Do the metal to metal connections. Press enter. NOTE: As the connections are done,the exclamatory mark on vdd disappears. For metal to poly connections, Go to create->wiring->wire->right click ->select via-> Poly ->make connections and enter. Make connections to vss,vout and vin. NOTE: Routing can be done automatically by Route->Automatic Routing.

PHYSICAL VERIFICATION:

Running DRC (Design Rule Check):

In the inverter layout window, Go to Assura ->Run DRC. If any DRC errors, they exists in VLW(view layer window) and are also highlighted in the schematic. Correct the DRC errors, if any and re-run the DRC check. If no DRC errors, a dialog box appears with no DRC errors found written in it.

Running LVS (Layout Verification System):

Go to Assura->Run LVS.

Running QRC (RC Extraction):

Go to Assura->Run QRC. From the CIW,

Tools->Library Manager->ambedkar->inverter->av_extracted and open it. Press shift+F in the av_extracted window to view all the parasitics.

CREATING THE CONFIGURATION VIEW: In CIW, Tools->Library Manager. File->new->cellview. Select Type->config. Press OK. The Hierarchy Editor and New Configuration window opens. Click use template at the bottom of New Configuration window and select spectre in the cyclic field and click OK. Change the top cellview to schematic and remove the default entry from the Library list. Click OK in the New Configuration window. In the Hierarchy Editor, click on Tree view. Save current settings. Close the Hierarchy Editor window.

To run the circuits with parasitics:

Open the same Hierarchy Editor window set for inverter_test configuration. Select the Tree view. Click right mouse on the inverter schematic. From set Instance View, select av_extracted view. Click on recompute the Hierarchy icon. When simulation completes, it displays all nets,designed devices,sources and parasitic devices as well.

To run the circuit without parasitics:

In CIW, Tools->Library Manager->ambedkar->inverter_test->config and open it. In the top cellview window, turn ON both the cyclic buttons and click OK. Execute Launch ADE L from the schematic window that is opened. Perform all the analysis and run again. In CIW,in the circuit inventory section,netlisting statistics is included. This contains all nets,designed devices,sources and loads.

Creating GDS II (Graphical Data Stream) file: In CIW, File->Export->Stream. This opens a virtuoso Xstream out window. Set stream file as ambedkar.gds Set library as ambedkar. Set toplevel cell as inverter Set view as layout. Click on options button .Go to layer tab. Select use automatic mapping.hide options. Click on Translate button. The stream file ambedkar.gds is stored in the specified location. To open the file from the terminal window, cd Cadence_ms_labs_614/ vi ambedkar.gds

NOTE: To edit the properties of a component, click on that component. Press Q.Edit the properties in the Edit Object Properties window.

NOTE: In the Edit Object Properties window, bodytie type shows the substrate connection. For source and substrate connected, select integrated. For no connection between source and substrate, select detached. NOTE: For giving a sine wave as input, select vsin from analog library.

CALCULATOR: It is used to edit the signals to be plotted and to calculate various parameters, i.e. bandwidth, slew rate etc. In the analog design environment (ADE) window, Go to Tools-> calculator. Ex: To calculate the bandwidth, select the signal waveform from the waveform window. Go to functional panel, select all, select bandwidth. Click on the evaluate the buffer icon. The bandwidth is calculated and displayed.

TRANSISTOR STATUS: In ADE window, Go to Results ->print -> dc operating point. In the schematic window, click on the centre of PMOS. It displays the dc operating point and the region of operation of transistor (as 0,1,2,3 or 4). The region of operation are given as: 0 cutoff, 1 triode/linear, 2 saturation, 3 subthreshold, 4 reverse. Go to results ->print ->model parameters. In the schematic window, click on the centre of PMOS.

SPECTRUM: In the waveform window, Go to measurements->spectrum.

Click on the waveform and click on plot. It displays the THD (Total Harmonic Distortion), Noise Figure, ENOB, SNR etc.

AMS (Analog Mixed Signal): It is used to simulate a design having both analog and digital blocks together. Ex: A buffer is created using an analog inverter and a digital inverter designed using verilog code. CREATING A DIGITAL INVERTER USING VERILOG CODE: In CIW, Go to file->new->cellview. Select cell as inv_verilog. Select type as verilog. Select view as verilog. Click OK. It opens the vi editor.

In the vi editor, Click i to enter into the write mode. Program: module inve_verilog (a,y); input a; output y; assign y=~a; endmodule. To save: ESC :wq ->enter. To check whether the verilog symbol is created or not,

Go to Tools ->Library manager ->Ambedkar ->inve_verilog ->symbol. CREATING SCHEMATIC FOR BUFFER: In CIW, Go to File -> new->cellview. Select cell as buffer. Select type as schematic. Click OK. In the schematic editor window, Go to create ->instance ->inverter. Place it on schematic. Go to create ->instance ->inve_verilog. Place it on schematic. Create ->pin ->vdd vss vin with direction input. Create pin ->vout with direction output. Make all connections. Check and save.

Create symbol for buffer: In schematic window, Go to create -> cellview ->from cellview. Align the pins. This creates the symbol. Check and save.

Create buffer_test schematic: In CIW, Go to file->new->cellview.

select cell as buffer_test. select type as schematic. Click OK. In the schematic window, Go to create->instance. Browse. Go to Ambedkar->buffer->symbol. Place it on schematic. For input, Go to create ->instance. Browse. Go to analoglib.->vpulse. Set pulse parameters as: V1-0, v2-3, period-20ns,delay time-1ns,rise time-1ns,fall time-1ns,pulse width-10ns. For vdd, Go to create ->instance. Browse. Go to analoglib.->vdc. Set dc voltage as: 1.8 Go to create ->instance. Browse. Go to analoglib.->gnd. Connect negative terminal of vpulse, vdc and vss pin to ground. Check and save.

CREATE CONFIG VIEW: In CIW,

Go to file->new->cellview. Select type as config. Select view as schematic. Click on use template. Set name to AMS. Click OK. Delete my_lib from library list. Click OK. Hierarchy Editior window opens. In that window, Go to Tree view. Right click on I/O,Go to instance view ->schematic. Click on recompute the hierarchy icon. Save and close. In CIW, Go to Tools->Library manager ->buffer_test->config and open it. A window is opened. Click yes on both. Click OK. In the config window, Go to launch ->ADEL. In the ADE window, Go to setup ->simulator/directory/host. Change to AMS. Click OK. Go to analyses ->choose. Select tran. Set stop time as 200ns. Click OK.

Go to outputs ->to be plotted->select on schematic. Select the input and output wire on schematic. Run the simulation.

NOTE: For choosing an inductor instance, in CIW, Go to Tools->Library manager. Select library as gpdk180 ->ind ->symbol.

POWER DISSIPIATION: In ADE window, Go to analyses ->choose. Select dc Turn on save dc operating point. Go to results ->print ->dc operating point. Select supply voltage in the schematic. This displays the total power dissipation. To check leakage voltage, input is grounded.

NOTE: The model libraries can be SS(slow slow), SF(slow fast), FF(fast fast) or NN(nominal nominal). They can be changed as follows: In ADE window, Go to set up ->model libraries.