Homework #9 Solution

1. Create Verilog modules that implement each of the following: a) b) c) d) An inverter. A 5-input AND gate. A 4-to-1 multiplexer. A J-K flip-flop with enable, asynchronous set and reset (i.e., preset and clear), and true and complemented outputs. e) A circuit that, when enable is true, counts clock transitions and generates a high output every 8 clock cycles.
module inverter(a, not_a); input a; output not_a; assign not_a = ~a; endmodule module and_5_inp(x, y); input[4:0] x; output y; assign y = x[0] & x[1] & x[2] & x[3] & x[4]; endmodule module mux_4_to_1(x, s, y); input[3:0] x; input[1:0] s; output y; assign y = x[s]; endmodule

module jk_flip_flop(preset, clear, en, clk, j, k, q, not_q); input preset, clear, en, clk, j, k; output reg q; output not_q; always @(posedge preset, posedge clear, negedge clk) if (preset) q <= 1'b1; else if (clear) q <= 1'b0; else if (en) case ({q, j, k}) 3'b000: q <= 1'b0; 3'b001: q <= 1'b0; 3'b010: q <= 1'b1; 3'b011: q <= 1'b1; 3'b100: q <= 1'b1; 3'b101: q <= 1'b0; 3'b110: q <= 1'b1; 3'b111: q <= 1'b0; endcase assign not_q = ~q; endmodule module divide_by_8(clk, en, tick); input clk, en; output reg tick; reg[2:0] s, snext; /* Advance state */ always @(negedge clk) if (en) s <= snext; /* Next state */ always @(s) snext <= s + 1'b1; /* Output */ always @(s) if (s == 3'b000) tick <= 1'b1; else tick <= 1'b0; endmodule

2. A clocked sequential circuit has three states: rest, armed, fire. The transitions are caused by external inputs according to the following rule: if the system is in the rest state, it will transition to the armed state if the RDY signal is asserted without regard for the FRE signal; if it is in the armed state, it will transition to the fire state if the FRE signal is asserted and the RDY signal is asserted; if it is in the fire state, it will transition to the ready state always without regard for the inputs. a) Create a Verilog module for this state machine.
Here is the state diagram:
0x

Rest 00 1x xx

Armed 01

11

Fire 11

01, 00, 10

module state_machine(rdy, fre, clk, rst, q); input rdy, fre, clk, rst; output[1:0] q; /* Use this to test state machine */ reg[1:0] s, snext; /* Advance or reset */ always @(negedge clk, posedge rst) if (rst) s <= 2'b00; else s <= snext; /* Next state */ always @(s, fre, rdy) case (s) 2'b00: if (rdy) snext <= 2'b01; else snext <= 2'b00; 2'b01: if (rdy & fre) snext <= 2'b10; else snext <= 2'b01; 2'b10: snext <= 2'b00; endcase /* Output */ assign q = s; endmodule

b) Write a test-bench for the FSM that shows its correct behavior. Run the simulation and attach the obtained outputs (text output of iverilog or waveforms on Xilinx).
module test_state_machine; reg rdy, fre; reg clk, rst; wire[1:0] q; /* Instantiate FSM */ state_machine M1(rdy, fre, clk, rst, q); /* Clock signal */ initial begin clk = 1'b1; forever #5 clk = ~clk; end /* Explore inputs */ initial begin $monitor("%d clk=%b, rdy=%b, fre=%b, q=%b", $realtime, clk, rdy, fre, q); rdy = 1'b0; fre = 1'b0; rst = 1'b1; #10 #10 #10 #10 #10 rst = 1'b0; rdy = 1'b1; fre = 1'b0; rdy = 1'b0; fre = 1'b0; rdy = 1'b0; fre = 1'b0; $finish;

end endmodule