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Jung-Suk Goo1, Richard Q. Williams2, Glenn O. Workman3, Qiang Chen4, Sungjae Lee2, and Edward J. Nowak2
1Technology 2SOI
Development Group, Advanced Micro Devices Inc. Compact Modeling Group, IBM Corporation 3CMOS Next Generation Design Foundations, Freescale Semiconductor Inc. 4Was with AMD Inc., now with Synopsys Inc.
Outline
Overview of the PD-SOI CMOS Technology Self-heating Model Parameter Calibration Flow Challenges in Measurement and Calibration Floating-Body Effects Modeling: History-Effect Body-Contacted Device Modeling Floating-Body Effects Simulation Issues Model Standardization Conclusion
45 nm 2GHz eDRAM
Domino AND +15% Domino MUX +25% SRAM 0%(bulk) +20% 20% 40%
Better control
Reduced Vt versus Lgate sensitivity Elimination of well-implant proximity effects (WPE) Natural isolation of auxiliary device elements (embedded DRAM, passives, high-voltage, and RF devices)
Better reliability
Reduced soft-error rates Elimination of latch-up
The chief difference of the PD-SOI is that the body of each SOI transistor is an independent 4th terminal for the device When absolutely needed, the body can be fixed to a chosen potential with a body tie
Transistor with body tie
However, in 99.9% of the chip, transistors will be operating as floating body devices
5 | IEEE SSC Society Fort Collins Chapter | Nov 10, 2008
IR
+ VR Drain
T0
Gate Source
Rth =
600
Device Turned On
RGate []
50
100
o
150
Chuck Temperature [ C]
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Self-Heating Removal
Channel Current
3.0 2.5
As Measured Self-Heating Removed
Parasitic Current
4.0
As Measured Self-Heating Removed
2.0 1.5 1.0 0.5 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2
3.0
2.0
1.0
0.0 0.0
-0.5
-1.0
-1.5
Addition of temperature node leads to simulation time increase, and, possibly, convergence issue Can disable self-heating mode for many high-performance logic products
Switching time is much faster than the thermal time constant Most analog blocks are operating at low enough bias range
8 | IEEE SSC Society Fort Collins Chapter | Nov 10, 2008
method 2
DC Body Currents Fitting (Idiode , Igb , Iii, I GIDL ) Body Effect & CV Fitting First -pass BC IV Fitting First -pass FB IV Fitting Refine Calibration
Check Circuit Response
Recenter Model
9 | IEEE SSC Society Fort Collins Chapter | Nov 10, 2008
Done
History Effect
Intrinsic MOSFET characteristics have only small impact on history effect
Except for the body-effect
Adjusting parasitic characteristics have huge impact on history effect and cause noticeable change in channel current
10 | IEEE SSC Society Fort Collins Chapter | Nov 10, 2008
P+ P-
N+ P w/ halo
nMOS
Bulk BT/SOI IGG IGB
-6 -7 -8 -9
pMOS
Bulk BT/SOI IGG IGB
-1.5
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
VG [V]
VG [V]
Solutions:
Selectively use specific regions Use bulk wafer
12 | IEEE SSC Society Fort Collins Chapter | Nov 10, 2008
Junction Capacitance
1.5
VDS=1.2V
CJunction [pF]
0.0 0.2 0.4 0.6
1.0
VT [V]
0.5
nMOSFET 2/0.0875m
-0.4
-0.2
Vbs [V]
Vbias [V]
Body bias can cause a fully-depleted body DBS1 Low-doped bridge region can introduce artifacts in measured data Solutions:
Selectively use specific regions Emphasize intrinsic response
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Slide 13 DBS1 I cannot change this graphic image, but it should not be hyphenated because the ly in fully = the hyphen in this use
David B. Schlosser, 9/13/2008
Transconductance (Gm)
88 86 84 82 80 3 10
Floating-Body
Body Resistance
Body-Contacted
10
10
10
10
10
10
10
10
Frequency [Hz]
Source
Drain
Diode leakages to
Source Drain Buried Oxide
Substrate
Definition of History-Effect
Definition of History-Effect
2nd
1st
1st switch : input transition after being held constant for a long time 2nd switch: input transition short time after the 1st switch
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Typical History-Effect
Evolution of Switching Delay
15 14 Delay/Stage [ps] 13 12
tr=tf =0.8ns
1st SW
2nd SW
10
-9
10
-8
10 10 Time [s]
10
-5
10
-4
Compression
Expansion
Heavily Loaded
100
IBM 9S 2 Mode l (1.2V 25C)
95
Delay/Stage [ps]
Delay/Stage [ps]
90 85 80 75 t =t =0.8ns r f 70
t
per
12.3%
1st t
rr
14.9%
1s t t
rr
2nd t
2nd t
ff
ff
4.5
per
step=100ps
s te p=100ps
4 -10 10
10
-9
10
-8
10 10 Time [s]
-7
-6
10
-5
10
-4
65 -10 10
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
Time [s]
C1
R1
C-Divider
C2
R2
Voltage
RC Decay
R-Divider
Time
Initial DC Conditions
Capacitive Coupling
Capacitive Coupling
Gate Coupling
Drain Coupling
Gate Coupling
Drain Coupling
Key Components
(Initial DC Condition)
1st SW
Igb,acc Idio,rev IGIDL II/I Idio,for
1st SW Initial
2nd SW
Igb,inv
Idio,for
KCL balance between forward and (reverse Idiode+IGIDL+II/I) Accumulation Igb is much smaller than forward Idiode
2nd SW Initial
KCL balance between forward Idiode*2 and inversion Igb
Key Components
VDD
(Capacitive Coupling)
Cj,rev
+
Cgb,acc
Vbs = VDD
Cj,for
Vb -
Key Components
(Body-Effect)
Vt vs. Vbody
Diode current Gate current Gate capacitance Junction capacitance
Vbody
Vt & speed
Body potential is established mostly by diode and gate characteristics (DC and AC) This body potential is translated into the actual switching performance by the body-effect (the main transfer function)
30 25 20
(1 -2 )/2 [%]
(1 -2 )/2 [%]
15 10 5 0 -5 -10 0.8
15 10 5 0 -5 -10
nd
nd
nd
nd
st
st
VDD [V]
VDD [V]
Cgb is critical for VDD dependence slope Igb became a major factor from 90 nm technology onward
Vb , 2 nd = VDD
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30 25 20
(1 -2 )/2 [%]
15 10 5 0 -5 -10 0.8
(1 -2 )/2 [%]
15 10 5 0 -5 -10
nd
nd
nd
nd
st
VDD [V]
st
VDD [V]
The diode current characteristic is the key characteristic dominating the VDD and temperature dependences of the history-effect
Proportional to forward Idiode Inversely proportional to reverse Idiode
10
5
Data Model
25 C o 100 C
1.2
1.4
1.6
VDD [V]
The measured history-effect can be successfully reproduced across a wide range of conditions when all the key components are properly modeled
IN
OUT
0.8V
1.0V
1.2V
1.5V
VDD [V]
Requires very high-accuracy test equipment Extremely low throughput Averaged over all stages, loosing variation details Large area Approximate precision
Floating Body
Reverse
VDS=0.1V
0.4 0.3
VT [V]
VDS=1.2V
Forward
nMOSFET 2/0.0875m
-0.4
-0.2
0.0
0.2
0.4
0.6
Vbs [V]
Sometimes the body effect is not able to fit for the entire range Then some range should be compromised Separating body-contacted and floating-body models maybe more desirable
33 | IEEE SSC Society Fort Collins Chapter | Nov 10, 2008
12
Coupling
(1 -2 )/2 [%]
Vbody [V]
nd
nd
Body RC Decay
st
0.4
0.5
10
10
10
10
Frequency [Hz]
Body-contacted PD-SOI circuit experiences the coupling effects exactly same as floating-body one Thus, it also exhibits history effect
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Physical
Ap+
Body
An+
Body
Agbcp
Source
Source
p+/p-
n+/p-
n+/p
n+/p
n+/p
n+/p
Rbodyext
Rbp
Rbodyext
Rbp
CGG
P+ STI P+ P-
N+ P w/ halo
-3
-2
-1
VG [V]
OverEstimated
QGB CG dVGS
QGC
VFB VDD
VT
VT
CG dVGS
Charge Ratio
Qp+ Qn+ Qp+/Qn+ Ratio
30
0.6
QGC
nd
20
0.4
Qp+/Qn+
~4.5%
10
0.2
7
Physical Agbcp=An++Ap+ W N=W P/2=1m 10 FET Segments
9
st
0.0
6 8 10
Agbcp=An+
10
10
10
VG [V]
Frequency [Hz]
Physical
BSIMSOI 4.1
Ap+
Body
An+
Agbcp2
Body
Agbcp
Source
Source
p+/p-
n+/p-
n+/p
p+/p
n+/p n+/p
Rbodyext
Rbp
Rbodyext
Rbp
Single Lumped
Rbodyext
RbpH/N
RbpH/N
Rbodyext
Rbp
Measurement
Model
DC Values
AC Values?
6 4 2 0 10
8
Technology-C WN=WP/2=5m
10
10
10
Frequency [Hz]
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Delay/Stage [ps]
10
-9
10
-8
10
-7
10
-6
1x10
-5
1x10
-4
Accuracy options
Vbody << VDD needs higher accuracy in voltage convergence criteria (vntol, etc.) Ibody << IDS needs tighter control on off-conductance of capacitors (gmindc) Stronger sensitivity of diode currents at low temperature needs special attention on numerical convergence criteria
43 | IEEE SSC Society Fort Collins Chapter | Nov 10, 2008
Harmonic balance
Solves Fourier series in f-domain Requires over-sampling and sufficient harmonics
st 55 1 SW
50
2 SW
nd
45 40 -9 10
10
-7
1x10
-5
10
-3
10
-1
Time [sec]
Charging/discharging
Circuits in sleep and wake-up modes
Steady-state
Critical for larger multi-input circuits, SRAMs, clock drivers, I/O, PLL, etc. Takes s~ms impractically long
44 | IEEE SSC Society Fort Collins Chapter | Nov 10, 2008
Model Standardization
Compact Modeling Council (CMC)
Hosted by the Government Electronics and Information Association (GEIA) Evaluates fundamental physics and numerical properties
Symmetry, continuity, convergence, and runtime
Benefits
Consistency in implementation on user side Recognition and funding to model developers Improved model accuracy and features
Through detailed review during the standardization process
Conclusion
Reviewed the current and future challenges in compact modeling, characterization, and circuit simulation of PD-SOI CMOS Floating-body effects
One of the main performance boosters Main complexity in PD-SOI compact modeling Measuring key components is challenging Nevertheless, mechanisms are well understood; thus, can be reproduced
PD-SOI simulation requires tighter convergence criteria and novel simulation techniques, mainly due to the floating-body effects Model standardization promotes implementation consistency and improved accuracy and features.
Acknowledgments
Advanced Semiconductor Technology Alliance (ASTA)
Technical contributions
K. Bernstein (IBM) B. Rice (Freescale)
Management support
A. Icel and N. Kepler (AMD) S. Springer and R. Wachnik (IBM) S. Jallepalli and M. Zunino (Freescale)